About the Execution of LoLA for RERS17pb113-PT-8
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16209.663 | 3600000.00 | 12114882.00 | 18585.50 | ?FF?T?F?F?F??FFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r326-tall-167889197900060.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RERS17pb113-PT-8, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889197900060
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 16M
-rw-r--r-- 1 mcc users 5.8K Feb 26 18:19 CTLCardinality.txt
-rw-r--r-- 1 mcc users 57K Feb 26 18:19 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 26 18:18 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 26 18:18 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 16:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 18:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 192K Feb 26 18:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 18:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 26 18:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 15M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-00
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-01
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-02
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-03
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-04
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-05
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-06
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-07
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-08
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-09
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-10
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-11
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-12
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-13
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-14
FORMULA_NAME RERS17pb113-PT-8-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1678944284144
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb113-PT-8
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT RERS17pb113-PT-8
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability
FORMULA RERS17pb113-PT-8-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-8-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-8-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-8-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-8-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-8-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-8-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-8-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-8-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 151536 kB
After kill :
MemTotal: 16393216 kB
MemFree: 15004592 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:499
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-8-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 21 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-8-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 26 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-8-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 31 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-8-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-02: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-8-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 36 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-8-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
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18 LTL EXCL 15/164 1/32 RERS17pb113-PT-8-LTLFireability-03 900 m, 47 m/sec, 899 t fired, .
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18 LTL EXCL 5/2348 1/5 RERS17pb113-PT-8-LTLFireability-03 201 m, -3740 m/sec, 200 t fired, .
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18 LTL EXCL 10/2348 1/5 RERS17pb113-PT-8-LTLFireability-03 400 m, 39 m/sec, 399 t fired, .
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18 LTL EXCL 15/2348 1/5 RERS17pb113-PT-8-LTLFireability-03 585 m, 37 m/sec, 584 t fired, .
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18 LTL EXCL 25/2348 1/5 RERS17pb113-PT-8-LTLFireability-03 950 m, 36 m/sec, 949 t fired, .
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18 LTL EXCL 30/2348 1/5 RERS17pb113-PT-8-LTLFireability-03 1076 m, 25 m/sec, 1075 t fired, .
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18 LTL EXCL 40/2348 1/5 RERS17pb113-PT-8-LTLFireability-03 1396 m, 34 m/sec, 1395 t fired, .
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18 LTL EXCL 5/2110 1/5 RERS17pb113-PT-8-LTLFireability-03 147 m, -1743 m/sec, 146 t fired, .
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18 LTL EXCL 40/2110 1/5 RERS17pb113-PT-8-LTLFireability-03 1083 m, 23 m/sec, 1082 t fired, .
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18 LTL EXCL 45/2110 1/5 RERS17pb113-PT-8-LTLFireability-03 1209 m, 25 m/sec, 1208 t fired, .
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18 LTL EXCL 50/2110 1/5 RERS17pb113-PT-8-LTLFireability-03 1332 m, 24 m/sec, 1331 t fired, .
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RERS17pb113-PT-8-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-8-LTLFireability-08: LTL false LTL model checker
RERS17pb113-PT-8-LTLFireability-10: CONJ false findpath
RERS17pb113-PT-8-LTLFireability-13: LTL false LTL model checker
RERS17pb113-PT-8-LTLFireability-14: CONJ false LTL model checker
RERS17pb113-PT-8-LTLFireability-15: LTL false LTL model checker
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RERS17pb113-PT-8-LTLFireability-00: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-8-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 LTL EXCL 55/796 1/5 RERS17pb113-PT-8-LTLFireability-03 1094 m, 18 m/sec, 1093 t fired, .
50 LTL EXCL 85/137 1/5 RERS17pb113-PT-8-LTLFireability-11 1594 m, 18 m/sec, 1593 t fired, .
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RERS17pb113-PT-8-LTLFireability-04: LTL true LTL model checker
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RERS17pb113-PT-8-LTLFireability-08: LTL false LTL model checker
RERS17pb113-PT-8-LTLFireability-10: CONJ false findpath
RERS17pb113-PT-8-LTLFireability-13: LTL false LTL model checker
RERS17pb113-PT-8-LTLFireability-14: CONJ false LTL model checker
RERS17pb113-PT-8-LTLFireability-15: LTL false LTL model checker
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RERS17pb113-PT-8-LTLFireability-00: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-8-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
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RERS17pb113-PT-8-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 LTL EXCL 60/796 1/5 RERS17pb113-PT-8-LTLFireability-03 1182 m, 17 m/sec, 1181 t fired, .
50 LTL EXCL 90/137 1/5 RERS17pb113-PT-8-LTLFireability-11 1686 m, 18 m/sec, 1685 t fired, .
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RERS17pb113-PT-8-LTLFireability-04: LTL true LTL model checker
RERS17pb113-PT-8-LTLFireability-06: LTL false LTL model checker
RERS17pb113-PT-8-LTLFireability-08: LTL false LTL model checker
RERS17pb113-PT-8-LTLFireability-10: CONJ false findpath
RERS17pb113-PT-8-LTLFireability-13: LTL false LTL model checker
RERS17pb113-PT-8-LTLFireability-14: CONJ false LTL model checker
RERS17pb113-PT-8-LTLFireability-15: LTL false LTL model checker
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RERS17pb113-PT-8-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-8-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 LTL EXCL 65/796 1/5 RERS17pb113-PT-8-LTLFireability-03 1280 m, 19 m/sec, 1279 t fired, .
50 LTL EXCL 95/137 1/5 RERS17pb113-PT-8-LTLFireability-11 1776 m, 18 m/sec, 1775 t fired, .
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RERS17pb113-PT-8-LTLFireability-13: LTL false LTL model checker
RERS17pb113-PT-8-LTLFireability-14: CONJ false LTL model checker
RERS17pb113-PT-8-LTLFireability-15: LTL false LTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 LTL EXCL 70/796 1/5 RERS17pb113-PT-8-LTLFireability-03 1372 m, 18 m/sec, 1371 t fired, .
50 LTL EXCL 100/137 1/5 RERS17pb113-PT-8-LTLFireability-11 1861 m, 17 m/sec, 1860 t fired, .
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RERS17pb113-PT-8-LTLFireability-04: LTL true LTL model checker
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RERS17pb113-PT-8-LTLFireability-13: LTL false LTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 LTL EXCL 75/796 1/5 RERS17pb113-PT-8-LTLFireability-03 1467 m, 19 m/sec, 1466 t fired, .
50 LTL EXCL 105/137 1/5 RERS17pb113-PT-8-LTLFireability-11 1942 m, 16 m/sec, 1941 t fired, .
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RERS17pb113-PT-8-LTLFireability-13: LTL false LTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 LTL EXCL 80/796 1/5 RERS17pb113-PT-8-LTLFireability-03 1563 m, 19 m/sec, 1562 t fired, .
50 LTL EXCL 110/137 1/5 RERS17pb113-PT-8-LTLFireability-11 2037 m, 19 m/sec, 2036 t fired, .
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RERS17pb113-PT-8-LTLFireability-10: CONJ false findpath
RERS17pb113-PT-8-LTLFireability-13: LTL false LTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 LTL EXCL 85/796 1/5 RERS17pb113-PT-8-LTLFireability-03 1657 m, 18 m/sec, 1656 t fired, .
50 LTL EXCL 115/137 1/5 RERS17pb113-PT-8-LTLFireability-11 2126 m, 17 m/sec, 2125 t fired, .
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-8"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-8, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889197900060"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-8.tgz
mv RERS17pb113-PT-8 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;