fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r326-tall-167889197900050
Last Updated
May 14, 2023

About the Execution of LoLA for RERS17pb113-PT-7

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16225.071 625176.00 1021704.00 90934.00 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889197900050.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RERS17pb113-PT-7, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889197900050
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 5.6K Feb 26 18:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K Feb 26 18:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 26 18:18 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 18:18 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 16:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 18:26 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 133K Feb 26 18:26 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.9K Feb 26 18:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 61K Feb 26 18:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 15M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-00
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-01
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-02
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-03
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-04
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-05
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-06
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-07
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-08
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-09
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-10
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-11
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-12
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-13
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-14
FORMULA_NAME RERS17pb113-PT-7-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678941039029

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb113-PT-7
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT RERS17pb113-PT-7
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

BK_STOP 1678941664205

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 71 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 76 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 13.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 81 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 86 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 91 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 96 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 101 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 106 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 111 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 116 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 121 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 126 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 131 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 136 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 141 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 146 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 151 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 156 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 161 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 166 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 171 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 13.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 176 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 181 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 186 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 191 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 196 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 201 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 206 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 211 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 216 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 221 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 11.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 226 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 231 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 236 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 241 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 246 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 251 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 256 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 13.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 261 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 266 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 271 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 276 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 281 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 286 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 291 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 296 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 301 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 306 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 311 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 316 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 321 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 326 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 331 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 336 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 341 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 346 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 351 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 356 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 361 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 366 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 371 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 376 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 381 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 386 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 391 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 396 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 401 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 406 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 411 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 416 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 421 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 426 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 431 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 127.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 436 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 441 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 446 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 15.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 451 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 456 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 461 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 466 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 478 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 483 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 491 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 496 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 503 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 508 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 514 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 519 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 524 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 529 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 534 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 539 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 545 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 550 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 555 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 560 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 565 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 570 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 575 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 580 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 585 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 590 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 595 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 600 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 605 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 610 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 615 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-7-CTLFireability-02: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-03: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-7-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-07: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-09: F 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-10: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-7-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-12: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-7-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 620 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 375 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-7"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-7, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889197900050"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-7.tgz
mv RERS17pb113-PT-7 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;