fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r326-tall-167889197900002
Last Updated
May 14, 2023

About the Execution of LoLA for RERS17pb113-PT-1

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16224.771 473134.00 739920.00 28583.80 ???????F???????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889197900002.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RERS17pb113-PT-1, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889197900002
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 4.6K Feb 26 18:12 CTLCardinality.txt
-rw-r--r-- 1 mcc users 42K Feb 26 18:12 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 26 18:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 18:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 21K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.4K Feb 26 18:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 96K Feb 26 18:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 18:13 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 65K Feb 26 18:13 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 15M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-00
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-01
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-02
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-03
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-04
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-05
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-06
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-07
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-08
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-09
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-10
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-11
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-12
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-13
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-14
FORMULA_NAME RERS17pb113-PT-1-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678929971803

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb113-PT-1
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT RERS17pb113-PT-1
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA RERS17pb113-PT-1-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678930444937

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-1-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-1-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-07: INITIAL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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RERS17pb113-PT-1-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-07: INITIAL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 218 secs. Pages in use: 0
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RERS17pb113-PT-1-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-07: INITIAL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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RERS17pb113-PT-1-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-07: INITIAL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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RERS17pb113-PT-1-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-07: INITIAL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-07: INITIAL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-07: INITIAL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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RERS17pb113-PT-1-CTLFireability-07: INITIAL false preprocessing

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RERS17pb113-PT-1-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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RERS17pb113-PT-1-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-06: EXEF 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-1-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-10: EFAG 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-1-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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RERS17pb113-PT-1-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
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13 CTL EXCL 16/201 1/32 RERS17pb113-PT-1-CTLFireability-04 101741 m, 20348 m/sec, 641095 t fired, .

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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 377 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-1"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-1, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889197900002"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-1.tgz
mv RERS17pb113-PT-1 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;