Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r295-tall-167873948500882.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is QuasiCertifProtocol-PT-18, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873948500882
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.8M
-rw-r--r-- 1 mcc users 42K Feb 26 01:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 289K Feb 26 01:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 26 01:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 26 01:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 16K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 89K Feb 26 01:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 593K Feb 26 01:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Feb 26 01:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 98K Feb 26 01:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 360K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-00
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-01
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-02
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-03
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-04
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-05
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-06
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-07
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-08
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-09
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-10
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-11
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-12
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-13
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-14
FORMULA_NAME QuasiCertifProtocol-PT-18-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678917814990

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=QuasiCertifProtocol-PT-18
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-15 22:03:36] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-15 22:03:36] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-15 22:03:36] [INFO ] Load time of PNML (sax parser for PT used): 74 ms
[2023-03-15 22:03:36] [INFO ] Transformed 1398 places.
[2023-03-15 22:03:36] [INFO ] Transformed 296 transitions.
[2023-03-15 22:03:36] [INFO ] Parsed PT model containing 1398 places and 296 transitions and 3119 arcs in 137 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
Support contains 999 out of 1398 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1398/1398 places, 296/296 transitions.
Reduce places removed 42 places and 0 transitions.
Iterating post reduction 0 with 42 rules applied. Total rules applied 42 place count 1356 transition count 296
Applied a total of 42 rules in 58 ms. Remains 1356 /1398 variables (removed 42) and now considering 296/296 (removed 0) transitions.
// Phase 1: matrix 296 rows 1356 cols
[2023-03-15 22:03:36] [INFO ] Computed 1062 place invariants in 71 ms
[2023-03-15 22:03:37] [INFO ] Implicit Places using invariants in 1047 ms returned []
[2023-03-15 22:03:37] [INFO ] Invariant cache hit.
[2023-03-15 22:03:38] [INFO ] Implicit Places using invariants and state equation in 953 ms returned [813, 814, 815, 816, 817, 818, 819, 820, 822, 926, 927, 929, 930, 931, 932, 933, 934]
Discarding 17 places :
Implicit Place search using SMT with State Equation took 2032 ms to find 17 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 1339/1398 places, 296/296 transitions.
Applied a total of 0 rules in 27 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 2118 ms. Remains : 1339/1398 places, 296/296 transitions.
Support contains 999 out of 1339 places after structural reductions.
[2023-03-15 22:03:39] [INFO ] Flatten gal took : 109 ms
[2023-03-15 22:03:39] [INFO ] Flatten gal took : 76 ms
[2023-03-15 22:03:39] [INFO ] Input system was already deterministic with 296 transitions.
Incomplete random walk after 10000 steps, including 442 resets, run finished after 532 ms. (steps per millisecond=18 ) properties (out of 59) seen :12
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 47) seen :0
Running SMT prover for 47 properties.
// Phase 1: matrix 296 rows 1339 cols
[2023-03-15 22:03:40] [INFO ] Computed 1045 place invariants in 25 ms
[2023-03-15 22:03:42] [INFO ] [Real]Absence check using 0 positive and 1045 generalized place invariants in 189 ms returned sat
[2023-03-15 22:03:42] [INFO ] After 1542ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:47
[2023-03-15 22:03:43] [INFO ] [Nat]Absence check using 0 positive and 1045 generalized place invariants in 183 ms returned sat
[2023-03-15 22:03:49] [INFO ] After 4662ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :44
[2023-03-15 22:03:54] [INFO ] After 9360ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :44
Attempting to minimize the solution found.
Minimization took 3884 ms.
[2023-03-15 22:03:57] [INFO ] After 15719ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :44
Fused 47 Parikh solutions to 40 different solutions.
Finished Parikh walk after 240 steps, including 1 resets, run visited all 9 properties in 7 ms. (steps per millisecond=34 )
Parikh walk visited 44 properties in 89 ms.
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-15 22:03:58] [INFO ] Flatten gal took : 46 ms
[2023-03-15 22:03:58] [INFO ] Flatten gal took : 46 ms
[2023-03-15 22:03:58] [INFO ] Input system was already deterministic with 296 transitions.
Support contains 637 out of 1339 places (down from 980) after GAL structural reductions.
Computed a total of 1339 stabilizing places and 296 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 1339 transition count 296
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
FORMULA QuasiCertifProtocol-PT-18-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 108 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 109 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:58] [INFO ] Flatten gal took : 30 ms
[2023-03-15 22:03:58] [INFO ] Flatten gal took : 31 ms
[2023-03-15 22:03:58] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 24 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:58] [INFO ] Flatten gal took : 28 ms
[2023-03-15 22:03:58] [INFO ] Flatten gal took : 29 ms
[2023-03-15 22:03:58] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 117 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 117 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:58] [INFO ] Flatten gal took : 28 ms
[2023-03-15 22:03:58] [INFO ] Flatten gal took : 32 ms
[2023-03-15 22:03:58] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 32 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:58] [INFO ] Flatten gal took : 26 ms
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 26 ms
[2023-03-15 22:03:59] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 34 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 24 ms
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 25 ms
[2023-03-15 22:03:59] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 31 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 24 ms
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 25 ms
[2023-03-15 22:03:59] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 30 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 23 ms
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 25 ms
[2023-03-15 22:03:59] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 28 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 24 ms
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 24 ms
[2023-03-15 22:03:59] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 31 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 23 ms
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 25 ms
[2023-03-15 22:03:59] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 34 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 23 ms
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 24 ms
[2023-03-15 22:03:59] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 32 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 23 ms
[2023-03-15 22:03:59] [INFO ] Flatten gal took : 24 ms
[2023-03-15 22:03:59] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 42 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 42 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:04:00] [INFO ] Flatten gal took : 24 ms
[2023-03-15 22:04:00] [INFO ] Flatten gal took : 25 ms
[2023-03-15 22:04:00] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Applied a total of 0 rules in 29 ms. Remains 1339 /1339 variables (removed 0) and now considering 296/296 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 1339/1339 places, 296/296 transitions.
[2023-03-15 22:04:00] [INFO ] Flatten gal took : 23 ms
[2023-03-15 22:04:00] [INFO ] Flatten gal took : 24 ms
[2023-03-15 22:04:00] [INFO ] Input system was already deterministic with 296 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Graph (complete) has 8709 edges and 1339 vertex of which 958 are kept as prefixes of interest. Removing 381 places using SCC suffix rule.11 ms
Discarding 381 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Discarding 37 places :
Symmetric choice reduction at 0 with 37 rule applications. Total rules 38 place count 920 transition count 219
Iterating global reduction 0 with 37 rules applied. Total rules applied 75 place count 920 transition count 219
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 76 place count 920 transition count 219
Applied a total of 76 rules in 192 ms. Remains 920 /1339 variables (removed 419) and now considering 219/296 (removed 77) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 193 ms. Remains : 920/1339 places, 219/296 transitions.
[2023-03-15 22:04:00] [INFO ] Flatten gal took : 16 ms
[2023-03-15 22:04:00] [INFO ] Flatten gal took : 16 ms
[2023-03-15 22:04:00] [INFO ] Input system was already deterministic with 219 transitions.
Incomplete random walk after 10000 steps, including 423 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 19 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2236843 steps, run timeout after 3001 ms. (steps per millisecond=745 ) properties seen :{}
Probabilistic random walk after 2236843 steps, saw 310655 distinct states, run finished after 3002 ms. (steps per millisecond=745 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 219 rows 920 cols
[2023-03-15 22:04:03] [INFO ] Computed 703 place invariants in 24 ms
[2023-03-15 22:04:03] [INFO ] [Real]Absence check using 0 positive and 703 generalized place invariants in 108 ms returned sat
[2023-03-15 22:04:04] [INFO ] After 218ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-15 22:04:04] [INFO ] After 270ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 26 ms.
[2023-03-15 22:04:04] [INFO ] After 543ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :1
Finished Parikh walk after 42 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=42 )
FORMULA QuasiCertifProtocol-PT-18-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 1 ms.
Starting structural reductions in SI_CTL mode, iteration 0 : 1339/1339 places, 296/296 transitions.
Graph (complete) has 8709 edges and 1339 vertex of which 958 are kept as prefixes of interest. Removing 381 places using SCC suffix rule.5 ms
Discarding 381 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Discarding 36 places :
Symmetric choice reduction at 0 with 36 rule applications. Total rules 37 place count 922 transition count 222
Iterating global reduction 0 with 36 rules applied. Total rules applied 73 place count 922 transition count 222
Applied a total of 73 rules in 70 ms. Remains 922 /1339 variables (removed 417) and now considering 222/296 (removed 74) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 70 ms. Remains : 922/1339 places, 222/296 transitions.
[2023-03-15 22:04:04] [INFO ] Flatten gal took : 16 ms
[2023-03-15 22:04:04] [INFO ] Flatten gal took : 17 ms
[2023-03-15 22:04:04] [INFO ] Input system was already deterministic with 222 transitions.
[2023-03-15 22:04:04] [INFO ] Flatten gal took : 27 ms
[2023-03-15 22:04:04] [INFO ] Flatten gal took : 27 ms
[2023-03-15 22:04:04] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2023-03-15 22:04:04] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1339 places, 296 transitions and 2925 arcs took 4 ms.
Total runtime 28039 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT QuasiCertifProtocol-PT-18
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-18-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678918254307

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 62 (type SKEL/SRCH) for 48 QuasiCertifProtocol-PT-18-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type EXCL) for 11 QuasiCertifProtocol-PT-18-CTLFireability-01
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 64 (type FNDP) for 11 QuasiCertifProtocol-PT-18-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 11 QuasiCertifProtocol-PT-18-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 66 (type EXCL) for QuasiCertifProtocol-PT-18-CTLFireability-01
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 64 (type FNDP) for QuasiCertifProtocol-PT-18-CTLFireability-01 (obsolete)
lola: CANCELED task # 65 (type EQUN) for QuasiCertifProtocol-PT-18-CTLFireability-01 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 64 (type FNDP) for QuasiCertifProtocol-PT-18-CTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/373/CTLFireability-65.sara.

lola: FINISHED task # 65 (type EQUN) for QuasiCertifProtocol-PT-18-CTLFireability-01
lola: result : true
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 16 (type EXCL) for 11 QuasiCertifProtocol-PT-18-CTLFireability-01
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 75 (type FNDP) for 0 QuasiCertifProtocol-PT-18-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type EQUN) for 0 QuasiCertifProtocol-PT-18-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 16 (type EXCL) for QuasiCertifProtocol-PT-18-CTLFireability-01
lola: result : false
lola: markings : 20
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 79 (type EXCL) for 0 QuasiCertifProtocol-PT-18-CTLFireability-00
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 75 (type FNDP) for QuasiCertifProtocol-PT-18-CTLFireability-00
lola: result : true
lola: fired transitions : 39
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 76 (type EQUN) for QuasiCertifProtocol-PT-18-CTLFireability-00 (obsolete)
lola: CANCELED task # 79 (type EXCL) for QuasiCertifProtocol-PT-18-CTLFireability-00 (obsolete)
lola: LAUNCH task # 22 (type EXCL) for 21 QuasiCertifProtocol-PT-18-CTLFireability-03
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for QuasiCertifProtocol-PT-18-CTLFireability-03
lola: result : true
lola: markings : 21
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 0 QuasiCertifProtocol-PT-18-CTLFireability-00
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for QuasiCertifProtocol-PT-18-CTLFireability-00
lola: result : true
lola: markings : 32
lola: fired transitions : 75
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 40 (type EXCL) for 39 QuasiCertifProtocol-PT-18-CTLFireability-10
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 62 (type SKEL/SRCH) for QuasiCertifProtocol-PT-18-CTLFireability-13
lola: result : false
lola: markings : 49217
lola: fired transitions : 205331
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 81 (type FNDP) for 48 QuasiCertifProtocol-PT-18-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type EQUN) for 48 QuasiCertifProtocol-PT-18-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SRCH) for 48 QuasiCertifProtocol-PT-18-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 84 (type SRCH) for QuasiCertifProtocol-PT-18-CTLFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 81 (type FNDP) for QuasiCertifProtocol-PT-18-CTLFireability-13
lola: result : true
lola: fired transitions : 38
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 82 (type EQUN) for QuasiCertifProtocol-PT-18-CTLFireability-13 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/373/CTLFireability-82.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 82 (type EQUN) for QuasiCertifProtocol-PT-18-CTLFireability-13
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-PT-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-13: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-18-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-09: EXEG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 4/326 3/32 QuasiCertifProtocol-PT-18-CTLFireability-10 316683 m, 63336 m/sec, 2148364 t fired, .

Time elapsed: 13 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 76 (type EQUN) for QuasiCertifProtocol-PT-18-CTLFireability-00
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-PT-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-13: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-18-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-09: EXEG 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 9/326 5/32 QuasiCertifProtocol-PT-18-CTLFireability-10 671154 m, 70894 m/sec, 4564148 t fired, .

Time elapsed: 18 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-PT-18-CTLFireability-03: CTL true CTL model checker
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QuasiCertifProtocol-PT-18-CTLFireability-09: EXEG true state space /EXEG
QuasiCertifProtocol-PT-18-CTLFireability-12: CTL true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-13: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-18-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-PT-18-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-PT-18-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-PT-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-PT-18-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 85/1093 31/32 QuasiCertifProtocol-PT-18-CTLFireability-02 5023077 m, 66129 m/sec, 39299422 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-PT-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-08: CTL false CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-09: EXEG true state space /EXEG
QuasiCertifProtocol-PT-18-CTLFireability-12: CTL true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-13: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-18-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-PT-18-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-PT-18-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-PT-18-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
QuasiCertifProtocol-PT-18-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: FINISHED task # 58 (type EXCL) for QuasiCertifProtocol-PT-18-CTLFireability-15
lola: result : true
lola: markings : 28
lola: fired transitions : 27
lola: time used : 0.000000
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-18-CTLFireability-00: DISJ true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-01: DISJ false DISJ
QuasiCertifProtocol-PT-18-CTLFireability-02: CTL unknown AGGR
QuasiCertifProtocol-PT-18-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-04: CTL unknown AGGR
QuasiCertifProtocol-PT-18-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-07: CTL false CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-08: CTL false CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-09: EXEG true state space /EXEG
QuasiCertifProtocol-PT-18-CTLFireability-10: CTL unknown AGGR
QuasiCertifProtocol-PT-18-CTLFireability-11: CTL unknown AGGR
QuasiCertifProtocol-PT-18-CTLFireability-12: CTL true CTL model checker
QuasiCertifProtocol-PT-18-CTLFireability-13: CONJ false findpath
QuasiCertifProtocol-PT-18-CTLFireability-15: DISJ true state space / EG


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-PT-18"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is QuasiCertifProtocol-PT-18, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873948500882"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-PT-18.tgz
mv QuasiCertifProtocol-PT-18 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;