fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r295-tall-167873948500866
Last Updated
May 14, 2023

About the Execution of LoLa+red for QuasiCertifProtocol-PT-06

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
732.119 76288.00 86085.00 479.50 TTTTFTFTFTFFFFFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r295-tall-167873948500866.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is QuasiCertifProtocol-PT-06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873948500866
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 868K
-rw-r--r-- 1 mcc users 16K Feb 26 01:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 131K Feb 26 01:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 26 01:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 26 01:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 16:37 LTLCardinality.txt
-rw-r--r-- 1 mcc users 36K Feb 25 16:37 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:37 LTLFireability.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:37 LTLFireability.xml
-rw-r--r-- 1 mcc users 37K Feb 26 01:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 300K Feb 26 01:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 26 01:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Feb 26 01:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 16:37 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.2K Feb 25 16:37 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 78K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-00
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-01
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-02
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-03
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-04
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-05
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-06
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-07
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-08
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-09
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-10
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-11
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-12
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-13
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-14
FORMULA_NAME QuasiCertifProtocol-PT-06-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678917123974

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=QuasiCertifProtocol-PT-06
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-15 21:52:05] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-15 21:52:05] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-15 21:52:05] [INFO ] Load time of PNML (sax parser for PT used): 43 ms
[2023-03-15 21:52:05] [INFO ] Transformed 270 places.
[2023-03-15 21:52:05] [INFO ] Transformed 116 transitions.
[2023-03-15 21:52:05] [INFO ] Parsed PT model containing 270 places and 116 transitions and 659 arcs in 100 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 249 out of 270 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 270/270 places, 116/116 transitions.
Reduce places removed 18 places and 0 transitions.
Iterating post reduction 0 with 18 rules applied. Total rules applied 18 place count 252 transition count 116
Applied a total of 18 rules in 14 ms. Remains 252 /270 variables (removed 18) and now considering 116/116 (removed 0) transitions.
// Phase 1: matrix 116 rows 252 cols
[2023-03-15 21:52:05] [INFO ] Computed 138 place invariants in 19 ms
[2023-03-15 21:52:05] [INFO ] Implicit Places using invariants in 294 ms returned []
[2023-03-15 21:52:05] [INFO ] Invariant cache hit.
[2023-03-15 21:52:05] [INFO ] Implicit Places using invariants and state equation in 120 ms returned []
Implicit Place search using SMT with State Equation took 437 ms to find 0 implicit places.
[2023-03-15 21:52:05] [INFO ] Invariant cache hit.
[2023-03-15 21:52:06] [INFO ] Dead Transitions using invariants and state equation in 112 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 252/270 places, 116/116 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 564 ms. Remains : 252/270 places, 116/116 transitions.
Support contains 249 out of 252 places after structural reductions.
[2023-03-15 21:52:06] [INFO ] Flatten gal took : 41 ms
[2023-03-15 21:52:06] [INFO ] Flatten gal took : 24 ms
[2023-03-15 21:52:06] [INFO ] Input system was already deterministic with 116 transitions.
Incomplete random walk after 10000 steps, including 983 resets, run finished after 572 ms. (steps per millisecond=17 ) properties (out of 67) seen :11
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1000 steps, including 10 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1000 steps, including 11 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 19 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 56) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 56) seen :2
Incomplete Best-First random walk after 1001 steps, including 16 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 16 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1000 steps, including 10 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 19 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 20 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1000 steps, including 17 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 22 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1000 steps, including 11 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 14 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 15 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1000 steps, including 15 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1000 steps, including 18 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 15 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 15 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 16 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 18 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 17 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 19 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 11 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1000 steps, including 16 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 54) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 54) seen :0
Running SMT prover for 54 properties.
[2023-03-15 21:52:07] [INFO ] Invariant cache hit.
[2023-03-15 21:52:07] [INFO ] [Real]Absence check using 0 positive and 138 generalized place invariants in 19 ms returned sat
[2023-03-15 21:52:07] [INFO ] After 396ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:54
[2023-03-15 21:52:08] [INFO ] [Nat]Absence check using 0 positive and 138 generalized place invariants in 19 ms returned sat
[2023-03-15 21:52:09] [INFO ] After 839ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :51
[2023-03-15 21:52:10] [INFO ] After 1823ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :51
Attempting to minimize the solution found.
Minimization took 691 ms.
[2023-03-15 21:52:11] [INFO ] After 3099ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :51
Fused 54 Parikh solutions to 42 different solutions.
Finished Parikh walk after 54 steps, including 0 resets, run visited all 2 properties in 1 ms. (steps per millisecond=54 )
Parikh walk visited 51 properties in 48 ms.
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 16 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 16 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
Computed a total of 252 stabilizing places and 116 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 252 transition count 116
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 2 formulas.
FORMULA QuasiCertifProtocol-PT-06-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA QuasiCertifProtocol-PT-06-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 10 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 10 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 10 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 16 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 10 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 10 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Graph (complete) has 733 edges and 252 vertex of which 244 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.3 ms
Discarding 8 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 12 ms. Remains 243 /252 variables (removed 9) and now considering 113/116 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 243/252 places, 113/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 8 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 9 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 113 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 3 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 8 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 9 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Graph (complete) has 733 edges and 252 vertex of which 244 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.2 ms
Discarding 8 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 244 transition count 114
Applied a total of 2 rules in 14 ms. Remains 244 /252 variables (removed 8) and now considering 114/116 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 244/252 places, 114/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 7 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 8 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 114 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 2 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 8 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 9 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Graph (complete) has 733 edges and 252 vertex of which 244 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 243 transition count 113
Applied a total of 2 rules in 21 ms. Remains 243 /252 variables (removed 9) and now considering 113/116 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 243/252 places, 113/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 8 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 8 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 113 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 4 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 7 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 7 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Graph (complete) has 733 edges and 252 vertex of which 244 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.2 ms
Discarding 8 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Applied a total of 1 rules in 8 ms. Remains 244 /252 variables (removed 8) and now considering 114/116 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 244/252 places, 114/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 6 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 7 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 114 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Graph (complete) has 733 edges and 252 vertex of which 244 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Reduce places removed 1 places and 1 transitions.
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 243 transition count 113
Applied a total of 2 rules in 15 ms. Remains 243 /252 variables (removed 9) and now considering 113/116 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 243/252 places, 113/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 6 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 6 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 113 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 3 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 6 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 6 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 4 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 5 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 6 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 3 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 5 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 6 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
Starting structural reductions in LTL mode, iteration 0 : 252/252 places, 116/116 transitions.
Applied a total of 0 rules in 5 ms. Remains 252 /252 variables (removed 0) and now considering 116/116 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 252/252 places, 116/116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 6 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 6 ms
[2023-03-15 21:52:11] [INFO ] Input system was already deterministic with 116 transitions.
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 9 ms
[2023-03-15 21:52:11] [INFO ] Flatten gal took : 9 ms
[2023-03-15 21:52:11] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2023-03-15 21:52:11] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 252 places, 116 transitions and 590 arcs took 2 ms.
Total runtime 6541 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT QuasiCertifProtocol-PT-06
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA QuasiCertifProtocol-PT-06-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678917200262

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 7 (type EXCL) for 6 QuasiCertifProtocol-PT-06-CTLFireability-02
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 7 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-02
lola: result : true
lola: markings : 220542
lola: fired transitions : 1552652
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 52 (type EXCL) for 47 QuasiCertifProtocol-PT-06-CTLFireability-14
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-14
lola: result : false
lola: markings : 2817
lola: fired transitions : 24323
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 QuasiCertifProtocol-PT-06-CTLFireability-13
lola: time limit : 256 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 3/256 3/32 QuasiCertifProtocol-PT-06-CTLFireability-13 546906 m, 109381 m/sec, 2845678 t fired, .

Time elapsed: 6 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 8/256 7/32 QuasiCertifProtocol-PT-06-CTLFireability-13 1314501 m, 153519 m/sec, 6936221 t fired, .

Time elapsed: 11 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 45 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-13
lola: result : false
lola: markings : 1595481
lola: fired transitions : 9041952
lola: time used : 10.000000
lola: memory pages used : 8
lola: LAUNCH task # 42 (type EXCL) for 41 QuasiCertifProtocol-PT-06-CTLFireability-12
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-12
lola: result : false
lola: markings : 2817
lola: fired transitions : 12161
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 QuasiCertifProtocol-PT-06-CTLFireability-11
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-11
lola: result : false
lola: markings : 193434
lola: fired transitions : 1014422
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 21 QuasiCertifProtocol-PT-06-CTLFireability-07
lola: time limit : 326 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-07
lola: result : true
lola: markings : 6409
lola: fired transitions : 21622
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 QuasiCertifProtocol-PT-06-CTLFireability-05
lola: time limit : 398 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-05
lola: result : true
lola: markings : 10
lola: fired transitions : 27
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 QuasiCertifProtocol-PT-06-CTLFireability-03
lola: time limit : 448 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 1/448 1/32 QuasiCertifProtocol-PT-06-CTLFireability-03 144919 m, 28983 m/sec, 1287565 t fired, .

Time elapsed: 16 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 6/448 4/32 QuasiCertifProtocol-PT-06-CTLFireability-03 822462 m, 135508 m/sec, 5944248 t fired, .

Time elapsed: 21 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 11/448 5/32 QuasiCertifProtocol-PT-06-CTLFireability-03 828826 m, 1272 m/sec, 10682359 t fired, .

Time elapsed: 26 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 10 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-03
lola: result : true
lola: markings : 871356
lola: fired transitions : 11237893
lola: time used : 12.000000
lola: memory pages used : 5
lola: LAUNCH task # 4 (type EXCL) for 3 QuasiCertifProtocol-PT-06-CTLFireability-01
lola: time limit : 510 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-01
lola: result : true
lola: markings : 193454
lola: fired transitions : 1014465
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 QuasiCertifProtocol-PT-06-CTLFireability-00
lola: time limit : 595 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-00
lola: result : true
lola: markings : 2824
lola: fired transitions : 12209
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 28 QuasiCertifProtocol-PT-06-CTLFireability-09
lola: time limit : 714 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 3/714 3/32 QuasiCertifProtocol-PT-06-CTLFireability-09 539682 m, 107936 m/sec, 2994784 t fired, .

Time elapsed: 31 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 8/714 6/32 QuasiCertifProtocol-PT-06-CTLFireability-09 1156722 m, 123408 m/sec, 7389653 t fired, .

Time elapsed: 36 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 13/714 9/32 QuasiCertifProtocol-PT-06-CTLFireability-09 1865503 m, 141756 m/sec, 11699990 t fired, .

Time elapsed: 41 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 18/714 10/32 QuasiCertifProtocol-PT-06-CTLFireability-09 2268362 m, 80571 m/sec, 15692163 t fired, .

Time elapsed: 46 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 31 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-09
lola: result : true
lola: markings : 2271960
lola: fired transitions : 15720024
lola: time used : 18.000000
lola: memory pages used : 10
lola: LAUNCH task # 19 (type EXCL) for 18 QuasiCertifProtocol-PT-06-CTLFireability-06
lola: time limit : 888 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-06
lola: result : false
lola: markings : 10
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 28 QuasiCertifProtocol-PT-06-CTLFireability-09
lola: time limit : 1184 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 0 1 0 3 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 5/1184 3/32 QuasiCertifProtocol-PT-06-CTLFireability-09 594327 m, 118865 m/sec, 4783399 t fired, .

Time elapsed: 51 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 0 1 0 3 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 10/1184 6/32 QuasiCertifProtocol-PT-06-CTLFireability-09 1105530 m, 102240 m/sec, 9505857 t fired, .

Time elapsed: 56 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 0 1 0 3 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 15/1184 8/32 QuasiCertifProtocol-PT-06-CTLFireability-09 1623943 m, 103682 m/sec, 14194892 t fired, .

Time elapsed: 61 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ 0 0 1 0 3 0 0 0
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 20/1184 10/32 QuasiCertifProtocol-PT-06-CTLFireability-09 2050199 m, 85251 m/sec, 18707466 t fired, .

Time elapsed: 66 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 33 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-09
lola: result : true
lola: markings : 2196377
lola: fired transitions : 20277827
lola: time used : 22.000000
lola: memory pages used : 11
lola: LAUNCH task # 36 (type EXCL) for 35 QuasiCertifProtocol-PT-06-CTLFireability-10
lola: time limit : 1766 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-10
lola: result : false
lola: markings : 19
lola: fired transitions : 40
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 QuasiCertifProtocol-PT-06-CTLFireability-04
lola: time limit : 3532 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for QuasiCertifProtocol-PT-06-CTLFireability-04
lola: result : false
lola: markings : 16337
lola: fired transitions : 61828
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
QuasiCertifProtocol-PT-06-CTLFireability-00: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-01: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-02: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-03: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-04: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-05: CTL true CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-06: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-07: DISJ true state space /EXEF
QuasiCertifProtocol-PT-06-CTLFireability-09: CONJ true CONJ
QuasiCertifProtocol-PT-06-CTLFireability-10: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-11: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-12: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-13: CTL false CTL model checker
QuasiCertifProtocol-PT-06-CTLFireability-14: CONJ false CTL model checker


Time elapsed: 68 secs. Pages in use: 11

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="QuasiCertifProtocol-PT-06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is QuasiCertifProtocol-PT-06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873948500866"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/QuasiCertifProtocol-PT-06.tgz
mv QuasiCertifProtocol-PT-06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;