fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r295-tall-167873948100570
Last Updated
May 14, 2023

About the Execution of LoLa+red for PolyORBLF-PT-S04J06T08

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3689.644 219346.00 239639.00 721.80 ??FT?TTFFFTTFFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r295-tall-167873948100570.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PolyORBLF-PT-S04J06T08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873948100570
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.0M
-rw-r--r-- 1 mcc users 20K Feb 26 14:13 CTLCardinality.txt
-rw-r--r-- 1 mcc users 115K Feb 26 14:13 CTLCardinality.xml
-rw-r--r-- 1 mcc users 74K Feb 26 14:10 CTLFireability.txt
-rw-r--r-- 1 mcc users 338K Feb 26 14:10 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 11K Feb 25 16:35 LTLCardinality.txt
-rw-r--r-- 1 mcc users 44K Feb 25 16:35 LTLCardinality.xml
-rw-r--r-- 1 mcc users 26K Feb 25 16:35 LTLFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 25 16:35 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 14:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 67K Feb 26 14:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 133K Feb 26 14:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 583K Feb 26 14:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:35 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.3K Feb 25 16:35 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 3.5M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-00
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-01
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-02
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-03
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-04
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-05
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-06
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-07
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-08
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-09
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-10
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-11
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-12
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-13
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-14
FORMULA_NAME PolyORBLF-PT-S04J06T08-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678867127930

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PolyORBLF-PT-S04J06T08
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-15 07:58:49] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-15 07:58:49] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-15 07:58:49] [INFO ] Load time of PNML (sax parser for PT used): 236 ms
[2023-03-15 07:58:49] [INFO ] Transformed 792 places.
[2023-03-15 07:58:49] [INFO ] Transformed 4268 transitions.
[2023-03-15 07:58:49] [INFO ] Parsed PT model containing 792 places and 4268 transitions and 28832 arcs in 331 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 22 ms.
[2023-03-15 07:58:49] [INFO ] Reduced 1768 identical enabling conditions.
[2023-03-15 07:58:49] [INFO ] Reduced 352 identical enabling conditions.
Ensure Unique test removed 2168 transitions
Reduce redundant transitions removed 2168 transitions.
Support contains 490 out of 792 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 792/792 places, 2100/2100 transitions.
Ensure Unique test removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 788 transition count 2100
Applied a total of 4 rules in 256 ms. Remains 788 /792 variables (removed 4) and now considering 2100/2100 (removed 0) transitions.
[2023-03-15 07:58:50] [INFO ] Flow matrix only has 2068 transitions (discarded 32 similar events)
// Phase 1: matrix 2068 rows 788 cols
[2023-03-15 07:58:50] [INFO ] Computed 54 place invariants in 137 ms
[2023-03-15 07:58:52] [INFO ] Dead Transitions using invariants and state equation in 2731 ms found 432 transitions.
Found 432 dead transitions using SMT.
Drop transitions removed 432 transitions
Dead transitions reduction (with SMT) triggered by suspicious arc values removed 432 transitions.
[2023-03-15 07:58:52] [INFO ] Flow matrix only has 1636 transitions (discarded 32 similar events)
// Phase 1: matrix 1636 rows 788 cols
[2023-03-15 07:58:52] [INFO ] Computed 54 place invariants in 58 ms
[2023-03-15 07:58:53] [INFO ] Implicit Places using invariants in 381 ms returned []
[2023-03-15 07:58:53] [INFO ] Flow matrix only has 1636 transitions (discarded 32 similar events)
[2023-03-15 07:58:53] [INFO ] Invariant cache hit.
[2023-03-15 07:58:54] [INFO ] State equation strengthened by 160 read => feed constraints.
[2023-03-15 07:59:02] [INFO ] Implicit Places using invariants and state equation in 9393 ms returned []
Implicit Place search using SMT with State Equation took 9780 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 788/792 places, 1668/2100 transitions.
Applied a total of 0 rules in 21 ms. Remains 788 /788 variables (removed 0) and now considering 1668/1668 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12818 ms. Remains : 788/792 places, 1668/2100 transitions.
Support contains 490 out of 788 places after structural reductions.
[2023-03-15 07:59:02] [INFO ] Flatten gal took : 160 ms
[2023-03-15 07:59:03] [INFO ] Flatten gal took : 125 ms
[2023-03-15 07:59:03] [INFO ] Input system was already deterministic with 1668 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 645 ms. (steps per millisecond=15 ) properties (out of 76) seen :45
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 53 ms. (steps per millisecond=18 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 31) seen :0
Running SMT prover for 31 properties.
[2023-03-15 07:59:04] [INFO ] Flow matrix only has 1636 transitions (discarded 32 similar events)
[2023-03-15 07:59:04] [INFO ] Invariant cache hit.
[2023-03-15 07:59:06] [INFO ] [Real]Absence check using 17 positive place invariants in 19 ms returned sat
[2023-03-15 07:59:06] [INFO ] [Real]Absence check using 17 positive and 37 generalized place invariants in 41 ms returned sat
[2023-03-15 07:59:06] [INFO ] After 755ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:30
[2023-03-15 07:59:06] [INFO ] [Nat]Absence check using 17 positive place invariants in 6 ms returned sat
[2023-03-15 07:59:06] [INFO ] [Nat]Absence check using 17 positive and 37 generalized place invariants in 52 ms returned sat
[2023-03-15 07:59:17] [INFO ] After 10827ms SMT Verify possible using all constraints in natural domain returned unsat :30 sat :0
Fused 31 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 5 out of 788 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Drop transitions removed 64 transitions
Trivial Post-agglo rules discarded 64 transitions
Performed 64 trivial Post agglomeration. Transition count delta: 64
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 788 transition count 1604
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 1 with 64 rules applied. Total rules applied 128 place count 724 transition count 1604
Performed 96 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 96 Pre rules applied. Total rules applied 128 place count 724 transition count 1508
Deduced a syphon composed of 96 places in 2 ms
Reduce places removed 96 places and 0 transitions.
Iterating global reduction 2 with 192 rules applied. Total rules applied 320 place count 628 transition count 1508
Performed 80 Post agglomeration using F-continuation condition.Transition count delta: 80
Deduced a syphon composed of 80 places in 2 ms
Reduce places removed 80 places and 0 transitions.
Iterating global reduction 2 with 160 rules applied. Total rules applied 480 place count 548 transition count 1428
Free-agglomeration rule (complex) applied 23 times.
Iterating global reduction 2 with 23 rules applied. Total rules applied 503 place count 548 transition count 1405
Reduce places removed 23 places and 0 transitions.
Iterating post reduction 2 with 23 rules applied. Total rules applied 526 place count 525 transition count 1405
Applied a total of 526 rules in 217 ms. Remains 525 /788 variables (removed 263) and now considering 1405/1668 (removed 263) transitions.
[2023-03-15 07:59:17] [INFO ] Flow matrix only has 1373 transitions (discarded 32 similar events)
// Phase 1: matrix 1373 rows 525 cols
[2023-03-15 07:59:17] [INFO ] Computed 54 place invariants in 23 ms
[2023-03-15 07:59:18] [INFO ] Dead Transitions using invariants and state equation in 1081 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1301 ms. Remains : 525/788 places, 1405/1668 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 1) seen :0
Finished probabilistic random walk after 93241 steps, run visited all 1 properties in 1649 ms. (steps per millisecond=56 )
Probabilistic random walk after 93241 steps, saw 69702 distinct states, run finished after 1650 ms. (steps per millisecond=56 ) properties seen :1
Successfully simplified 30 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-15 07:59:20] [INFO ] Flatten gal took : 78 ms
[2023-03-15 07:59:20] [INFO ] Flatten gal took : 83 ms
[2023-03-15 07:59:20] [INFO ] Input system was already deterministic with 1668 transitions.
Support contains 300 out of 788 places (down from 308) after GAL structural reductions.
FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 780 transition count 1660
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 780 transition count 1660
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 24 place count 772 transition count 1652
Iterating global reduction 0 with 8 rules applied. Total rules applied 32 place count 772 transition count 1652
Applied a total of 32 rules in 76 ms. Remains 772 /788 variables (removed 16) and now considering 1652/1668 (removed 16) transitions.
[2023-03-15 07:59:20] [INFO ] Flow matrix only has 1620 transitions (discarded 32 similar events)
// Phase 1: matrix 1620 rows 772 cols
[2023-03-15 07:59:20] [INFO ] Computed 54 place invariants in 37 ms
[2023-03-15 07:59:22] [INFO ] Dead Transitions using invariants and state equation in 2086 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2164 ms. Remains : 772/788 places, 1652/1668 transitions.
[2023-03-15 07:59:22] [INFO ] Flatten gal took : 60 ms
[2023-03-15 07:59:23] [INFO ] Flatten gal took : 61 ms
[2023-03-15 07:59:23] [INFO ] Input system was already deterministic with 1652 transitions.
Starting structural reductions in LTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 780 transition count 1660
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 780 transition count 1660
Applied a total of 16 rules in 25 ms. Remains 780 /788 variables (removed 8) and now considering 1660/1668 (removed 8) transitions.
[2023-03-15 07:59:23] [INFO ] Flow matrix only has 1628 transitions (discarded 32 similar events)
// Phase 1: matrix 1628 rows 780 cols
[2023-03-15 07:59:23] [INFO ] Computed 54 place invariants in 30 ms
[2023-03-15 07:59:25] [INFO ] Dead Transitions using invariants and state equation in 2126 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2153 ms. Remains : 780/788 places, 1660/1668 transitions.
[2023-03-15 07:59:25] [INFO ] Flatten gal took : 55 ms
[2023-03-15 07:59:25] [INFO ] Flatten gal took : 63 ms
[2023-03-15 07:59:25] [INFO ] Input system was already deterministic with 1660 transitions.
Starting structural reductions in LTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 780 transition count 1660
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 780 transition count 1660
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 24 place count 772 transition count 1652
Iterating global reduction 0 with 8 rules applied. Total rules applied 32 place count 772 transition count 1652
Applied a total of 32 rules in 64 ms. Remains 772 /788 variables (removed 16) and now considering 1652/1668 (removed 16) transitions.
[2023-03-15 07:59:25] [INFO ] Flow matrix only has 1620 transitions (discarded 32 similar events)
// Phase 1: matrix 1620 rows 772 cols
[2023-03-15 07:59:25] [INFO ] Computed 54 place invariants in 40 ms
[2023-03-15 07:59:27] [INFO ] Dead Transitions using invariants and state equation in 2120 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2195 ms. Remains : 772/788 places, 1652/1668 transitions.
[2023-03-15 07:59:27] [INFO ] Flatten gal took : 73 ms
[2023-03-15 07:59:28] [INFO ] Flatten gal took : 64 ms
[2023-03-15 07:59:28] [INFO ] Input system was already deterministic with 1652 transitions.
Starting structural reductions in LTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 780 transition count 1660
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 780 transition count 1660
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 24 place count 772 transition count 1652
Iterating global reduction 0 with 8 rules applied. Total rules applied 32 place count 772 transition count 1652
Applied a total of 32 rules in 75 ms. Remains 772 /788 variables (removed 16) and now considering 1652/1668 (removed 16) transitions.
[2023-03-15 07:59:28] [INFO ] Flow matrix only has 1620 transitions (discarded 32 similar events)
[2023-03-15 07:59:28] [INFO ] Invariant cache hit.
[2023-03-15 07:59:30] [INFO ] Dead Transitions using invariants and state equation in 2135 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2226 ms. Remains : 772/788 places, 1652/1668 transitions.
[2023-03-15 07:59:30] [INFO ] Flatten gal took : 46 ms
[2023-03-15 07:59:30] [INFO ] Flatten gal took : 53 ms
[2023-03-15 07:59:30] [INFO ] Input system was already deterministic with 1652 transitions.
Starting structural reductions in LTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Applied a total of 0 rules in 9 ms. Remains 788 /788 variables (removed 0) and now considering 1668/1668 (removed 0) transitions.
[2023-03-15 07:59:30] [INFO ] Flow matrix only has 1636 transitions (discarded 32 similar events)
// Phase 1: matrix 1636 rows 788 cols
[2023-03-15 07:59:30] [INFO ] Computed 54 place invariants in 31 ms
[2023-03-15 07:59:32] [INFO ] Dead Transitions using invariants and state equation in 2213 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2222 ms. Remains : 788/788 places, 1668/1668 transitions.
[2023-03-15 07:59:32] [INFO ] Flatten gal took : 66 ms
[2023-03-15 07:59:32] [INFO ] Flatten gal took : 54 ms
[2023-03-15 07:59:33] [INFO ] Input system was already deterministic with 1668 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Drop transitions removed 56 transitions
Trivial Post-agglo rules discarded 56 transitions
Performed 56 trivial Post agglomeration. Transition count delta: 56
Iterating post reduction 0 with 56 rules applied. Total rules applied 56 place count 788 transition count 1612
Reduce places removed 56 places and 0 transitions.
Iterating post reduction 1 with 56 rules applied. Total rules applied 112 place count 732 transition count 1612
Performed 104 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 104 Pre rules applied. Total rules applied 112 place count 732 transition count 1508
Deduced a syphon composed of 104 places in 1 ms
Reduce places removed 104 places and 0 transitions.
Iterating global reduction 2 with 208 rules applied. Total rules applied 320 place count 628 transition count 1508
Discarding 8 places :
Symmetric choice reduction at 2 with 8 rule applications. Total rules 328 place count 620 transition count 1500
Iterating global reduction 2 with 8 rules applied. Total rules applied 336 place count 620 transition count 1500
Performed 72 Post agglomeration using F-continuation condition.Transition count delta: 72
Deduced a syphon composed of 72 places in 1 ms
Reduce places removed 72 places and 0 transitions.
Iterating global reduction 2 with 144 rules applied. Total rules applied 480 place count 548 transition count 1428
Applied a total of 480 rules in 96 ms. Remains 548 /788 variables (removed 240) and now considering 1428/1668 (removed 240) transitions.
[2023-03-15 07:59:33] [INFO ] Flow matrix only has 1396 transitions (discarded 32 similar events)
// Phase 1: matrix 1396 rows 548 cols
[2023-03-15 07:59:33] [INFO ] Computed 54 place invariants in 26 ms
[2023-03-15 07:59:34] [INFO ] Dead Transitions using invariants and state equation in 1113 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1210 ms. Remains : 548/788 places, 1428/1668 transitions.
[2023-03-15 07:59:34] [INFO ] Flatten gal took : 41 ms
[2023-03-15 07:59:34] [INFO ] Flatten gal took : 45 ms
[2023-03-15 07:59:34] [INFO ] Input system was already deterministic with 1428 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Drop transitions removed 64 transitions
Trivial Post-agglo rules discarded 64 transitions
Performed 64 trivial Post agglomeration. Transition count delta: 64
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 788 transition count 1604
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 1 with 64 rules applied. Total rules applied 128 place count 724 transition count 1604
Performed 95 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 95 Pre rules applied. Total rules applied 128 place count 724 transition count 1509
Deduced a syphon composed of 95 places in 0 ms
Reduce places removed 95 places and 0 transitions.
Iterating global reduction 2 with 190 rules applied. Total rules applied 318 place count 629 transition count 1509
Performed 80 Post agglomeration using F-continuation condition.Transition count delta: 80
Deduced a syphon composed of 80 places in 1 ms
Reduce places removed 80 places and 0 transitions.
Iterating global reduction 2 with 160 rules applied. Total rules applied 478 place count 549 transition count 1429
Applied a total of 478 rules in 80 ms. Remains 549 /788 variables (removed 239) and now considering 1429/1668 (removed 239) transitions.
[2023-03-15 07:59:34] [INFO ] Flow matrix only has 1397 transitions (discarded 32 similar events)
// Phase 1: matrix 1397 rows 549 cols
[2023-03-15 07:59:34] [INFO ] Computed 54 place invariants in 33 ms
[2023-03-15 07:59:35] [INFO ] Dead Transitions using invariants and state equation in 1072 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1155 ms. Remains : 549/788 places, 1429/1668 transitions.
[2023-03-15 07:59:35] [INFO ] Flatten gal took : 43 ms
[2023-03-15 07:59:35] [INFO ] Flatten gal took : 46 ms
[2023-03-15 07:59:35] [INFO ] Input system was already deterministic with 1429 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Drop transitions removed 72 transitions
Trivial Post-agglo rules discarded 72 transitions
Performed 72 trivial Post agglomeration. Transition count delta: 72
Iterating post reduction 0 with 72 rules applied. Total rules applied 72 place count 788 transition count 1596
Reduce places removed 72 places and 0 transitions.
Iterating post reduction 1 with 72 rules applied. Total rules applied 144 place count 716 transition count 1596
Performed 96 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 96 Pre rules applied. Total rules applied 144 place count 716 transition count 1500
Deduced a syphon composed of 96 places in 1 ms
Reduce places removed 96 places and 0 transitions.
Iterating global reduction 2 with 192 rules applied. Total rules applied 336 place count 620 transition count 1500
Performed 80 Post agglomeration using F-continuation condition.Transition count delta: 80
Deduced a syphon composed of 80 places in 1 ms
Reduce places removed 80 places and 0 transitions.
Iterating global reduction 2 with 160 rules applied. Total rules applied 496 place count 540 transition count 1420
Applied a total of 496 rules in 81 ms. Remains 540 /788 variables (removed 248) and now considering 1420/1668 (removed 248) transitions.
[2023-03-15 07:59:35] [INFO ] Flow matrix only has 1388 transitions (discarded 32 similar events)
// Phase 1: matrix 1388 rows 540 cols
[2023-03-15 07:59:35] [INFO ] Computed 54 place invariants in 26 ms
[2023-03-15 07:59:36] [INFO ] Dead Transitions using invariants and state equation in 1093 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1175 ms. Remains : 540/788 places, 1420/1668 transitions.
[2023-03-15 07:59:37] [INFO ] Flatten gal took : 42 ms
[2023-03-15 07:59:37] [INFO ] Flatten gal took : 43 ms
[2023-03-15 07:59:37] [INFO ] Input system was already deterministic with 1420 transitions.
Starting structural reductions in LTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 780 transition count 1660
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 780 transition count 1660
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 24 place count 772 transition count 1652
Iterating global reduction 0 with 8 rules applied. Total rules applied 32 place count 772 transition count 1652
Applied a total of 32 rules in 28 ms. Remains 772 /788 variables (removed 16) and now considering 1652/1668 (removed 16) transitions.
[2023-03-15 07:59:37] [INFO ] Flow matrix only has 1620 transitions (discarded 32 similar events)
// Phase 1: matrix 1620 rows 772 cols
[2023-03-15 07:59:37] [INFO ] Computed 54 place invariants in 31 ms
[2023-03-15 07:59:39] [INFO ] Dead Transitions using invariants and state equation in 2194 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2224 ms. Remains : 772/788 places, 1652/1668 transitions.
[2023-03-15 07:59:39] [INFO ] Flatten gal took : 47 ms
[2023-03-15 07:59:39] [INFO ] Flatten gal took : 52 ms
[2023-03-15 07:59:39] [INFO ] Input system was already deterministic with 1652 transitions.
Starting structural reductions in LTL mode, iteration 0 : 788/788 places, 1668/1668 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 780 transition count 1660
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 780 transition count 1660
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 24 place count 772 transition count 1652
Iterating global reduction 0 with 8 rules applied. Total rules applied 32 place count 772 transition count 1652
Applied a total of 32 rules in 27 ms. Remains 772 /788 variables (removed 16) and now considering 1652/1668 (removed 16) transitions.
[2023-03-15 07:59:39] [INFO ] Flow matrix only has 1620 transitions (discarded 32 similar events)
[2023-03-15 07:59:39] [INFO ] Invariant cache hit.
[2023-03-15 07:59:41] [INFO ] Dead Transitions using invariants and state equation in 2184 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2213 ms. Remains : 772/788 places, 1652/1668 transitions.
[2023-03-15 07:59:41] [INFO ] Flatten gal took : 49 ms
[2023-03-15 07:59:41] [INFO ] Flatten gal took : 53 ms
[2023-03-15 07:59:42] [INFO ] Input system was already deterministic with 1652 transitions.
[2023-03-15 07:59:42] [INFO ] Flatten gal took : 62 ms
[2023-03-15 07:59:42] [INFO ] Flatten gal took : 62 ms
[2023-03-15 07:59:42] [INFO ] Export to MCC of 10 properties in file /home/mcc/execution/CTLFireability.sr.xml took 11 ms.
[2023-03-15 07:59:42] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 788 places, 1668 transitions and 7428 arcs took 8 ms.
Total runtime 53011 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PolyORBLF-PT-S04J06T08
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S04J06T08-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678867347276

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 22 (type EXCL) for 21 PolyORBLF-PT-S04J06T08-CTLFireability-09
lola: time limit : 358 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 22 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-09
lola: result : false
lola: markings : 885
lola: fired transitions : 886
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 PolyORBLF-PT-S04J06T08-CTLFireability-06
lola: time limit : 397 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-06
lola: result : true
lola: markings : 947
lola: fired transitions : 2802
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 13 (type EXCL) for 12 PolyORBLF-PT-S04J06T08-CTLFireability-04
lola: time limit : 447 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 4/447 4/32 PolyORBLF-PT-S04J06T08-CTLFireability-04 260149 m, 52029 m/sec, 594978 t fired, .

Time elapsed: 24 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 9/447 8/32 PolyORBLF-PT-S04J06T08-CTLFireability-04 600632 m, 68096 m/sec, 1389260 t fired, .

Time elapsed: 29 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 14/447 13/32 PolyORBLF-PT-S04J06T08-CTLFireability-04 925005 m, 64874 m/sec, 2185628 t fired, .

Time elapsed: 34 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 19/447 17/32 PolyORBLF-PT-S04J06T08-CTLFireability-04 1252924 m, 65583 m/sec, 2972365 t fired, .

Time elapsed: 39 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 24/447 21/32 PolyORBLF-PT-S04J06T08-CTLFireability-04 1570419 m, 63499 m/sec, 3749893 t fired, .

Time elapsed: 44 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 29/447 25/32 PolyORBLF-PT-S04J06T08-CTLFireability-04 1889444 m, 63805 m/sec, 4533508 t fired, .

Time elapsed: 49 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 34/447 29/32 PolyORBLF-PT-S04J06T08-CTLFireability-04 2193415 m, 60794 m/sec, 5317228 t fired, .

Time elapsed: 54 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 10
lola: CANCELED task # 13 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 59 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
lola: LAUNCH task # 28 (type EXCL) for 27 PolyORBLF-PT-S04J06T08-CTLFireability-14
lola: time limit : 505 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-14
lola: result : true
lola: markings : 319519
lola: fired transitions : 336907
lola: time used : 2.000000
lola: memory pages used : 5
lola: LAUNCH task # 25 (type EXCL) for 24 PolyORBLF-PT-S04J06T08-CTLFireability-11
lola: time limit : 589 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-11
lola: result : true
lola: markings : 40811
lola: fired transitions : 82584
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 PolyORBLF-PT-S04J06T08-CTLFireability-03
lola: time limit : 707 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-03
lola: result : true
lola: markings : 90
lola: fired transitions : 93
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 PolyORBLF-PT-S04J06T08-CTLFireability-02
lola: time limit : 884 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-02
lola: result : false
lola: markings : 21392
lola: fired transitions : 45291
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 PolyORBLF-PT-S04J06T08-CTLFireability-01
lola: time limit : 1179 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 2/1179 2/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 159031 m, 31806 m/sec, 322556 t fired, .

Time elapsed: 64 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 7/1179 6/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 460883 m, 60370 m/sec, 1330133 t fired, .

Time elapsed: 69 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 12/1179 9/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 737163 m, 55256 m/sec, 2329541 t fired, .

Time elapsed: 74 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 17/1179 12/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 999885 m, 52544 m/sec, 3340821 t fired, .

Time elapsed: 79 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 22/1179 16/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 1279986 m, 56020 m/sec, 4338825 t fired, .

Time elapsed: 84 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 27/1179 19/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 1558165 m, 55635 m/sec, 5340624 t fired, .

Time elapsed: 89 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 32/1179 23/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 1844206 m, 57208 m/sec, 6342365 t fired, .

Time elapsed: 94 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 37/1179 26/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 2104818 m, 52122 m/sec, 7353680 t fired, .

Time elapsed: 99 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 42/1179 29/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 2381509 m, 55338 m/sec, 8343299 t fired, .

Time elapsed: 104 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 47/1179 32/32 PolyORBLF-PT-S04J06T08-CTLFireability-01 2659413 m, 55580 m/sec, 9343608 t fired, .

Time elapsed: 109 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
lola: CANCELED task # 4 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 114 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
lola: LAUNCH task # 1 (type EXCL) for 0 PolyORBLF-PT-S04J06T08-CTLFireability-00
lola: time limit : 1743 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/1743 4/32 PolyORBLF-PT-S04J06T08-CTLFireability-00 360484 m, 72096 m/sec, 813736 t fired, .

Time elapsed: 119 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/1743 8/32 PolyORBLF-PT-S04J06T08-CTLFireability-00 696302 m, 67163 m/sec, 1647695 t fired, .

Time elapsed: 124 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/1743 11/32 PolyORBLF-PT-S04J06T08-CTLFireability-00 1026468 m, 66033 m/sec, 2482456 t fired, .

Time elapsed: 129 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/1743 14/32 PolyORBLF-PT-S04J06T08-CTLFireability-00 1360849 m, 66876 m/sec, 3316138 t fired, .

Time elapsed: 134 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/1743 18/32 PolyORBLF-PT-S04J06T08-CTLFireability-00 1692722 m, 66374 m/sec, 4151491 t fired, .

Time elapsed: 139 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/1743 21/32 PolyORBLF-PT-S04J06T08-CTLFireability-00 2018447 m, 65145 m/sec, 4986157 t fired, .

Time elapsed: 144 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/1743 24/32 PolyORBLF-PT-S04J06T08-CTLFireability-00 2342959 m, 64902 m/sec, 5814693 t fired, .

Time elapsed: 149 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/1743 27/32 PolyORBLF-PT-S04J06T08-CTLFireability-00 2659612 m, 63330 m/sec, 6653389 t fired, .

Time elapsed: 154 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/1743 30/32 PolyORBLF-PT-S04J06T08-CTLFireability-00 2977424 m, 63562 m/sec, 7487306 t fired, .

Time elapsed: 159 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
lola: CANCELED task # 1 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 164 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
lola: LAUNCH task # 19 (type EXCL) for 18 PolyORBLF-PT-S04J06T08-CTLFireability-08
lola: time limit : 3436 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for PolyORBLF-PT-S04J06T08-CTLFireability-08
lola: result : false
lola: markings : 887
lola: fired transitions : 2662
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 10

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S04J06T08-CTLFireability-00: CTL unknown AGGR
PolyORBLF-PT-S04J06T08-CTLFireability-01: CTL unknown AGGR
PolyORBLF-PT-S04J06T08-CTLFireability-02: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-03: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-04: CTL unknown AGGR
PolyORBLF-PT-S04J06T08-CTLFireability-06: EGEF true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-08: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-09: CTL false CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-11: CTL true CTL model checker
PolyORBLF-PT-S04J06T08-CTLFireability-14: CTL true CTL model checker


Time elapsed: 164 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PolyORBLF-PT-S04J06T08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PolyORBLF-PT-S04J06T08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873948100570"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PolyORBLF-PT-S04J06T08.tgz
mv PolyORBLF-PT-S04J06T08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;