About the Execution of LoLa+red for PhaseVariation-PT-D10CS100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16219.628 | 1604354.00 | 4437713.00 | 15595.90 | FTTTT?T??T?T?TTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r295-tall-167873947300042.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PhaseVariation-PT-D10CS100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r295-tall-167873947300042
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.4M
-rw-r--r-- 1 mcc users 8.3K Feb 26 15:13 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 26 15:13 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Feb 26 15:12 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 15:12 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 16:32 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:32 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:32 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 15:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 121K Feb 26 15:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 17K Feb 26 15:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Feb 26 15:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:32 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:32 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 2.9M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-00
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-01
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-02
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-03
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-04
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-05
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-06
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-07
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-08
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-09
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-10
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-11
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-12
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-13
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-14
FORMULA_NAME PhaseVariation-PT-D10CS100-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678777615971
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PhaseVariation-PT-D10CS100
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 07:06:57] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 07:06:57] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 07:06:57] [INFO ] Load time of PNML (sax parser for PT used): 229 ms
[2023-03-14 07:06:57] [INFO ] Transformed 302 places.
[2023-03-14 07:06:57] [INFO ] Transformed 3137 transitions.
[2023-03-14 07:06:57] [INFO ] Parsed PT model containing 302 places and 3137 transitions and 21755 arcs in 420 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Support contains 170 out of 302 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 46 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:06:58] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
// Phase 1: matrix 201 rows 302 cols
[2023-03-14 07:06:58] [INFO ] Computed 101 place invariants in 19 ms
[2023-03-14 07:06:59] [INFO ] Dead Transitions using invariants and state equation in 1404 ms found 0 transitions.
[2023-03-14 07:06:59] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:06:59] [INFO ] Invariant cache hit.
[2023-03-14 07:06:59] [INFO ] Implicit Places using invariants in 163 ms returned []
[2023-03-14 07:06:59] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:06:59] [INFO ] Invariant cache hit.
[2023-03-14 07:06:59] [INFO ] State equation strengthened by 183 read => feed constraints.
[2023-03-14 07:06:59] [INFO ] Implicit Places using invariants and state equation in 288 ms returned []
Implicit Place search using SMT with State Equation took 454 ms to find 0 implicit places.
[2023-03-14 07:06:59] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:06:59] [INFO ] Invariant cache hit.
[2023-03-14 07:07:00] [INFO ] Dead Transitions using invariants and state equation in 1019 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2950 ms. Remains : 302/302 places, 3137/3137 transitions.
Support contains 170 out of 302 places after structural reductions.
[2023-03-14 07:07:01] [INFO ] Flatten gal took : 232 ms
[2023-03-14 07:07:01] [INFO ] Flatten gal took : 138 ms
[2023-03-14 07:07:01] [INFO ] Input system was already deterministic with 3137 transitions.
Incomplete random walk after 10000 steps, including 41 resets, run finished after 306 ms. (steps per millisecond=32 ) properties (out of 91) seen :89
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 2) seen :1
Finished Best-First random walk after 3875 steps, including 1 resets, run visited all 1 properties in 10 ms. (steps per millisecond=387 )
[2023-03-14 07:07:02] [INFO ] Flatten gal took : 92 ms
[2023-03-14 07:07:02] [INFO ] Flatten gal took : 95 ms
[2023-03-14 07:07:02] [INFO ] Input system was already deterministic with 3137 transitions.
Computed a total of 302 stabilizing places and 3137 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 302 transition count 3137
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 2 formulas.
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 31 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:02] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:02] [INFO ] Invariant cache hit.
[2023-03-14 07:07:03] [INFO ] Dead Transitions using invariants and state equation in 839 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 872 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:03] [INFO ] Flatten gal took : 88 ms
[2023-03-14 07:07:03] [INFO ] Flatten gal took : 96 ms
[2023-03-14 07:07:03] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 14 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:03] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:03] [INFO ] Invariant cache hit.
[2023-03-14 07:07:04] [INFO ] Dead Transitions using invariants and state equation in 832 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 847 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:04] [INFO ] Flatten gal took : 79 ms
[2023-03-14 07:07:04] [INFO ] Flatten gal took : 85 ms
[2023-03-14 07:07:05] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 12 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:05] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:05] [INFO ] Invariant cache hit.
[2023-03-14 07:07:06] [INFO ] Dead Transitions using invariants and state equation in 927 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 942 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:06] [INFO ] Flatten gal took : 76 ms
[2023-03-14 07:07:06] [INFO ] Flatten gal took : 83 ms
[2023-03-14 07:07:06] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 11 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:06] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:06] [INFO ] Invariant cache hit.
[2023-03-14 07:07:07] [INFO ] Dead Transitions using invariants and state equation in 832 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 847 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:07] [INFO ] Flatten gal took : 73 ms
[2023-03-14 07:07:07] [INFO ] Flatten gal took : 88 ms
[2023-03-14 07:07:07] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 831 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:08] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:08] [INFO ] Invariant cache hit.
[2023-03-14 07:07:09] [INFO ] Dead Transitions using invariants and state equation in 856 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1689 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:09] [INFO ] Flatten gal took : 80 ms
[2023-03-14 07:07:09] [INFO ] Flatten gal took : 92 ms
[2023-03-14 07:07:09] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 10 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:09] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:09] [INFO ] Invariant cache hit.
[2023-03-14 07:07:10] [INFO ] Dead Transitions using invariants and state equation in 895 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 906 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:10] [INFO ] Flatten gal took : 74 ms
[2023-03-14 07:07:10] [INFO ] Flatten gal took : 82 ms
[2023-03-14 07:07:10] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 10 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:10] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:10] [INFO ] Invariant cache hit.
[2023-03-14 07:07:11] [INFO ] Dead Transitions using invariants and state equation in 901 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 914 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:11] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-14 07:07:11] [INFO ] Flatten gal took : 75 ms
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-14 07:07:11] [INFO ] Flatten gal took : 90 ms
[2023-03-14 07:07:12] [INFO ] Input system was already deterministic with 3137 transitions.
Support contains 0 out of 302 places (down from 9) after GAL structural reductions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 717 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:12] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:12] [INFO ] Invariant cache hit.
[2023-03-14 07:07:13] [INFO ] Dead Transitions using invariants and state equation in 926 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1659 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:13] [INFO ] Flatten gal took : 74 ms
[2023-03-14 07:07:13] [INFO ] Flatten gal took : 83 ms
[2023-03-14 07:07:14] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 9 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:14] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:14] [INFO ] Invariant cache hit.
[2023-03-14 07:07:14] [INFO ] Dead Transitions using invariants and state equation in 825 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 849 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:14] [INFO ] Flatten gal took : 74 ms
[2023-03-14 07:07:15] [INFO ] Flatten gal took : 81 ms
[2023-03-14 07:07:15] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 9 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:15] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:15] [INFO ] Invariant cache hit.
[2023-03-14 07:07:16] [INFO ] Dead Transitions using invariants and state equation in 964 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 975 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:16] [INFO ] Flatten gal took : 73 ms
[2023-03-14 07:07:16] [INFO ] Flatten gal took : 81 ms
[2023-03-14 07:07:16] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 8 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:16] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:16] [INFO ] Invariant cache hit.
[2023-03-14 07:07:17] [INFO ] Dead Transitions using invariants and state equation in 938 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 963 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:17] [INFO ] Flatten gal took : 74 ms
[2023-03-14 07:07:17] [INFO ] Flatten gal took : 82 ms
[2023-03-14 07:07:17] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 9 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:17] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:17] [INFO ] Invariant cache hit.
[2023-03-14 07:07:18] [INFO ] Dead Transitions using invariants and state equation in 891 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 903 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:18] [INFO ] Flatten gal took : 73 ms
[2023-03-14 07:07:18] [INFO ] Flatten gal took : 81 ms
[2023-03-14 07:07:18] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in LTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 9 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:19] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:19] [INFO ] Invariant cache hit.
[2023-03-14 07:07:19] [INFO ] Dead Transitions using invariants and state equation in 884 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 894 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:19] [INFO ] Flatten gal took : 75 ms
[2023-03-14 07:07:20] [INFO ] Flatten gal took : 80 ms
[2023-03-14 07:07:20] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 682 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:20] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:20] [INFO ] Invariant cache hit.
[2023-03-14 07:07:21] [INFO ] Dead Transitions using invariants and state equation in 931 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1624 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:21] [INFO ] Flatten gal took : 74 ms
[2023-03-14 07:07:21] [INFO ] Flatten gal took : 82 ms
[2023-03-14 07:07:22] [INFO ] Input system was already deterministic with 3137 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 302/302 places, 3137/3137 transitions.
Applied a total of 0 rules in 705 ms. Remains 302 /302 variables (removed 0) and now considering 3137/3137 (removed 0) transitions.
[2023-03-14 07:07:22] [INFO ] Flow matrix only has 201 transitions (discarded 2936 similar events)
[2023-03-14 07:07:22] [INFO ] Invariant cache hit.
[2023-03-14 07:07:23] [INFO ] Dead Transitions using invariants and state equation in 955 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1662 ms. Remains : 302/302 places, 3137/3137 transitions.
[2023-03-14 07:07:23] [INFO ] Flatten gal took : 72 ms
[2023-03-14 07:07:23] [INFO ] Flatten gal took : 83 ms
[2023-03-14 07:07:24] [INFO ] Input system was already deterministic with 3137 transitions.
[2023-03-14 07:07:24] [INFO ] Flatten gal took : 80 ms
[2023-03-14 07:07:24] [INFO ] Flatten gal took : 90 ms
[2023-03-14 07:07:24] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 42 ms.
[2023-03-14 07:07:24] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 302 places, 3137 transitions and 21755 arcs took 26 ms.
Total runtime 27014 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PhaseVariation-PT-D10CS100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/368
CTLFireability
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PhaseVariation-PT-D10CS100-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678779220325
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/368/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/368/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/368/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 4 (type EXCL) for 3 PhaseVariation-PT-D10CS100-CTLFireability-01
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for PhaseVariation-PT-D10CS100-CTLFireability-01
lola: result : true
lola: markings : 122
lola: fired transitions : 123
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 13 (type EXCL) for 6 PhaseVariation-PT-D10CS100-CTLFireability-02
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 13 (type EXCL) for PhaseVariation-PT-D10CS100-CTLFireability-02
lola: result : true
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 72 (type EXCL) for 71 PhaseVariation-PT-D10CS100-CTLFireability-15
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 72 (type EXCL) for PhaseVariation-PT-D10CS100-CTLFireability-15
lola: result : false
lola: markings : 121
lola: fired transitions : 120
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 PhaseVariation-PT-D10CS100-CTLFireability-07
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 74 (type FNDP) for 6 PhaseVariation-PT-D10CS100-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 6 PhaseVariation-PT-D10CS100-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SRCH) for 6 PhaseVariation-PT-D10CS100-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 77 (type SRCH) for PhaseVariation-PT-D10CS100-CTLFireability-02
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 74 (type FNDP) for PhaseVariation-PT-D10CS100-CTLFireability-02 (obsolete)
lola: CANCELED task # 75 (type EQUN) for PhaseVariation-PT-D10CS100-CTLFireability-02 (obsolete)
lola: FINISHED task # 74 (type FNDP) for PhaseVariation-PT-D10CS100-CTLFireability-02
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: try reading problem file /home/mcc/execution/368/CTLFireability-75.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:663
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D10CS100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ 0 4 0 0 4 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 2/256 1/32 PhaseVariation-PT-D10CS100-CTLFireability-07 36521 m, 7304 m/sec, 1080116 t fired, .
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PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D10CS100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ 0 4 0 0 4 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 7/256 1/32 PhaseVariation-PT-D10CS100-CTLFireability-07 127953 m, 18286 m/sec, 4010287 t fired, .
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PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D10CS100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ 0 4 0 0 4 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 12/256 2/32 PhaseVariation-PT-D10CS100-CTLFireability-07 209597 m, 16328 m/sec, 6902135 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D10CS100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ 0 4 0 0 4 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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39 CTL EXCL 17/256 2/32 PhaseVariation-PT-D10CS100-CTLFireability-07 281384 m, 14357 m/sec, 9898005 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D10CS100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ 0 4 0 0 4 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 22/256 3/32 PhaseVariation-PT-D10CS100-CTLFireability-07 369907 m, 17704 m/sec, 12728717 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D10CS100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ 0 4 0 0 4 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 27/256 3/32 PhaseVariation-PT-D10CS100-CTLFireability-07 444311 m, 14880 m/sec, 15720248 t fired, .
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PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D10CS100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ 0 4 0 0 4 0 0 0
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39 CTL EXCL 15/3338 1/5 PhaseVariation-PT-D10CS100-CTLFireability-07 137140 m, 9142 m/sec, 4349854 t fired, .
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39 CTL EXCL 20/3338 2/5 PhaseVariation-PT-D10CS100-CTLFireability-07 181165 m, 8805 m/sec, 5820968 t fired, .
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39 CTL EXCL 30/3338 2/5 PhaseVariation-PT-D10CS100-CTLFireability-07 257726 m, 7452 m/sec, 8894520 t fired, .
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PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
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PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
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PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
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PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
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PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
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PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
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PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
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PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
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PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
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PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
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PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
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PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
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PhaseVariation-PT-D10CS100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
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PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
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PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
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PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
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PhaseVariation-PT-D10CS100-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PhaseVariation-PT-D10CS100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PhaseVariation-PT-D10CS100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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lola: LAUNCH task # 30 (type EXCL) for 29 PhaseVariation-PT-D10CS100-CTLFireability-03
lola: time limit : 506 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for PhaseVariation-PT-D10CS100-CTLFireability-03
lola: result : true
lola: markings : 6028
lola: fired transitions : 21340
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 PhaseVariation-PT-D10CS100-CTLFireability-00
lola: time limit : 675 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for PhaseVariation-PT-D10CS100-CTLFireability-00
lola: result : false
lola: markings : 121
lola: fired transitions : 364
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 79 (type EXCL) for 32 PhaseVariation-PT-D10CS100-CTLFireability-04
lola: time limit : 1013 sec
lola: memory limit: 32 pages
lola: FINISHED task # 79 (type EXCL) for PhaseVariation-PT-D10CS100-CTLFireability-04
lola: result : false
lola: markings : 121
lola: fired transitions : 121
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 69 (type EXCL) for 68 PhaseVariation-PT-D10CS100-CTLFireability-14
lola: time limit : 2026 sec
lola: memory limit: 32 pages
lola: FINISHED task # 69 (type EXCL) for PhaseVariation-PT-D10CS100-CTLFireability-14
lola: result : true
lola: markings : 121
lola: fired transitions : 242
lola: time used : 1.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D10CS100-CTLFireability-00: CTL false CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-01: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-02: DISJ true DISJ
PhaseVariation-PT-D10CS100-CTLFireability-03: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-04: SP ECTL true LTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-05: CTL unknown AGGR
PhaseVariation-PT-D10CS100-CTLFireability-07: CTL unknown AGGR
PhaseVariation-PT-D10CS100-CTLFireability-08: CTL unknown AGGR
PhaseVariation-PT-D10CS100-CTLFireability-09: CONJ true CONJ
PhaseVariation-PT-D10CS100-CTLFireability-10: CTL unknown AGGR
PhaseVariation-PT-D10CS100-CTLFireability-11: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-12: CTL unknown AGGR
PhaseVariation-PT-D10CS100-CTLFireability-14: CTL true CTL model checker
PhaseVariation-PT-D10CS100-CTLFireability-15: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PhaseVariation-PT-D10CS100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PhaseVariation-PT-D10CS100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r295-tall-167873947300042"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PhaseVariation-PT-D10CS100.tgz
mv PhaseVariation-PT-D10CS100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;