fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r294-tall-167873946800586
Last Updated
May 14, 2023

About the Execution of LoLA for PolyORBLF-PT-S06J04T04

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15946.535 3600000.00 5376947.00 7406.80 ?FTFFF???FT??T?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r294-tall-167873946800586.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is PolyORBLF-PT-S06J04T04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r294-tall-167873946800586
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 8.2M
-rw-r--r-- 1 mcc users 13K Feb 26 13:55 CTLCardinality.txt
-rw-r--r-- 1 mcc users 88K Feb 26 13:55 CTLCardinality.xml
-rw-r--r-- 1 mcc users 115K Feb 26 13:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 474K Feb 26 13:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 7.8K Feb 25 16:35 LTLCardinality.txt
-rw-r--r-- 1 mcc users 36K Feb 25 16:35 LTLCardinality.xml
-rw-r--r-- 1 mcc users 39K Feb 25 16:35 LTLFireability.txt
-rw-r--r-- 1 mcc users 140K Feb 25 16:35 LTLFireability.xml
-rw-r--r-- 1 mcc users 19K Feb 26 14:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 121K Feb 26 14:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 39K Feb 26 14:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 191K Feb 26 14:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 16:35 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.4K Feb 25 16:35 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 6.8M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-00
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-01
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-02
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-03
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-04
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-05
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-06
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-07
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-08
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-09
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-10
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-11
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-12
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-13
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-14
FORMULA_NAME PolyORBLF-PT-S06J04T04-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678914317870

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PolyORBLF-PT-S06J04T04
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT PolyORBLF-PT-S06J04T04
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA PolyORBLF-PT-S06J04T04-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S06J04T04-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S06J04T04-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S06J04T04-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S06J04T04-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S06J04T04-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S06J04T04-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PolyORBLF-PT-S06J04T04-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 259920 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16156244 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 31 (type CNST) for 30 PolyORBLF-PT-S06J04T04-CTLFireability-10
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 31 (type CNST) for PolyORBLF-PT-S06J04T04-CTLFireability-10
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 1 (type EXCL) for 0 PolyORBLF-PT-S06J04T04-CTLFireability-00
lola: time limit : 202 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 48 (type FNDP) for 6 PolyORBLF-PT-S06J04T04-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 6 PolyORBLF-PT-S06J04T04-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 6 PolyORBLF-PT-S06J04T04-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 51 (type SRCH) for PolyORBLF-PT-S06J04T04-CTLFireability-02
lola: result : unknown
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 48 (type FNDP) for PolyORBLF-PT-S06J04T04-CTLFireability-02
lola: result : true
lola: fired transitions : 100
lola: tried executions : 9
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 49 (type EQUN) for PolyORBLF-PT-S06J04T04-CTLFireability-02 (obsolete)
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: try reading problem file /home/mcc/execution/CTLFireability-49.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type FNDP) for 27 PolyORBLF-PT-S06J04T04-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 27 PolyORBLF-PT-S06J04T04-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SRCH) for 27 PolyORBLF-PT-S06J04T04-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 3 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 3/246 1/32 PolyORBLF-PT-S06J04T04-CTLFireability-00 122363 m, 24472 m/sec, 294458 t fired, .
53 EF FNDP 0/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 --
54 EF STEQ 0/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara not yet started (preprocessing).
56 EF SRCH 0/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 --

Time elapsed: 158 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 56 (type SRCH) for PolyORBLF-PT-S06J04T04-CTLFireability-09
lola: result : unknown
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-54.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 8/246 7/32 PolyORBLF-PT-S06J04T04-CTLFireability-00 739370 m, 123401 m/sec, 1667520 t fired, .
53 EF FNDP 5/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 147316 t fired, 2605 attempts, .
54 EF STEQ 5/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 163 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 13/246 12/32 PolyORBLF-PT-S06J04T04-CTLFireability-00 1348710 m, 121868 m/sec, 3138693 t fired, .
53 EF FNDP 10/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 301995 t fired, 5124 attempts, .
54 EF STEQ 10/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 168 secs. Pages in use: 12
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 18/246 17/32 PolyORBLF-PT-S06J04T04-CTLFireability-00 1960605 m, 122379 m/sec, 4594163 t fired, .
53 EF FNDP 15/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 458587 t fired, 7558 attempts, .
54 EF STEQ 15/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 173 secs. Pages in use: 17
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 23/246 21/32 PolyORBLF-PT-S06J04T04-CTLFireability-00 2569874 m, 121853 m/sec, 6068660 t fired, .
53 EF FNDP 20/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 616074 t fired, 9915 attempts, .
54 EF STEQ 20/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 178 secs. Pages in use: 21
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 28/246 26/32 PolyORBLF-PT-S06J04T04-CTLFireability-00 3153606 m, 116746 m/sec, 7579048 t fired, .
53 EF FNDP 25/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 774333 t fired, 12176 attempts, .
54 EF STEQ 25/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 183 secs. Pages in use: 26
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 33/246 31/32 PolyORBLF-PT-S06J04T04-CTLFireability-00 3757079 m, 120694 m/sec, 9058026 t fired, .
53 EF FNDP 30/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 934607 t fired, 14377 attempts, .
54 EF STEQ 30/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 188 secs. Pages in use: 31
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 35/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 1095299 t fired, 16544 attempts, .
54 EF STEQ 35/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 193 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 PolyORBLF-PT-S06J04T04-CTLFireability-15
lola: time limit : 262 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/262 4/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 467067 m, 93413 m/sec, 1397784 t fired, .
53 EF FNDP 40/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 1256690 t fired, 18650 attempts, .
54 EF STEQ 40/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 198 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/262 6/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 677845 m, 42155 m/sec, 2764504 t fired, .
53 EF FNDP 45/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 1418825 t fired, 20700 attempts, .
54 EF STEQ 45/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 203 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/262 8/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 887695 m, 41970 m/sec, 4127152 t fired, .
53 EF FNDP 50/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 1582147 t fired, 22675 attempts, .
54 EF STEQ 50/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 208 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/262 10/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 1103455 m, 43152 m/sec, 5569101 t fired, .
53 EF FNDP 55/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 1744743 t fired, 24651 attempts, .
54 EF STEQ 55/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 213 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/262 11/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 1329310 m, 45171 m/sec, 7000768 t fired, .
53 EF FNDP 60/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 1908287 t fired, 26537 attempts, .
54 EF STEQ 60/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 218 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/262 14/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 1586932 m, 51524 m/sec, 8453730 t fired, .
53 EF FNDP 65/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 2072240 t fired, 28409 attempts, .
54 EF STEQ 65/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 223 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 35/262 15/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 1786280 m, 39869 m/sec, 9912081 t fired, .
53 EF FNDP 70/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 2236313 t fired, 30207 attempts, .
54 EF STEQ 70/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 228 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 40/262 17/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 2002264 m, 43196 m/sec, 11371208 t fired, .
53 EF FNDP 75/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 2400862 t fired, 32003 attempts, .
54 EF STEQ 75/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 233 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 45/262 19/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 2233131 m, 46173 m/sec, 12764789 t fired, .
53 EF FNDP 80/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 2565687 t fired, 33768 attempts, .
54 EF STEQ 80/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 238 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 50/262 21/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 2458229 m, 45019 m/sec, 14246175 t fired, .
53 EF FNDP 85/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 2730985 t fired, 35485 attempts, .
54 EF STEQ 85/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 243 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 55/262 23/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 2692884 m, 46931 m/sec, 15733736 t fired, .
53 EF FNDP 90/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 2896338 t fired, 37211 attempts, .
54 EF STEQ 90/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 248 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 60/262 24/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 2910211 m, 43465 m/sec, 17165774 t fired, .
53 EF FNDP 95/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 3062182 t fired, 38851 attempts, .
54 EF STEQ 95/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 253 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 65/262 26/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 3136624 m, 45282 m/sec, 18629475 t fired, .
53 EF FNDP 100/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 3227214 t fired, 40541 attempts, .
54 EF STEQ 100/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 258 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 70/262 28/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 3381228 m, 48920 m/sec, 20133673 t fired, .
53 EF FNDP 105/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 3390578 t fired, 42156 attempts, .
54 EF STEQ 105/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 263 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 75/262 30/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 3580240 m, 39802 m/sec, 21584415 t fired, .
53 EF FNDP 110/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 3557453 t fired, 43802 attempts, .
54 EF STEQ 110/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 268 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 80/262 31/32 PolyORBLF-PT-S06J04T04-CTLFireability-15 3789024 m, 41756 m/sec, 22967433 t fired, .
53 EF FNDP 115/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 3723796 t fired, 45456 attempts, .
54 EF STEQ 115/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 273 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 46 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 120/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 3890912 t fired, 47033 attempts, .
54 EF STEQ 120/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 278 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 43 (type EXCL) for 42 PolyORBLF-PT-S06J04T04-CTLFireability-14
lola: time limit : 276 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/276 4/32 PolyORBLF-PT-S06J04T04-CTLFireability-14 433415 m, 86683 m/sec, 986879 t fired, .
53 EF FNDP 125/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 4059100 t fired, 48620 attempts, .
54 EF STEQ 125/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 283 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/276 8/32 PolyORBLF-PT-S06J04T04-CTLFireability-14 880159 m, 89348 m/sec, 2004249 t fired, .
53 EF FNDP 130/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 4226260 t fired, 50219 attempts, .
54 EF STEQ 130/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 288 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/276 11/32 PolyORBLF-PT-S06J04T04-CTLFireability-14 1341830 m, 92334 m/sec, 3119192 t fired, .
53 EF FNDP 135/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 4394030 t fired, 51742 attempts, .
54 EF STEQ 135/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 293 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/276 15/32 PolyORBLF-PT-S06J04T04-CTLFireability-14 1796536 m, 90941 m/sec, 4173162 t fired, .
53 EF FNDP 140/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 4561545 t fired, 53290 attempts, .
54 EF STEQ 140/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 298 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/276 19/32 PolyORBLF-PT-S06J04T04-CTLFireability-14 2260175 m, 92727 m/sec, 5328653 t fired, .
53 EF FNDP 145/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 4729188 t fired, 54805 attempts, .
54 EF STEQ 145/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 303 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/276 23/32 PolyORBLF-PT-S06J04T04-CTLFireability-14 2720197 m, 92004 m/sec, 6438085 t fired, .
53 EF FNDP 150/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 4897397 t fired, 56367 attempts, .
54 EF STEQ 150/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 308 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 35/276 26/32 PolyORBLF-PT-S06J04T04-CTLFireability-14 3172583 m, 90477 m/sec, 7627721 t fired, .
53 EF FNDP 155/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 5066087 t fired, 57889 attempts, .
54 EF STEQ 155/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 313 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 40/276 30/32 PolyORBLF-PT-S06J04T04-CTLFireability-14 3637253 m, 92934 m/sec, 8756537 t fired, .
53 EF FNDP 160/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 5233842 t fired, 59425 attempts, .
54 EF STEQ 160/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 318 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 165/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 5401275 t fired, 60978 attempts, .
54 EF STEQ 165/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 323 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 PolyORBLF-PT-S06J04T04-CTLFireability-13
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-13
lola: result : true
lola: markings : 198
lola: fired transitions : 197
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 PolyORBLF-PT-S06J04T04-CTLFireability-12
lola: time limit : 327 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/327 6/32 PolyORBLF-PT-S06J04T04-CTLFireability-12 720847 m, 144169 m/sec, 1460271 t fired, .
53 EF FNDP 170/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 5568992 t fired, 62515 attempts, .
54 EF STEQ 170/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 328 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/327 12/32 PolyORBLF-PT-S06J04T04-CTLFireability-12 1452254 m, 146281 m/sec, 2953144 t fired, .
53 EF FNDP 175/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 5735446 t fired, 64034 attempts, .
54 EF STEQ 175/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 333 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/327 18/32 PolyORBLF-PT-S06J04T04-CTLFireability-12 2176236 m, 144796 m/sec, 4477169 t fired, .
53 EF FNDP 180/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 5900791 t fired, 65508 attempts, .
54 EF STEQ 180/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 338 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/327 24/32 PolyORBLF-PT-S06J04T04-CTLFireability-12 2898162 m, 144385 m/sec, 5989290 t fired, .
53 EF FNDP 185/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 6066546 t fired, 67016 attempts, .
54 EF STEQ 185/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 343 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/327 30/32 PolyORBLF-PT-S06J04T04-CTLFireability-12 3607228 m, 141813 m/sec, 7518556 t fired, .
53 EF FNDP 190/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 6232591 t fired, 68471 attempts, .
54 EF STEQ 190/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 348 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 37 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 195/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 6399554 t fired, 69948 attempts, .
54 EF STEQ 195/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 353 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 PolyORBLF-PT-S06J04T04-CTLFireability-08
lola: time limit : 360 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/360 4/32 PolyORBLF-PT-S06J04T04-CTLFireability-08 405017 m, 81003 m/sec, 1328269 t fired, .
53 EF FNDP 200/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 6568078 t fired, 71424 attempts, .
54 EF STEQ 200/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 358 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/360 7/32 PolyORBLF-PT-S06J04T04-CTLFireability-08 817506 m, 82497 m/sec, 2647477 t fired, .
53 EF FNDP 205/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 6736312 t fired, 72956 attempts, .
54 EF STEQ 205/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 363 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/360 11/32 PolyORBLF-PT-S06J04T04-CTLFireability-08 1230529 m, 82604 m/sec, 4035033 t fired, .
53 EF FNDP 210/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 6904759 t fired, 74444 attempts, .
54 EF STEQ 210/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 368 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/360 14/32 PolyORBLF-PT-S06J04T04-CTLFireability-08 1631785 m, 80251 m/sec, 5431937 t fired, .
53 EF FNDP 215/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 7073145 t fired, 75859 attempts, .
54 EF STEQ 215/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 373 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/360 17/32 PolyORBLF-PT-S06J04T04-CTLFireability-08 2041846 m, 82012 m/sec, 6793278 t fired, .
53 EF FNDP 220/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 7241712 t fired, 77302 attempts, .
54 EF STEQ 220/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 378 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 30/360 20/32 PolyORBLF-PT-S06J04T04-CTLFireability-08 2449314 m, 81493 m/sec, 8193615 t fired, .
53 EF FNDP 225/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 7410040 t fired, 78757 attempts, .
54 EF STEQ 225/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 383 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 35/360 24/32 PolyORBLF-PT-S06J04T04-CTLFireability-08 2849866 m, 80110 m/sec, 9596904 t fired, .
53 EF FNDP 230/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 7578716 t fired, 80204 attempts, .
54 EF STEQ 230/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 388 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 40/360 27/32 PolyORBLF-PT-S06J04T04-CTLFireability-08 3253627 m, 80752 m/sec, 11027006 t fired, .
53 EF FNDP 235/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 7747264 t fired, 81648 attempts, .
54 EF STEQ 235/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 393 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 45/360 30/32 PolyORBLF-PT-S06J04T04-CTLFireability-08 3663566 m, 81987 m/sec, 12435502 t fired, .
53 EF FNDP 240/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 7915471 t fired, 83145 attempts, .
54 EF STEQ 240/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 398 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 245/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 8083944 t fired, 84624 attempts, .
54 EF STEQ 245/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 403 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 21 PolyORBLF-PT-S06J04T04-CTLFireability-07
lola: time limit : 399 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/399 3/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 256174 m, 51234 m/sec, 548834 t fired, .
53 EF FNDP 250/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 8252473 t fired, 86079 attempts, .
54 EF STEQ 250/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 408 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/399 6/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 613436 m, 71452 m/sec, 1465578 t fired, .
53 EF FNDP 255/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 8420724 t fired, 87527 attempts, .
54 EF STEQ 255/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 413 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/399 9/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 1017064 m, 80725 m/sec, 2585623 t fired, .
53 EF FNDP 260/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 8589174 t fired, 88970 attempts, .
54 EF STEQ 260/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 418 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/399 13/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 1417102 m, 80007 m/sec, 3730746 t fired, .
53 EF FNDP 265/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 8757644 t fired, 90395 attempts, .
54 EF STEQ 265/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 423 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 25/399 16/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 1823987 m, 81377 m/sec, 4855441 t fired, .
53 EF FNDP 270/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 8926322 t fired, 91834 attempts, .
54 EF STEQ 270/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 428 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 30/399 19/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 2223982 m, 79999 m/sec, 6006563 t fired, .
53 EF FNDP 275/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 9095008 t fired, 93294 attempts, .
54 EF STEQ 275/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 433 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 35/399 22/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 2624164 m, 80036 m/sec, 7157193 t fired, .
53 EF FNDP 280/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 9264321 t fired, 94755 attempts, .
54 EF STEQ 280/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 438 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 40/399 26/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 3022291 m, 79625 m/sec, 8288954 t fired, .
53 EF FNDP 285/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 9432572 t fired, 96264 attempts, .
54 EF STEQ 285/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 443 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 45/399 29/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 3420497 m, 79641 m/sec, 9405827 t fired, .
53 EF FNDP 290/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 9600555 t fired, 97706 attempts, .
54 EF STEQ 290/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 448 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 50/399 32/32 PolyORBLF-PT-S06J04T04-CTLFireability-07 3819502 m, 79801 m/sec, 10541824 t fired, .
53 EF FNDP 295/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 9769650 t fired, 99130 attempts, .
54 EF STEQ 295/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 453 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 300/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 9938009 t fired, 100629 attempts, .
54 EF STEQ 300/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 458 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 PolyORBLF-PT-S06J04T04-CTLFireability-06
lola: time limit : 448 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/448 5/32 PolyORBLF-PT-S06J04T04-CTLFireability-06 551728 m, 110345 m/sec, 1648819 t fired, .
53 EF FNDP 305/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 10106972 t fired, 102046 attempts, .
54 EF STEQ 305/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 463 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/448 9/32 PolyORBLF-PT-S06J04T04-CTLFireability-06 1088272 m, 107308 m/sec, 3288935 t fired, .
53 EF FNDP 310/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 10253585 t fired, 103308 attempts, .
54 EF STEQ 310/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 468 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/448 14/32 PolyORBLF-PT-S06J04T04-CTLFireability-06 1619112 m, 106168 m/sec, 4943158 t fired, .
53 EF FNDP 315/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 10421802 t fired, 104795 attempts, .
54 EF STEQ 315/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 473 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/448 18/32 PolyORBLF-PT-S06J04T04-CTLFireability-06 2157557 m, 107689 m/sec, 6599474 t fired, .
53 EF FNDP 320/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 10590594 t fired, 106218 attempts, .
54 EF STEQ 320/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 478 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/448 22/32 PolyORBLF-PT-S06J04T04-CTLFireability-06 2691847 m, 106858 m/sec, 8243104 t fired, .
53 EF FNDP 325/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 10759012 t fired, 107702 attempts, .
54 EF STEQ 325/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 483 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/448 27/32 PolyORBLF-PT-S06J04T04-CTLFireability-06 3216095 m, 104849 m/sec, 9900163 t fired, .
53 EF FNDP 330/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 10927752 t fired, 109101 attempts, .
54 EF STEQ 330/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 488 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/448 31/32 PolyORBLF-PT-S06J04T04-CTLFireability-06 3742128 m, 105206 m/sec, 11559456 t fired, .
53 EF FNDP 335/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 11096207 t fired, 110538 attempts, .
54 EF STEQ 335/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 493 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 1 2 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 340/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 11265278 t fired, 111964 attempts, .
54 EF STEQ 340/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.

Time elapsed: 498 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 PolyORBLF-PT-S06J04T04-CTLFireability-05
lola: time limit : 517 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-05
lola: result : false
lola: markings : 59316
lola: fired transitions : 112519
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 PolyORBLF-PT-S06J04T04-CTLFireability-04
lola: time limit : 620 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-04
lola: result : false
lola: markings : 198
lola: fired transitions : 395
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 PolyORBLF-PT-S06J04T04-CTLFireability-03
lola: time limit : 775 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-03
lola: result : false
lola: markings : 510
lola: fired transitions : 550
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 PolyORBLF-PT-S06J04T04-CTLFireability-01
lola: time limit : 1034 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-01
lola: result : false
lola: markings : 199
lola: fired transitions : 401
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 27 PolyORBLF-PT-S06J04T04-CTLFireability-09
lola: time limit : 1551 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 345/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 11433642 t fired, 113381 attempts, .
54 EF STEQ 345/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 5/1551 1/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 136524 m, 27304 m/sec, 168262 t fired, .

Time elapsed: 503 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 350/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 11601594 t fired, 114859 attempts, .
54 EF STEQ 350/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 10/1551 2/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 284437 m, 29582 m/sec, 359678 t fired, .

Time elapsed: 508 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 355/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 11769375 t fired, 116327 attempts, .
54 EF STEQ 355/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 15/1551 3/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 431687 m, 29450 m/sec, 554790 t fired, .

Time elapsed: 513 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 360/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 11937828 t fired, 117741 attempts, .
54 EF STEQ 360/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 20/1551 4/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 578425 m, 29347 m/sec, 754647 t fired, .

Time elapsed: 518 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 365/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 12106489 t fired, 119154 attempts, .
54 EF STEQ 365/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 25/1551 5/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 724299 m, 29174 m/sec, 956680 t fired, .

Time elapsed: 523 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 370/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 12275171 t fired, 120594 attempts, .
54 EF STEQ 370/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 30/1551 6/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 871019 m, 29344 m/sec, 1162537 t fired, .

Time elapsed: 528 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 375/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 12444031 t fired, 122053 attempts, .
54 EF STEQ 375/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 35/1551 7/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 950108 m, 15817 m/sec, 1272406 t fired, .

Time elapsed: 533 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 380/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 12613195 t fired, 123440 attempts, .
54 EF STEQ 380/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 40/1551 7/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1022477 m, 14473 m/sec, 1372655 t fired, .

Time elapsed: 538 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 385/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 12782146 t fired, 124896 attempts, .
54 EF STEQ 385/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 45/1551 7/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1094894 m, 14483 m/sec, 1473924 t fired, .

Time elapsed: 543 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 390/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 12951171 t fired, 126340 attempts, .
54 EF STEQ 390/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 50/1551 8/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1167460 m, 14513 m/sec, 1577985 t fired, .

Time elapsed: 548 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 395/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 13120819 t fired, 127737 attempts, .
54 EF STEQ 395/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 55/1551 8/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1239221 m, 14352 m/sec, 1679117 t fired, .

Time elapsed: 553 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 400/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 13290412 t fired, 129156 attempts, .
54 EF STEQ 400/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 60/1551 9/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1311396 m, 14435 m/sec, 1780805 t fired, .

Time elapsed: 558 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 405/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 13459153 t fired, 130591 attempts, .
54 EF STEQ 405/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 65/1551 9/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1384030 m, 14526 m/sec, 1883947 t fired, .

Time elapsed: 563 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 410/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 13628545 t fired, 132054 attempts, .
54 EF STEQ 410/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 70/1551 10/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1456449 m, 14483 m/sec, 1986640 t fired, .

Time elapsed: 568 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 415/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 13797674 t fired, 133479 attempts, .
54 EF STEQ 415/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 75/1551 10/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1528531 m, 14416 m/sec, 2091619 t fired, .

Time elapsed: 573 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 420/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 13966206 t fired, 134825 attempts, .
54 EF STEQ 420/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 80/1551 10/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1601120 m, 14517 m/sec, 2196034 t fired, .

Time elapsed: 578 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 425/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 14134382 t fired, 136249 attempts, .
54 EF STEQ 425/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 85/1551 11/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1675900 m, 14956 m/sec, 2308023 t fired, .

Time elapsed: 583 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 430/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 14301965 t fired, 137713 attempts, .
54 EF STEQ 430/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 90/1551 11/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1748832 m, 14586 m/sec, 2411389 t fired, .

Time elapsed: 588 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 435/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 14470288 t fired, 139118 attempts, .
54 EF STEQ 435/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 95/1551 12/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1821447 m, 14523 m/sec, 2518663 t fired, .

Time elapsed: 593 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 440/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 14638938 t fired, 140524 attempts, .
54 EF STEQ 440/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 100/1551 12/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1895459 m, 14802 m/sec, 2630430 t fired, .

Time elapsed: 598 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 445/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 14807485 t fired, 142007 attempts, .
54 EF STEQ 445/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 105/1551 13/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 1968339 m, 14576 m/sec, 2734136 t fired, .

Time elapsed: 603 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 450/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 14975571 t fired, 143453 attempts, .
54 EF STEQ 450/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 110/1551 13/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 2040868 m, 14505 m/sec, 2838987 t fired, .

Time elapsed: 608 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 455/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 15144445 t fired, 144926 attempts, .
54 EF STEQ 455/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 115/1551 14/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 2125939 m, 17014 m/sec, 2964401 t fired, .

Time elapsed: 613 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 460/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 15312151 t fired, 146364 attempts, .
54 EF STEQ 460/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 120/1551 14/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 2224576 m, 19727 m/sec, 3111239 t fired, .

Time elapsed: 618 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 465/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 15481083 t fired, 147755 attempts, .
54 EF STEQ 465/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 125/1551 15/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 2297273 m, 14539 m/sec, 3214895 t fired, .

Time elapsed: 623 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 470/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 15649008 t fired, 149181 attempts, .
54 EF STEQ 470/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 130/1551 15/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 2408927 m, 22330 m/sec, 3380042 t fired, .

Time elapsed: 628 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 475/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 15817725 t fired, 150593 attempts, .
54 EF STEQ 475/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 135/1551 16/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 2538542 m, 25923 m/sec, 3572589 t fired, .

Time elapsed: 633 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 480/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 15986495 t fired, 152007 attempts, .
54 EF STEQ 480/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 140/1551 16/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 2625404 m, 17372 m/sec, 3703525 t fired, .

Time elapsed: 638 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 485/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 16154554 t fired, 153455 attempts, .
54 EF STEQ 485/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 145/1551 17/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 2774392 m, 29797 m/sec, 3934666 t fired, .

Time elapsed: 643 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 490/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 16321738 t fired, 154840 attempts, .
54 EF STEQ 490/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 150/1551 18/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 2920142 m, 29150 m/sec, 4147063 t fired, .

Time elapsed: 648 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 495/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 16489935 t fired, 156267 attempts, .
54 EF STEQ 495/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 155/1551 19/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3015275 m, 19026 m/sec, 4293385 t fired, .

Time elapsed: 653 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 500/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 16657825 t fired, 157654 attempts, .
54 EF STEQ 500/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 160/1551 19/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3090711 m, 15087 m/sec, 4415522 t fired, .

Time elapsed: 658 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 505/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 16826357 t fired, 159094 attempts, .
54 EF STEQ 505/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 165/1551 20/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3163144 m, 14486 m/sec, 4522838 t fired, .

Time elapsed: 663 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 510/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 16995094 t fired, 160541 attempts, .
54 EF STEQ 510/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 170/1551 20/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3236074 m, 14586 m/sec, 4627567 t fired, .

Time elapsed: 668 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 515/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 17164304 t fired, 161935 attempts, .
54 EF STEQ 515/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 175/1551 20/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3308017 m, 14388 m/sec, 4733999 t fired, .

Time elapsed: 673 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 520/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 17334066 t fired, 163347 attempts, .
54 EF STEQ 520/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 180/1551 21/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3388034 m, 16003 m/sec, 4869138 t fired, .

Time elapsed: 678 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 525/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 17501991 t fired, 164790 attempts, .
54 EF STEQ 525/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 185/1551 21/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3461701 m, 14733 m/sec, 4983583 t fired, .

Time elapsed: 683 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 530/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 17670762 t fired, 166196 attempts, .
54 EF STEQ 530/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 190/1551 22/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3536579 m, 14975 m/sec, 5102110 t fired, .

Time elapsed: 688 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 535/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 17837724 t fired, 167659 attempts, .
54 EF STEQ 535/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 195/1551 22/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3608512 m, 14386 m/sec, 5209713 t fired, .

Time elapsed: 693 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 540/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 18005735 t fired, 169110 attempts, .
54 EF STEQ 540/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 200/1551 23/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3680806 m, 14458 m/sec, 5316090 t fired, .

Time elapsed: 698 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 545/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 18174098 t fired, 170535 attempts, .
54 EF STEQ 545/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 205/1551 23/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3754715 m, 14781 m/sec, 5431961 t fired, .

Time elapsed: 703 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 550/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 18342201 t fired, 172003 attempts, .
54 EF STEQ 550/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 210/1551 23/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3827319 m, 14520 m/sec, 5541915 t fired, .

Time elapsed: 708 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 555/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 18510278 t fired, 173434 attempts, .
54 EF STEQ 555/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 215/1551 24/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3904192 m, 15374 m/sec, 5671591 t fired, .

Time elapsed: 713 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 560/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 18678132 t fired, 174849 attempts, .
54 EF STEQ 560/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 220/1551 24/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 3976642 m, 14490 m/sec, 5784064 t fired, .

Time elapsed: 718 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 565/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 18846018 t fired, 176254 attempts, .
54 EF STEQ 565/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 225/1551 25/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 4050353 m, 14742 m/sec, 5898893 t fired, .

Time elapsed: 723 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 570/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 19014976 t fired, 177649 attempts, .
54 EF STEQ 570/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 230/1551 25/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 4126199 m, 15169 m/sec, 6019125 t fired, .

Time elapsed: 728 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF 0 0 3 0 2 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 1 0 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 575/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 19184237 t fired, 179082 attempts, .
54 EF STEQ 575/3442 0/5 PolyORBLF-PT-S06J04T04-CTLFireability-09 sara is running.
55 EF EXCL 235/1551 26/32 PolyORBLF-PT-S06J04T04-CTLFireability-09 4200498 m, 14859 m/sec, 6133926 t fired, .

Time elapsed: 733 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16

lola: FINISHED task # 54 (type EQUN) for PolyORBLF-PT-S06J04T04-CTLFireability-09
lola: result : false
lola: CANCELED task # 53 (type FNDP) for PolyORBLF-PT-S06J04T04-CTLFireability-09 (obsolete)
lola: CANCELED task # 55 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-09 (obsolete)
lola: LAUNCH task # 52 (type EXCL) for 33 PolyORBLF-PT-S06J04T04-CTLFireability-11
lola: time limit : 2865 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type FNDP) for PolyORBLF-PT-S06J04T04-CTLFireability-09
lola: result : unknown
lola: fired transitions : 19247846
lola: tried executions : 179639
lola: time used : 577.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 3/2865 4/32 PolyORBLF-PT-S06J04T04-CTLFireability-11 538303 m, 107660 m/sec, 1216254 t fired, .

Time elapsed: 738 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 8/2865 9/32 PolyORBLF-PT-S06J04T04-CTLFireability-11 1392893 m, 170918 m/sec, 3247827 t fired, .

Time elapsed: 743 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 13/2865 15/32 PolyORBLF-PT-S06J04T04-CTLFireability-11 2227874 m, 166996 m/sec, 5284261 t fired, .

Time elapsed: 748 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 18/2865 20/32 PolyORBLF-PT-S06J04T04-CTLFireability-11 3066608 m, 167746 m/sec, 7292868 t fired, .

Time elapsed: 753 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 23/2865 25/32 PolyORBLF-PT-S06J04T04-CTLFireability-11 3895371 m, 165752 m/sec, 9283513 t fired, .

Time elapsed: 758 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 1 0 1 0 0 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 28/2865 30/32 PolyORBLF-PT-S06J04T04-CTLFireability-11 4724473 m, 165820 m/sec, 11292245 t fired, .

Time elapsed: 763 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for PolyORBLF-PT-S06J04T04-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 768 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 773 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 778 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 783 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 788 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 793 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 798 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 803 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 808 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 813 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 818 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 823 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 828 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 833 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 838 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 843 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 848 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 853 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 858 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 863 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 868 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 873 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 878 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 883 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 888 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 893 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 898 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 903 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 908 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 913 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 918 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 923 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 928 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 933 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 938 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 943 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 948 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 953 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 958 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 963 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 968 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 973 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 978 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 983 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 988 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 993 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 998 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1003 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1008 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1013 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1018 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1023 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1028 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1033 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1038 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1043 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1048 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1053 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1058 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1063 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1068 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1073 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1078 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1083 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1088 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1093 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1098 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1103 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1108 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1113 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1118 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1123 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1128 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1133 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1138 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1143 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1148 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1153 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1158 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1163 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1168 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1173 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1178 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1183 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1188 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1193 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1198 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1203 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1208 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1213 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1218 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1223 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1228 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1233 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1238 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1243 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1248 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1253 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1258 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1263 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1268 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1273 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1278 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1283 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1288 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1293 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1298 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1303 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1308 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1313 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1318 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1323 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1328 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1333 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1338 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1343 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1348 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1353 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1358 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1363 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1368 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1373 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1378 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1383 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1389 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1394 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1399 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1404 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1409 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1414 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1419 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1424 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1429 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1434 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1439 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1444 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1449 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1454 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1459 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1464 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1469 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1474 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1479 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1484 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1489 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1494 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1499 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1504 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1509 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1514 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1519 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1524 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1529 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1534 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1539 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1544 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1549 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1554 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1559 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1564 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1569 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1574 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1579 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1584 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1589 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1594 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1599 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1604 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1609 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1614 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1619 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1624 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1629 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1634 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1639 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1644 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1649 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1654 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1659 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1664 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1669 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1674 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1679 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1684 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1689 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1694 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1699 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1704 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1709 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1714 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1719 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1724 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1729 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1734 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1739 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1744 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1749 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1754 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1759 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1764 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1769 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1774 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1779 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1784 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1789 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1794 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1799 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1804 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1809 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1814 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1819 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1824 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1829 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1834 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1839 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1844 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1849 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1854 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1859 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1864 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1869 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1874 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1879 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1884 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1889 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1894 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1899 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1904 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1909 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1914 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1919 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1924 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1929 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1934 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1939 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1944 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1949 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1954 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1959 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1964 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1969 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1974 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1979 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1984 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1989 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1994 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1999 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2004 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2009 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2014 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2019 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2024 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2029 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2034 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2039 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2044 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2049 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2054 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2059 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2064 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2069 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2074 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2079 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2084 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2089 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2094 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2099 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2104 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2109 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2114 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2119 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2124 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2129 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2134 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2139 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2144 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2149 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2154 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2159 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2164 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2169 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2174 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2179 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2184 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2189 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2194 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2199 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2204 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2209 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2214 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2219 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2224 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2229 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2234 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2239 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2244 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2249 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2254 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2259 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2264 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2269 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2274 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2279 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2284 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2289 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2294 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2299 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2304 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2309 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2314 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2319 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2324 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2329 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2334 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2339 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2344 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2349 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2354 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2359 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2364 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2369 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2374 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2379 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2384 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2389 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2394 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2399 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2404 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2409 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2414 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2419 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2424 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2429 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2434 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2439 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2444 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2449 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2454 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2459 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2464 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2469 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2474 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2479 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2484 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2489 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2494 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2499 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2504 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2509 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2514 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2519 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2524 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2529 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2534 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2539 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2544 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2549 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2554 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2559 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2564 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2569 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2574 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2579 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2584 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2589 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2594 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2599 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2604 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2609 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2614 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2619 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2624 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2629 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2634 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2639 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2644 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2649 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2654 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2659 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2664 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2669 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2674 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2679 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2684 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2689 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2694 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2699 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2704 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2709 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2714 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2719 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2724 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2729 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2734 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2739 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2744 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2749 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2754 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2759 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2764 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2769 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2774 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2779 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2784 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2789 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2794 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2799 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2804 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2809 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2814 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2819 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2824 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2829 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2834 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2839 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2844 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2849 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2854 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2859 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2864 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2869 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2874 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2879 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2884 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2889 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2894 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2899 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2904 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2909 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PolyORBLF-PT-S06J04T04-CTLFireability-01: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-02: EF true findpath
PolyORBLF-PT-S06J04T04-CTLFireability-03: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-04: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-05: CTL false CTL model checker
PolyORBLF-PT-S06J04T04-CTLFireability-09: EF false state equation
PolyORBLF-PT-S06J04T04-CTLFireability-10: INITIAL true preprocessing
PolyORBLF-PT-S06J04T04-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PolyORBLF-PT-S06J04T04-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-11: EFAG 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
PolyORBLF-PT-S06J04T04-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2914 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PolyORBLF-PT-S06J04T04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is PolyORBLF-PT-S06J04T04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r294-tall-167873946800586"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PolyORBLF-PT-S06J04T04.tgz
mv PolyORBLF-PT-S06J04T04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;