fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r265-smll-167863540100458
Last Updated
May 14, 2023

About the Execution of LTSMin+red for PermAdmissibility-COL-01

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
282.388 10547.00 21622.00 583.40 FTFFTTFTFFFTFFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r265-smll-167863540100458.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool ltsminxred
Input is PermAdmissibility-COL-01, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r265-smll-167863540100458
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 7.0K Feb 26 01:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 26 01:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 01:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 01:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 01:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 109K Feb 26 01:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 01:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 26 01:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 54K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-00
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-01
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-02
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-03
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-04
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-05
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-06
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-07
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-08
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-09
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-10
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-11
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-12
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-13
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-14
FORMULA_NAME PermAdmissibility-COL-01-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679029660428

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PermAdmissibility-COL-01
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202303021504
[2023-03-17 05:07:43] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 05:07:43] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 05:07:43] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-17 05:07:43] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-17 05:07:44] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 856 ms
[2023-03-17 05:07:44] [INFO ] Imported 40 HL places and 16 HL transitions for a total of 208 PT places and 1024.0 transition bindings in 26 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 28 ms.
[2023-03-17 05:07:44] [INFO ] Built PT skeleton of HLPN with 40 places and 16 transitions 83 arcs in 6 ms.
[2023-03-17 05:07:44] [INFO ] Skeletonized 16 HLPN properties in 3 ms.
Computed a total of 40 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 40 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 8 formulas.
FORMULA PermAdmissibility-COL-01-CTLFireability-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 11 properties that can be checked using skeleton over-approximation.
Computed a total of 40 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 40 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Incomplete random walk after 10000 steps, including 588 resets, run finished after 580 ms. (steps per millisecond=17 ) properties (out of 21) seen :16
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 359 ms. (steps per millisecond=27 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 197 ms. (steps per millisecond=50 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 223 ms. (steps per millisecond=44 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 241 ms. (steps per millisecond=41 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 244 ms. (steps per millisecond=40 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
// Phase 1: matrix 16 rows 40 cols
[2023-03-17 05:07:46] [INFO ] Computed 24 place invariants in 6 ms
[2023-03-17 05:07:46] [INFO ] [Real]Absence check using 0 positive and 24 generalized place invariants in 24 ms returned sat
[2023-03-17 05:07:46] [INFO ] After 262ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0 real:1
[2023-03-17 05:07:46] [INFO ] [Nat]Absence check using 0 positive and 24 generalized place invariants in 12 ms returned sat
[2023-03-17 05:07:46] [INFO ] After 85ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :0
Fused 5 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 5 atomic propositions for a total of 10 simplifications.
[2023-03-17 05:07:46] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-17 05:07:46] [INFO ] Flatten gal took : 51 ms
[2023-03-17 05:07:46] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA PermAdmissibility-COL-01-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PermAdmissibility-COL-01-CTLFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-17 05:07:46] [INFO ] Flatten gal took : 7 ms
Symmetric sort wr.t. initial and guards and successors and join/free detected :input
Symmetric sort wr.t. initial detected :input
Symmetric sort wr.t. initial and guards detected :input
Applying symmetric unfolding of full symmetric sort :input domain size was 8
[2023-03-17 05:07:46] [INFO ] Unfolded HLPN to a Petri net with 40 places and 16 transitions 83 arcs in 12 ms.
[2023-03-17 05:07:46] [INFO ] Unfolded 13 HLPN properties in 0 ms.
Support contains 32 out of 40 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 40/40 places, 16/16 transitions.
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 32 transition count 16
Applied a total of 8 rules in 9 ms. Remains 32 /40 variables (removed 8) and now considering 16/16 (removed 0) transitions.
// Phase 1: matrix 16 rows 32 cols
[2023-03-17 05:07:46] [INFO ] Computed 16 place invariants in 7 ms
[2023-03-17 05:07:46] [INFO ] Implicit Places using invariants in 76 ms returned []
[2023-03-17 05:07:46] [INFO ] Invariant cache hit.
[2023-03-17 05:07:46] [INFO ] Implicit Places using invariants and state equation in 52 ms returned []
Implicit Place search using SMT with State Equation took 131 ms to find 0 implicit places.
[2023-03-17 05:07:46] [INFO ] Invariant cache hit.
[2023-03-17 05:07:46] [INFO ] Dead Transitions using invariants and state equation in 45 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 32/40 places, 16/16 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 187 ms. Remains : 32/40 places, 16/16 transitions.
Support contains 32 out of 32 places after structural reductions.
[2023-03-17 05:07:46] [INFO ] Flatten gal took : 6 ms
[2023-03-17 05:07:46] [INFO ] Flatten gal took : 7 ms
[2023-03-17 05:07:46] [INFO ] Input system was already deterministic with 16 transitions.
Incomplete random walk after 10000 steps, including 588 resets, run finished after 511 ms. (steps per millisecond=19 ) properties (out of 28) seen :23
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 304 ms. (steps per millisecond=32 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 228 ms. (steps per millisecond=43 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 234 ms. (steps per millisecond=42 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 241 ms. (steps per millisecond=41 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 588 resets, run finished after 256 ms. (steps per millisecond=39 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-03-17 05:07:48] [INFO ] Invariant cache hit.
[2023-03-17 05:07:48] [INFO ] [Real]Absence check using 0 positive and 16 generalized place invariants in 6 ms returned sat
[2023-03-17 05:07:48] [INFO ] After 69ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-17 05:07:48] [INFO ] [Nat]Absence check using 0 positive and 16 generalized place invariants in 9 ms returned sat
[2023-03-17 05:07:48] [INFO ] After 107ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :0
Fused 5 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 5 atomic propositions for a total of 13 simplifications.
[2023-03-17 05:07:48] [INFO ] Flatten gal took : 6 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 6 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
FORMULA PermAdmissibility-COL-01-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 32 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 32 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 28 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.1 ms
Discarding 4 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Ensure Unique test removed 2 places
Applied a total of 1 rules in 9 ms. Remains 26 /32 variables (removed 6) and now considering 14/16 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 26/32 places, 14/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 14 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 32/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 30 transition count 16
Applied a total of 2 rules in 2 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 30/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 1 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 1 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 2 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 1 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 28 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.0 ms
Discarding 4 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Ensure Unique test removed 1 places
Applied a total of 1 rules in 3 ms. Remains 27 /32 variables (removed 5) and now considering 14/16 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 27/32 places, 14/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 2 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 2 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 14 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 1 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 32/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 2 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 32/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 2 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 30 transition count 16
Applied a total of 2 rules in 1 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 30/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 2 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 2 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 32/32 places, 16/16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Input system was already deterministic with 16 transitions.
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 4 ms
[2023-03-17 05:07:49] [INFO ] Flatten gal took : 3 ms
[2023-03-17 05:07:49] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-17 05:07:49] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 32 places, 16 transitions and 75 arcs took 1 ms.
Total runtime 6220 ms.
There are residual formulas that ITS could not solve within timeout
pnml2lts-sym model.pnml --lace-workers=4 --vset=lddmc --saturation=sat -rbs,w2W,ru,hf --sylvan-sizes=20,28,20,28 --ctl=/tmp/472/ctl_0_ --ctl=/tmp/472/ctl_1_ --ctl=/tmp/472/ctl_2_ --ctl=/tmp/472/ctl_3_ --ctl=/tmp/472/ctl_4_ --ctl=/tmp/472/ctl_5_ --ctl=/tmp/472/ctl_6_ --ctl=/tmp/472/ctl_7_ --ctl=/tmp/472/ctl_8_ --ctl=/tmp/472/ctl_9_ --ctl=/tmp/472/ctl_10_ --ctl=/tmp/472/ctl_11_ --mu-par --mu-opt
FORMULA PermAdmissibility-COL-01-CTLFireability-01 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-04 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-05 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-09 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-10 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-12 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-13 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-14 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA PermAdmissibility-COL-01-CTLFireability-15 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN

BK_STOP 1679029670975

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2023
ctl formula name PermAdmissibility-COL-01-CTLFireability-01
ctl formula formula --ctl=/tmp/472/ctl_0_
ctl formula name PermAdmissibility-COL-01-CTLFireability-02
ctl formula formula --ctl=/tmp/472/ctl_1_
ctl formula name PermAdmissibility-COL-01-CTLFireability-04
ctl formula formula --ctl=/tmp/472/ctl_2_
ctl formula name PermAdmissibility-COL-01-CTLFireability-05
ctl formula formula --ctl=/tmp/472/ctl_3_
ctl formula name PermAdmissibility-COL-01-CTLFireability-06
ctl formula formula --ctl=/tmp/472/ctl_4_
ctl formula name PermAdmissibility-COL-01-CTLFireability-09
ctl formula formula --ctl=/tmp/472/ctl_5_
ctl formula name PermAdmissibility-COL-01-CTLFireability-10
ctl formula formula --ctl=/tmp/472/ctl_6_
ctl formula name PermAdmissibility-COL-01-CTLFireability-11
ctl formula formula --ctl=/tmp/472/ctl_7_
ctl formula name PermAdmissibility-COL-01-CTLFireability-12
ctl formula formula --ctl=/tmp/472/ctl_8_
ctl formula name PermAdmissibility-COL-01-CTLFireability-13
ctl formula formula --ctl=/tmp/472/ctl_9_
ctl formula name PermAdmissibility-COL-01-CTLFireability-14
ctl formula formula --ctl=/tmp/472/ctl_10_
ctl formula name PermAdmissibility-COL-01-CTLFireability-15
ctl formula formula --ctl=/tmp/472/ctl_11_
pnml2lts-sym: Exploration order is bfs-prev
pnml2lts-sym: Saturation strategy is sat
pnml2lts-sym: Guided search strategy is unguided
pnml2lts-sym: Attractor strategy is default
pnml2lts-sym: opening model.pnml
pnml2lts-sym: Edge label is id
Warning: program compiled against libxml 210 using older 209
pnml2lts-sym: Petri net has 32 places, 16 transitions and 75 arcs
pnml2lts-sym: Petri net Petri analyzed
pnml2lts-sym: There are no safe places
pnml2lts-sym: Loading Petri net took 0.000 real 0.000 user 0.000 sys
pnml2lts-sym: Initializing regrouping layer
pnml2lts-sym: Regroup specification: bs,w2W,ru,hf
pnml2lts-sym: Regroup Boost's Sloan
pnml2lts-sym: Regroup over-approximate must-write to may-write
pnml2lts-sym: Regroup Row sUbsume
pnml2lts-sym: Reqroup Horizontal Flip
pnml2lts-sym: Regrouping: 16->15 groups
pnml2lts-sym: Regrouping took 0.000 real 0.000 user 0.000 sys
pnml2lts-sym: state vector length is 32; there are 15 groups
pnml2lts-sym: Creating a multi-core ListDD domain.
pnml2lts-sym: Sylvan allocates 15.000 GB virtual memory for nodes table and operation cache.
pnml2lts-sym: Initial nodes table and operation cache requires 60.00 MB.
pnml2lts-sym: Using GBgetTransitionsShortR2W as next-state function
pnml2lts-sym: got initial state
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: Exploration took 113 group checks and 0 next state calls
pnml2lts-sym: reachability took 0.020 real 0.090 user 0.030 sys
pnml2lts-sym: counting visited states...
pnml2lts-sym: counting took 0.010 real 0.000 user 0.010 sys
pnml2lts-sym: state space has 17 states, 165 nodes
pnml2lts-sym: Formula /tmp/472/ctl_1_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_2_ holds for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_3_ holds for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_4_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_5_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_7_ holds for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_6_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_11_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_9_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_10_ holds for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_8_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/472/ctl_0_ holds for the initial state
pnml2lts-sym: group_next: 168 nodes total
pnml2lts-sym: group_explored: 235 nodes, 94 short vectors total
pnml2lts-sym: max token count: 2

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-01"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool ltsminxred"
echo " Input is PermAdmissibility-COL-01, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r265-smll-167863540100458"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-01.tgz
mv PermAdmissibility-COL-01 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;