fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r263-smll-167863538400546
Last Updated
May 14, 2023

About the Execution of LoLa+red for PermAdmissibility-PT-50

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
8494.016 2182943.00 2245255.00 5678.20 ????????F???F?FT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r263-smll-167863538400546.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PermAdmissibility-PT-50, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r263-smll-167863538400546
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.6M
-rw-r--r-- 1 mcc users 11K Feb 26 01:18 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 26 01:18 CTLCardinality.xml
-rw-r--r-- 1 mcc users 76K Feb 26 01:17 CTLFireability.txt
-rw-r--r-- 1 mcc users 407K Feb 26 01:17 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 16:31 LTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Feb 25 16:31 LTLCardinality.xml
-rw-r--r-- 1 mcc users 23K Feb 25 16:31 LTLFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 25 16:31 LTLFireability.xml
-rw-r--r-- 1 mcc users 22K Feb 26 01:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 190K Feb 26 01:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 36K Feb 26 01:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 166K Feb 26 01:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.7K Feb 25 16:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 340K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-00
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-01
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-02
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-03
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-04
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-05
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-06
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-07
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-08
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-09
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-10
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-11
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-12
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-13
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-14
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678834562949

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PermAdmissibility-PT-50
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 22:56:06] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 22:56:06] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 22:56:07] [INFO ] Load time of PNML (sax parser for PT used): 199 ms
[2023-03-14 22:56:07] [INFO ] Transformed 168 places.
[2023-03-14 22:56:07] [INFO ] Transformed 592 transitions.
[2023-03-14 22:56:07] [INFO ] Parsed PT model containing 168 places and 592 transitions and 3456 arcs in 367 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 71 ms.
Support contains 104 out of 168 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 168/168 places, 592/592 transitions.
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 104 transition count 592
Applied a total of 64 rules in 32 ms. Remains 104 /168 variables (removed 64) and now considering 592/592 (removed 0) transitions.
// Phase 1: matrix 592 rows 104 cols
[2023-03-14 22:56:07] [INFO ] Computed 16 place invariants in 31 ms
[2023-03-14 22:56:07] [INFO ] Implicit Places using invariants in 298 ms returned []
[2023-03-14 22:56:07] [INFO ] Invariant cache hit.
[2023-03-14 22:56:08] [INFO ] Implicit Places using invariants and state equation in 471 ms returned []
Implicit Place search using SMT with State Equation took 820 ms to find 0 implicit places.
[2023-03-14 22:56:08] [INFO ] Invariant cache hit.
[2023-03-14 22:56:08] [INFO ] Dead Transitions using invariants and state equation in 611 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 104/168 places, 592/592 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1473 ms. Remains : 104/168 places, 592/592 transitions.
Support contains 104 out of 104 places after structural reductions.
[2023-03-14 22:56:09] [INFO ] Flatten gal took : 162 ms
[2023-03-14 22:56:10] [INFO ] Flatten gal took : 124 ms
[2023-03-14 22:56:10] [INFO ] Input system was already deterministic with 592 transitions.
Incomplete random walk after 10009 steps, including 12 resets, run finished after 195 ms. (steps per millisecond=51 ) properties (out of 81) seen :53
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=22 ) properties (out of 28) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 27) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 27) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 27) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 26) seen :8
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 18) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 18) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 17) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 16) seen :0
Running SMT prover for 16 properties.
[2023-03-14 22:56:11] [INFO ] Invariant cache hit.
[2023-03-14 22:56:12] [INFO ] [Real]Absence check using 0 positive and 16 generalized place invariants in 14 ms returned sat
[2023-03-14 22:56:12] [INFO ] After 253ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:16
[2023-03-14 22:56:12] [INFO ] [Nat]Absence check using 0 positive and 16 generalized place invariants in 12 ms returned sat
[2023-03-14 22:56:17] [INFO ] After 4660ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :16
[2023-03-14 22:56:20] [INFO ] After 8085ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :16
Attempting to minimize the solution found.
Minimization took 3002 ms.
[2023-03-14 22:56:23] [INFO ] After 11365ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :16
Finished Parikh walk after 229 steps, including 0 resets, run visited all 2 properties in 16 ms. (steps per millisecond=14 )
Parikh walk visited 16 properties in 254 ms.
[2023-03-14 22:56:24] [INFO ] Flatten gal took : 113 ms
[2023-03-14 22:56:24] [INFO ] Flatten gal took : 86 ms
[2023-03-14 22:56:25] [INFO ] Input system was already deterministic with 592 transitions.
Computed a total of 104 stabilizing places and 592 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 104 transition count 592
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 2 formulas.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 12 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 31 ms
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 34 ms
[2023-03-14 22:56:25] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 6 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 28 ms
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 33 ms
[2023-03-14 22:56:25] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 58 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 59 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 44 ms
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 52 ms
[2023-03-14 22:56:25] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 78 transition count 344
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 78 transition count 344
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 76 place count 54 transition count 108
Iterating global reduction 0 with 24 rules applied. Total rules applied 100 place count 54 transition count 108
Applied a total of 100 rules in 22 ms. Remains 54 /104 variables (removed 50) and now considering 108/592 (removed 484) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 54/104 places, 108/592 transitions.
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 9 ms
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 10 ms
[2023-03-14 22:56:25] [INFO ] Input system was already deterministic with 108 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Applied a total of 0 rules in 4 ms. Remains 104 /104 variables (removed 0) and now considering 592/592 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 104/104 places, 592/592 transitions.
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 41 ms
[2023-03-14 22:56:25] [INFO ] Flatten gal took : 46 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 592 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 9 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 20 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 24 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 78 transition count 344
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 78 transition count 344
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 76 place count 54 transition count 108
Iterating global reduction 0 with 24 rules applied. Total rules applied 100 place count 54 transition count 108
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 102 place count 52 transition count 92
Iterating global reduction 0 with 2 rules applied. Total rules applied 104 place count 52 transition count 92
Applied a total of 104 rules in 17 ms. Remains 52 /104 variables (removed 52) and now considering 92/592 (removed 500) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 52/104 places, 92/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 5 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 5 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 92 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Applied a total of 0 rules in 3 ms. Remains 104 /104 variables (removed 0) and now considering 592/592 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 104/104 places, 592/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 30 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 38 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 592 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 438
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 438
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 30 place count 87 transition count 378
Iterating global reduction 0 with 4 rules applied. Total rules applied 34 place count 87 transition count 378
Applied a total of 34 rules in 8 ms. Remains 87 /104 variables (removed 17) and now considering 378/592 (removed 214) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 87/104 places, 378/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 16 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 17 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 378 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 22 place count 82 transition count 360
Iterating global reduction 0 with 22 rules applied. Total rules applied 44 place count 82 transition count 360
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 58 place count 68 transition count 186
Iterating global reduction 0 with 14 rules applied. Total rules applied 72 place count 68 transition count 186
Applied a total of 72 rules in 23 ms. Remains 68 /104 variables (removed 36) and now considering 186/592 (removed 406) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 68/104 places, 186/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 11 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 11 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 186 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 19 place count 85 transition count 376
Iterating global reduction 0 with 19 rules applied. Total rules applied 38 place count 85 transition count 376
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 45 place count 78 transition count 278
Iterating global reduction 0 with 7 rules applied. Total rules applied 52 place count 78 transition count 278
Applied a total of 52 rules in 10 ms. Remains 78 /104 variables (removed 26) and now considering 278/592 (removed 314) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 78/104 places, 278/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 14 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 13 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 278 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 80 transition count 352
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 80 transition count 352
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 62 place count 66 transition count 180
Iterating global reduction 0 with 14 rules applied. Total rules applied 76 place count 66 transition count 180
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 77 place count 65 transition count 172
Iterating global reduction 0 with 1 rules applied. Total rules applied 78 place count 65 transition count 172
Applied a total of 78 rules in 9 ms. Remains 65 /104 variables (removed 39) and now considering 172/592 (removed 420) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 65/104 places, 172/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 9 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 10 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 172 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 88 transition count 400
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 88 transition count 400
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 41 place count 79 transition count 276
Iterating global reduction 0 with 9 rules applied. Total rules applied 50 place count 79 transition count 276
Applied a total of 50 rules in 7 ms. Remains 79 /104 variables (removed 25) and now considering 276/592 (removed 316) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 79/104 places, 276/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 15 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 16 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 276 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 84 transition count 372
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 84 transition count 372
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 47 place count 77 transition count 272
Iterating global reduction 0 with 7 rules applied. Total rules applied 54 place count 77 transition count 272
Applied a total of 54 rules in 7 ms. Remains 77 /104 variables (removed 27) and now considering 272/592 (removed 320) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 77/104 places, 272/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 14 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 15 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 272 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 87 transition count 390
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 87 transition count 390
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 38 place count 83 transition count 330
Iterating global reduction 0 with 4 rules applied. Total rules applied 42 place count 83 transition count 330
Applied a total of 42 rules in 6 ms. Remains 83 /104 variables (removed 21) and now considering 330/592 (removed 262) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 83/104 places, 330/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 14 ms
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 27 ms
[2023-03-14 22:56:26] [INFO ] Input system was already deterministic with 330 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 80 transition count 352
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 80 transition count 352
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 62 place count 66 transition count 176
Iterating global reduction 0 with 14 rules applied. Total rules applied 76 place count 66 transition count 176
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 77 place count 65 transition count 168
Iterating global reduction 0 with 1 rules applied. Total rules applied 78 place count 65 transition count 168
Applied a total of 78 rules in 11 ms. Remains 65 /104 variables (removed 39) and now considering 168/592 (removed 424) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 65/104 places, 168/592 transitions.
[2023-03-14 22:56:26] [INFO ] Flatten gal took : 13 ms
[2023-03-14 22:56:27] [INFO ] Flatten gal took : 13 ms
[2023-03-14 22:56:27] [INFO ] Input system was already deterministic with 168 transitions.
[2023-03-14 22:56:27] [INFO ] Flatten gal took : 115 ms
[2023-03-14 22:56:27] [INFO ] Flatten gal took : 97 ms
[2023-03-14 22:56:28] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 36 ms.
[2023-03-14 22:56:28] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 104 places, 592 transitions and 2944 arcs took 4 ms.
Total runtime 21568 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PermAdmissibility-PT-50
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/367
CTLFireability

FORMULA PermAdmissibility-PT-50-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-50-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-50-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-PT-50-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678836745892

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/367/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/367/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/367/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 32 (type EXCL) for 21 PermAdmissibility-PT-50-CTLFireability-07
lola: time limit : 102 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:663
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: FINISHED task # 32 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-07
lola: result : true
lola: markings : 16
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 81 (type EXCL) for 21 PermAdmissibility-PT-50-CTLFireability-07
lola: time limit : 105 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 83 (type FNDP) for 21 PermAdmissibility-PT-50-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type EQUN) for 21 PermAdmissibility-PT-50-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 88 (type SRCH) for 21 PermAdmissibility-PT-50-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 83 (type FNDP) for PermAdmissibility-PT-50-CTLFireability-07
lola: result : true
lola: fired transitions : 14
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 81 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-07 (obsolete)
lola: CANCELED task # 84 (type EQUN) for PermAdmissibility-PT-50-CTLFireability-07 (obsolete)
lola: CANCELED task # 88 (type SRCH) for PermAdmissibility-PT-50-CTLFireability-07 (obsolete)
lola: LAUNCH task # 86 (type EXCL) for 18 PermAdmissibility-PT-50-CTLFireability-06
lola: time limit : 143 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
sara: try reading problem file /home/mcc/execution/367/CTLFireability-84.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 91 (type FNDP) for 62 PermAdmissibility-PT-50-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 92 (type EQUN) for 62 PermAdmissibility-PT-50-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type SRCH) for 62 PermAdmissibility-PT-50-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 91 (type FNDP) for PermAdmissibility-PT-50-CTLFireability-14
lola: result : true
lola: fired transitions : 34
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 94 (type SRCH) for PermAdmissibility-PT-50-CTLFireability-14
lola: result : true
lola: markings : 22
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 92 (type EQUN) for PermAdmissibility-PT-50-CTLFireability-14 (obsolete)
sara: try reading problem file /home/mcc/execution/367/CTLFireability-92.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.

lola: FINISHED task # 92 (type EQUN) for PermAdmissibility-PT-50-CTLFireability-14
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 8 0 0 4
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 4/179 1/32 PermAdmissibility-PT-50-CTLFireability-06 118955 m, 23791 m/sec, 580525 t fired, .

Time elapsed: 20 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16

lola: FINISHED task # 84 (type EQUN) for PermAdmissibility-PT-50-CTLFireability-07
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 9/179 2/32 PermAdmissibility-PT-50-CTLFireability-06 286687 m, 33546 m/sec, 1499495 t fired, .

Time elapsed: 25 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 14/179 2/32 PermAdmissibility-PT-50-CTLFireability-06 451842 m, 33031 m/sec, 2444160 t fired, .

Time elapsed: 30 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 19/179 3/32 PermAdmissibility-PT-50-CTLFireability-06 614356 m, 32502 m/sec, 3393327 t fired, .

Time elapsed: 35 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 24/179 4/32 PermAdmissibility-PT-50-CTLFireability-06 776871 m, 32503 m/sec, 4362192 t fired, .

Time elapsed: 40 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 29/179 4/32 PermAdmissibility-PT-50-CTLFireability-06 928811 m, 30388 m/sec, 5282580 t fired, .

Time elapsed: 45 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 34/179 5/32 PermAdmissibility-PT-50-CTLFireability-06 1085181 m, 31274 m/sec, 6204827 t fired, .

Time elapsed: 50 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 39/179 5/32 PermAdmissibility-PT-50-CTLFireability-06 1240962 m, 31156 m/sec, 7189426 t fired, .

Time elapsed: 55 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 44/179 6/32 PermAdmissibility-PT-50-CTLFireability-06 1398911 m, 31589 m/sec, 8184963 t fired, .

Time elapsed: 60 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 49/179 7/32 PermAdmissibility-PT-50-CTLFireability-06 1556865 m, 31590 m/sec, 9151167 t fired, .

Time elapsed: 65 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 54/179 7/32 PermAdmissibility-PT-50-CTLFireability-06 1699291 m, 28485 m/sec, 10073341 t fired, .

Time elapsed: 70 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 59/179 8/32 PermAdmissibility-PT-50-CTLFireability-06 1856903 m, 31522 m/sec, 11034846 t fired, .

Time elapsed: 75 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 64/179 8/32 PermAdmissibility-PT-50-CTLFireability-06 2008296 m, 30278 m/sec, 11963601 t fired, .

Time elapsed: 80 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 69/179 9/32 PermAdmissibility-PT-50-CTLFireability-06 2163849 m, 31110 m/sec, 12939201 t fired, .

Time elapsed: 85 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 74/179 10/32 PermAdmissibility-PT-50-CTLFireability-06 2316104 m, 30451 m/sec, 13935658 t fired, .

Time elapsed: 90 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 79/179 10/32 PermAdmissibility-PT-50-CTLFireability-06 2469537 m, 30686 m/sec, 14950558 t fired, .

Time elapsed: 95 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 84/179 11/32 PermAdmissibility-PT-50-CTLFireability-06 2619102 m, 29913 m/sec, 16001717 t fired, .

Time elapsed: 100 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 89/179 12/32 PermAdmissibility-PT-50-CTLFireability-06 2779738 m, 32127 m/sec, 16944131 t fired, .

Time elapsed: 105 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 94/179 12/32 PermAdmissibility-PT-50-CTLFireability-06 2933088 m, 30670 m/sec, 17926363 t fired, .

Time elapsed: 110 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 99/179 13/32 PermAdmissibility-PT-50-CTLFireability-06 3072268 m, 27836 m/sec, 18840555 t fired, .

Time elapsed: 115 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 104/179 13/32 PermAdmissibility-PT-50-CTLFireability-06 3220767 m, 29699 m/sec, 19857551 t fired, .

Time elapsed: 120 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 109/179 14/32 PermAdmissibility-PT-50-CTLFireability-06 3346867 m, 25220 m/sec, 20739049 t fired, .

Time elapsed: 125 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 114/179 14/32 PermAdmissibility-PT-50-CTLFireability-06 3492521 m, 29130 m/sec, 21579681 t fired, .

Time elapsed: 130 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 119/179 15/32 PermAdmissibility-PT-50-CTLFireability-06 3648359 m, 31167 m/sec, 22549660 t fired, .

Time elapsed: 135 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 124/179 16/32 PermAdmissibility-PT-50-CTLFireability-06 3800063 m, 30340 m/sec, 23543106 t fired, .

Time elapsed: 140 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 129/179 16/32 PermAdmissibility-PT-50-CTLFireability-06 3951503 m, 30288 m/sec, 24535625 t fired, .

Time elapsed: 145 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 134/179 17/32 PermAdmissibility-PT-50-CTLFireability-06 4104817 m, 30662 m/sec, 25556008 t fired, .

Time elapsed: 150 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 139/179 17/32 PermAdmissibility-PT-50-CTLFireability-06 4256175 m, 30271 m/sec, 26571743 t fired, .

Time elapsed: 155 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 144/179 18/32 PermAdmissibility-PT-50-CTLFireability-06 4403808 m, 29526 m/sec, 27592510 t fired, .

Time elapsed: 160 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 149/179 19/32 PermAdmissibility-PT-50-CTLFireability-06 4553387 m, 29915 m/sec, 28611187 t fired, .

Time elapsed: 165 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 154/179 19/32 PermAdmissibility-PT-50-CTLFireability-06 4699681 m, 29258 m/sec, 29648055 t fired, .

Time elapsed: 170 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 159/179 20/32 PermAdmissibility-PT-50-CTLFireability-06 4844963 m, 29056 m/sec, 30701537 t fired, .

Time elapsed: 175 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 164/179 20/32 PermAdmissibility-PT-50-CTLFireability-06 5017220 m, 34451 m/sec, 31585629 t fired, .

Time elapsed: 180 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 169/179 21/32 PermAdmissibility-PT-50-CTLFireability-06 5184086 m, 33373 m/sec, 32515191 t fired, .

Time elapsed: 185 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 174/179 22/32 PermAdmissibility-PT-50-CTLFireability-06 5341375 m, 31457 m/sec, 33409361 t fired, .

Time elapsed: 190 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 179/179 22/32 PermAdmissibility-PT-50-CTLFireability-06 5487982 m, 29321 m/sec, 34295332 t fired, .

Time elapsed: 195 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 86 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-06 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 1 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 200 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 78 (type EXCL) for 77 PermAdmissibility-PT-50-CTLFireability-15
lola: time limit : 178 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 86 (type EXCL) for 18 PermAdmissibility-PT-50-CTLFireability-06
lola: time limit : 3400 sec
lola: memory limit: 5 pages
lola: FINISHED task # 78 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-15
lola: result : true
lola: markings : 801
lola: fired transitions : 803
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 5/178 1/5 PermAdmissibility-PT-50-CTLFireability-06 148264 m, -1067943 m/sec, 739996 t fired, .

Time elapsed: 205 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 10/178 2/5 PermAdmissibility-PT-50-CTLFireability-06 309051 m, 32157 m/sec, 1632991 t fired, .

Time elapsed: 210 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 15/178 2/5 PermAdmissibility-PT-50-CTLFireability-06 470439 m, 32277 m/sec, 2545587 t fired, .

Time elapsed: 215 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 20/178 3/5 PermAdmissibility-PT-50-CTLFireability-06 628744 m, 31661 m/sec, 3479745 t fired, .

Time elapsed: 220 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 25/178 4/5 PermAdmissibility-PT-50-CTLFireability-06 786101 m, 31471 m/sec, 4420035 t fired, .

Time elapsed: 225 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 30/178 4/5 PermAdmissibility-PT-50-CTLFireability-06 943172 m, 31414 m/sec, 5361233 t fired, .

Time elapsed: 230 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 35/178 5/5 PermAdmissibility-PT-50-CTLFireability-06 1099971 m, 31359 m/sec, 6296495 t fired, .

Time elapsed: 235 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EXEG EXCL 40/178 5/5 PermAdmissibility-PT-50-CTLFireability-06 1253186 m, 30643 m/sec, 7262162 t fired, .

Time elapsed: 240 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 86 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: DISJ 0 3 0 0 7 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 245 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 75 (type EXCL) for 62 PermAdmissibility-PT-50-CTLFireability-14
lola: time limit : 186 sec
lola: memory limit: 32 pages
lola: FINISHED task # 75 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-14
lola: result : false
lola: markings : 801
lola: fired transitions : 800
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 65 (type EXCL) for 62 PermAdmissibility-PT-50-CTLFireability-14
lola: time limit : 209 sec
lola: memory limit: 32 pages
lola: FINISHED task # 65 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-14
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 60 (type EXCL) for 59 PermAdmissibility-PT-50-CTLFireability-13
lola: time limit : 223 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 5/223 3/32 PermAdmissibility-PT-50-CTLFireability-13 432574 m, 86514 m/sec, 3860740 t fired, .

Time elapsed: 250 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 10/223 5/32 PermAdmissibility-PT-50-CTLFireability-13 818809 m, 77247 m/sec, 8062199 t fired, .

Time elapsed: 255 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 15/223 7/32 PermAdmissibility-PT-50-CTLFireability-13 1081499 m, 52538 m/sec, 12509466 t fired, .

Time elapsed: 260 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 20/223 8/32 PermAdmissibility-PT-50-CTLFireability-13 1338090 m, 51318 m/sec, 16856484 t fired, .

Time elapsed: 265 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 25/223 10/32 PermAdmissibility-PT-50-CTLFireability-13 1584117 m, 49205 m/sec, 21222947 t fired, .

Time elapsed: 270 secs. Pages in use: 33
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 30/223 11/32 PermAdmissibility-PT-50-CTLFireability-13 1829434 m, 49063 m/sec, 25520488 t fired, .

Time elapsed: 275 secs. Pages in use: 34
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 35/223 13/32 PermAdmissibility-PT-50-CTLFireability-13 2072587 m, 48630 m/sec, 29788069 t fired, .

Time elapsed: 280 secs. Pages in use: 36
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 40/223 14/32 PermAdmissibility-PT-50-CTLFireability-13 2313511 m, 48184 m/sec, 34029600 t fired, .

Time elapsed: 285 secs. Pages in use: 37
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 45/223 15/32 PermAdmissibility-PT-50-CTLFireability-13 2552434 m, 47784 m/sec, 38241315 t fired, .

Time elapsed: 290 secs. Pages in use: 38
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 50/223 17/32 PermAdmissibility-PT-50-CTLFireability-13 2790634 m, 47640 m/sec, 42401078 t fired, .

Time elapsed: 295 secs. Pages in use: 40
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 55/223 18/32 PermAdmissibility-PT-50-CTLFireability-13 3068397 m, 55552 m/sec, 46779727 t fired, .

Time elapsed: 300 secs. Pages in use: 41
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 60/223 20/32 PermAdmissibility-PT-50-CTLFireability-13 3303980 m, 47116 m/sec, 51091090 t fired, .

Time elapsed: 305 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 65/223 21/32 PermAdmissibility-PT-50-CTLFireability-13 3529565 m, 45117 m/sec, 55392029 t fired, .

Time elapsed: 310 secs. Pages in use: 44
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 70/223 22/32 PermAdmissibility-PT-50-CTLFireability-13 3750625 m, 44212 m/sec, 59650194 t fired, .

Time elapsed: 315 secs. Pages in use: 45
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 75/223 23/32 PermAdmissibility-PT-50-CTLFireability-13 3960761 m, 42027 m/sec, 63845111 t fired, .

Time elapsed: 320 secs. Pages in use: 46
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 80/223 25/32 PermAdmissibility-PT-50-CTLFireability-13 4177630 m, 43373 m/sec, 68045555 t fired, .

Time elapsed: 325 secs. Pages in use: 48
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 85/223 26/32 PermAdmissibility-PT-50-CTLFireability-13 4395750 m, 43624 m/sec, 72271422 t fired, .

Time elapsed: 330 secs. Pages in use: 49
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 90/223 27/32 PermAdmissibility-PT-50-CTLFireability-13 4604137 m, 41677 m/sec, 76468905 t fired, .

Time elapsed: 335 secs. Pages in use: 50
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 95/223 28/32 PermAdmissibility-PT-50-CTLFireability-13 4813144 m, 41801 m/sec, 80595200 t fired, .

Time elapsed: 340 secs. Pages in use: 51
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 100/223 30/32 PermAdmissibility-PT-50-CTLFireability-13 5020625 m, 41496 m/sec, 84731956 t fired, .

Time elapsed: 345 secs. Pages in use: 53
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 105/223 31/32 PermAdmissibility-PT-50-CTLFireability-13 5226993 m, 41273 m/sec, 88826430 t fired, .

Time elapsed: 350 secs. Pages in use: 54
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 110/223 32/32 PermAdmissibility-PT-50-CTLFireability-13 5436732 m, 41947 m/sec, 92992647 t fired, .

Time elapsed: 355 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 60 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 360 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 57 (type EXCL) for 56 PermAdmissibility-PT-50-CTLFireability-12
lola: time limit : 231 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-12
lola: result : false
lola: markings : 851
lola: fired transitions : 850
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 PermAdmissibility-PT-50-CTLFireability-11
lola: time limit : 249 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 5/249 2/32 PermAdmissibility-PT-50-CTLFireability-11 228148 m, 45629 m/sec, 1757510 t fired, .

Time elapsed: 365 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 10/249 3/32 PermAdmissibility-PT-50-CTLFireability-11 456839 m, 45738 m/sec, 3627108 t fired, .

Time elapsed: 370 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 15/249 5/32 PermAdmissibility-PT-50-CTLFireability-11 682074 m, 45047 m/sec, 5487470 t fired, .

Time elapsed: 375 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 20/249 5/32 PermAdmissibility-PT-50-CTLFireability-11 810462 m, 25677 m/sec, 7157454 t fired, .

Time elapsed: 380 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 25/249 6/32 PermAdmissibility-PT-50-CTLFireability-11 919607 m, 21829 m/sec, 8806646 t fired, .

Time elapsed: 385 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 30/249 7/32 PermAdmissibility-PT-50-CTLFireability-11 1025324 m, 21143 m/sec, 10449699 t fired, .

Time elapsed: 390 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 35/249 7/32 PermAdmissibility-PT-50-CTLFireability-11 1118823 m, 18699 m/sec, 12053718 t fired, .

Time elapsed: 395 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 40/249 8/32 PermAdmissibility-PT-50-CTLFireability-11 1220939 m, 20423 m/sec, 13679637 t fired, .

Time elapsed: 400 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 45/249 8/32 PermAdmissibility-PT-50-CTLFireability-11 1327881 m, 21388 m/sec, 15324269 t fired, .

Time elapsed: 405 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 50/249 9/32 PermAdmissibility-PT-50-CTLFireability-11 1418309 m, 18085 m/sec, 16917351 t fired, .

Time elapsed: 410 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 55/249 9/32 PermAdmissibility-PT-50-CTLFireability-11 1524005 m, 21139 m/sec, 18564178 t fired, .

Time elapsed: 415 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 60/249 10/32 PermAdmissibility-PT-50-CTLFireability-11 1615088 m, 18216 m/sec, 20156752 t fired, .

Time elapsed: 420 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 65/249 11/32 PermAdmissibility-PT-50-CTLFireability-11 1722277 m, 21437 m/sec, 21803211 t fired, .

Time elapsed: 425 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 70/249 11/32 PermAdmissibility-PT-50-CTLFireability-11 1811276 m, 17799 m/sec, 23382802 t fired, .

Time elapsed: 430 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 75/249 12/32 PermAdmissibility-PT-50-CTLFireability-11 1921502 m, 22045 m/sec, 25037824 t fired, .

Time elapsed: 435 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 80/249 12/32 PermAdmissibility-PT-50-CTLFireability-11 2004463 m, 16592 m/sec, 26594003 t fired, .

Time elapsed: 440 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 85/249 13/32 PermAdmissibility-PT-50-CTLFireability-11 2100880 m, 19283 m/sec, 28208583 t fired, .

Time elapsed: 445 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 90/249 13/32 PermAdmissibility-PT-50-CTLFireability-11 2205070 m, 20838 m/sec, 29834830 t fired, .

Time elapsed: 450 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 95/249 14/32 PermAdmissibility-PT-50-CTLFireability-11 2294986 m, 17983 m/sec, 31415221 t fired, .

Time elapsed: 455 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 100/249 15/32 PermAdmissibility-PT-50-CTLFireability-11 2401944 m, 21391 m/sec, 33060408 t fired, .

Time elapsed: 460 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 105/249 15/32 PermAdmissibility-PT-50-CTLFireability-11 2488912 m, 17393 m/sec, 34624889 t fired, .

Time elapsed: 465 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 110/249 16/32 PermAdmissibility-PT-50-CTLFireability-11 2583829 m, 18983 m/sec, 36224255 t fired, .

Time elapsed: 470 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 115/249 16/32 PermAdmissibility-PT-50-CTLFireability-11 2696641 m, 22562 m/sec, 37878287 t fired, .

Time elapsed: 475 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 120/249 17/32 PermAdmissibility-PT-50-CTLFireability-11 2774347 m, 15541 m/sec, 39408801 t fired, .

Time elapsed: 480 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 125/249 17/32 PermAdmissibility-PT-50-CTLFireability-11 2893961 m, 23922 m/sec, 41082389 t fired, .

Time elapsed: 485 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 130/249 18/32 PermAdmissibility-PT-50-CTLFireability-11 3012740 m, 23755 m/sec, 42743769 t fired, .

Time elapsed: 490 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 135/249 19/32 PermAdmissibility-PT-50-CTLFireability-11 3108029 m, 19057 m/sec, 44353326 t fired, .

Time elapsed: 495 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 140/249 19/32 PermAdmissibility-PT-50-CTLFireability-11 3197973 m, 17988 m/sec, 45958563 t fired, .

Time elapsed: 500 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 145/249 20/32 PermAdmissibility-PT-50-CTLFireability-11 3287454 m, 17896 m/sec, 47577276 t fired, .

Time elapsed: 505 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 150/249 20/32 PermAdmissibility-PT-50-CTLFireability-11 3377703 m, 18049 m/sec, 49183865 t fired, .

Time elapsed: 510 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 155/249 21/32 PermAdmissibility-PT-50-CTLFireability-11 3467640 m, 17987 m/sec, 50801324 t fired, .

Time elapsed: 515 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 160/249 21/32 PermAdmissibility-PT-50-CTLFireability-11 3557815 m, 18035 m/sec, 52411119 t fired, .

Time elapsed: 520 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 165/249 22/32 PermAdmissibility-PT-50-CTLFireability-11 3644760 m, 17389 m/sec, 54013315 t fired, .

Time elapsed: 525 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 170/249 22/32 PermAdmissibility-PT-50-CTLFireability-11 3736336 m, 18315 m/sec, 55634607 t fired, .

Time elapsed: 530 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 175/249 23/32 PermAdmissibility-PT-50-CTLFireability-11 3818445 m, 16421 m/sec, 57213717 t fired, .

Time elapsed: 535 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 180/249 23/32 PermAdmissibility-PT-50-CTLFireability-11 3905164 m, 17343 m/sec, 58806472 t fired, .

Time elapsed: 540 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 185/249 24/32 PermAdmissibility-PT-50-CTLFireability-11 3986688 m, 16304 m/sec, 60384652 t fired, .

Time elapsed: 545 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 190/249 24/32 PermAdmissibility-PT-50-CTLFireability-11 4078753 m, 18413 m/sec, 61987861 t fired, .

Time elapsed: 550 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 195/249 25/32 PermAdmissibility-PT-50-CTLFireability-11 4161815 m, 16612 m/sec, 63572272 t fired, .

Time elapsed: 555 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 200/249 25/32 PermAdmissibility-PT-50-CTLFireability-11 4245682 m, 16773 m/sec, 65172426 t fired, .

Time elapsed: 560 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 205/249 26/32 PermAdmissibility-PT-50-CTLFireability-11 4340769 m, 19017 m/sec, 66798794 t fired, .

Time elapsed: 565 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 210/249 26/32 PermAdmissibility-PT-50-CTLFireability-11 4419906 m, 15827 m/sec, 68364273 t fired, .

Time elapsed: 570 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 215/249 27/32 PermAdmissibility-PT-50-CTLFireability-11 4503057 m, 16630 m/sec, 69948014 t fired, .

Time elapsed: 575 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 220/249 27/32 PermAdmissibility-PT-50-CTLFireability-11 4586751 m, 16738 m/sec, 71542953 t fired, .

Time elapsed: 580 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 225/249 28/32 PermAdmissibility-PT-50-CTLFireability-11 4682264 m, 19102 m/sec, 73167680 t fired, .

Time elapsed: 585 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 230/249 28/32 PermAdmissibility-PT-50-CTLFireability-11 4761229 m, 15793 m/sec, 74724345 t fired, .

Time elapsed: 590 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 235/249 28/32 PermAdmissibility-PT-50-CTLFireability-11 4838536 m, 15461 m/sec, 76288002 t fired, .

Time elapsed: 595 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 240/249 29/32 PermAdmissibility-PT-50-CTLFireability-11 4924480 m, 17188 m/sec, 77878191 t fired, .

Time elapsed: 600 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 245/249 29/32 PermAdmissibility-PT-50-CTLFireability-11 5006861 m, 16476 m/sec, 79461208 t fired, .

Time elapsed: 605 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-11 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 1 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 610 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 51 (type EXCL) for 50 PermAdmissibility-PT-50-CTLFireability-10
lola: time limit : 249 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 54 (type EXCL) for 53 PermAdmissibility-PT-50-CTLFireability-11
lola: time limit : 2990 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 5/249 5/32 PermAdmissibility-PT-50-CTLFireability-10 907888 m, 181577 m/sec, 1096786 t fired, .
54 CTL EXCL 5/2990 2/5 PermAdmissibility-PT-50-CTLFireability-11 228438 m, -955684 m/sec, 1759955 t fired, .

Time elapsed: 615 secs. Pages in use: 60
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 10/249 10/32 PermAdmissibility-PT-50-CTLFireability-10 1811556 m, 180733 m/sec, 2243376 t fired, .
54 CTL EXCL 10/230 3/5 PermAdmissibility-PT-50-CTLFireability-11 450742 m, 44460 m/sec, 3576964 t fired, .

Time elapsed: 620 secs. Pages in use: 66
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 15/249 15/32 PermAdmissibility-PT-50-CTLFireability-10 2685965 m, 174881 m/sec, 3426495 t fired, .
54 CTL EXCL 15/230 5/5 PermAdmissibility-PT-50-CTLFireability-11 668665 m, 43584 m/sec, 5374949 t fired, .

Time elapsed: 625 secs. Pages in use: 73
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 20/249 19/32 PermAdmissibility-PT-50-CTLFireability-10 3532866 m, 169380 m/sec, 4649272 t fired, .
54 CTL EXCL 20/230 5/5 PermAdmissibility-PT-50-CTLFireability-11 801823 m, 26631 m/sec, 7024939 t fired, .

Time elapsed: 630 secs. Pages in use: 77
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 25/249 24/32 PermAdmissibility-PT-50-CTLFireability-10 4343447 m, 162116 m/sec, 5875747 t fired, .

Time elapsed: 635 secs. Pages in use: 78
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 30/249 28/32 PermAdmissibility-PT-50-CTLFireability-10 5127434 m, 156797 m/sec, 7242722 t fired, .

Time elapsed: 640 secs. Pages in use: 81
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 35/249 32/32 PermAdmissibility-PT-50-CTLFireability-10 5950566 m, 164626 m/sec, 8587681 t fired, .

Time elapsed: 645 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 51 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 3 0 0 9 0 0 3
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 650 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 45 (type EXCL) for 44 PermAdmissibility-PT-50-CTLFireability-08
lola: time limit : 268 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-08
lola: result : false
lola: markings : 801
lola: fired transitions : 1602
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 21 PermAdmissibility-PT-50-CTLFireability-07
lola: time limit : 295 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-07
lola: result : true
lola: markings : 1408
lola: fired transitions : 1407
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 21 PermAdmissibility-PT-50-CTLFireability-07
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-07
lola: result : true
lola: markings : 1412
lola: fired transitions : 1411
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 PermAdmissibility-PT-50-CTLFireability-05
lola: time limit : 368 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/368 3/32 PermAdmissibility-PT-50-CTLFireability-05 438594 m, 87718 m/sec, 3916940 t fired, .

Time elapsed: 655 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/368 5/32 PermAdmissibility-PT-50-CTLFireability-05 824498 m, 77180 m/sec, 8153644 t fired, .

Time elapsed: 660 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/368 7/32 PermAdmissibility-PT-50-CTLFireability-05 1088557 m, 52811 m/sec, 12623754 t fired, .

Time elapsed: 665 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/368 8/32 PermAdmissibility-PT-50-CTLFireability-05 1344700 m, 51228 m/sec, 16991120 t fired, .

Time elapsed: 670 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/368 10/32 PermAdmissibility-PT-50-CTLFireability-05 1593180 m, 49696 m/sec, 21381567 t fired, .

Time elapsed: 675 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 30/368 11/32 PermAdmissibility-PT-50-CTLFireability-05 1840145 m, 49393 m/sec, 25699893 t fired, .

Time elapsed: 680 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 35/368 13/32 PermAdmissibility-PT-50-CTLFireability-05 2083812 m, 48733 m/sec, 30000612 t fired, .

Time elapsed: 685 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 40/368 14/32 PermAdmissibility-PT-50-CTLFireability-05 2327524 m, 48742 m/sec, 34276276 t fired, .

Time elapsed: 690 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 45/368 15/32 PermAdmissibility-PT-50-CTLFireability-05 2568523 m, 48199 m/sec, 38529840 t fired, .

Time elapsed: 695 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 50/368 17/32 PermAdmissibility-PT-50-CTLFireability-05 2822641 m, 50823 m/sec, 42720398 t fired, .

Time elapsed: 700 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 55/368 18/32 PermAdmissibility-PT-50-CTLFireability-05 3090936 m, 53659 m/sec, 47138806 t fired, .

Time elapsed: 705 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 60/368 20/32 PermAdmissibility-PT-50-CTLFireability-05 3324117 m, 46636 m/sec, 51489434 t fired, .

Time elapsed: 710 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 65/368 21/32 PermAdmissibility-PT-50-CTLFireability-05 3550798 m, 45336 m/sec, 55818212 t fired, .

Time elapsed: 715 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 70/368 22/32 PermAdmissibility-PT-50-CTLFireability-05 3774746 m, 44789 m/sec, 60113969 t fired, .

Time elapsed: 720 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 75/368 24/32 PermAdmissibility-PT-50-CTLFireability-05 3984897 m, 42030 m/sec, 64329754 t fired, .

Time elapsed: 725 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 80/368 25/32 PermAdmissibility-PT-50-CTLFireability-05 4204143 m, 43849 m/sec, 68578570 t fired, .

Time elapsed: 730 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 85/368 26/32 PermAdmissibility-PT-50-CTLFireability-05 4421636 m, 43498 m/sec, 72817334 t fired, .

Time elapsed: 735 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 90/368 27/32 PermAdmissibility-PT-50-CTLFireability-05 4632897 m, 42252 m/sec, 77054665 t fired, .

Time elapsed: 740 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 95/368 29/32 PermAdmissibility-PT-50-CTLFireability-05 4844144 m, 42249 m/sec, 81211589 t fired, .

Time elapsed: 745 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 100/368 30/32 PermAdmissibility-PT-50-CTLFireability-05 5060609 m, 43293 m/sec, 85374798 t fired, .

Time elapsed: 750 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 105/368 31/32 PermAdmissibility-PT-50-CTLFireability-05 5264520 m, 40782 m/sec, 89539151 t fired, .

Time elapsed: 755 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 110/368 32/32 PermAdmissibility-PT-50-CTLFireability-05 5482578 m, 43611 m/sec, 93709182 t fired, .

Time elapsed: 760 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 765 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 PermAdmissibility-PT-50-CTLFireability-04
lola: time limit : 405 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/405 1/32 PermAdmissibility-PT-50-CTLFireability-04 31651 m, 6330 m/sec, 70053 t fired, .

Time elapsed: 770 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/405 1/32 PermAdmissibility-PT-50-CTLFireability-04 69588 m, 7587 m/sec, 154345 t fired, .

Time elapsed: 775 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/405 1/32 PermAdmissibility-PT-50-CTLFireability-04 107446 m, 7571 m/sec, 238565 t fired, .

Time elapsed: 780 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/405 1/32 PermAdmissibility-PT-50-CTLFireability-04 145333 m, 7577 m/sec, 322889 t fired, .

Time elapsed: 785 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/405 2/32 PermAdmissibility-PT-50-CTLFireability-04 183145 m, 7562 m/sec, 407070 t fired, .

Time elapsed: 790 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/405 2/32 PermAdmissibility-PT-50-CTLFireability-04 216671 m, 6705 m/sec, 480936 t fired, .

Time elapsed: 795 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/405 2/32 PermAdmissibility-PT-50-CTLFireability-04 246378 m, 5941 m/sec, 546731 t fired, .

Time elapsed: 800 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/405 2/32 PermAdmissibility-PT-50-CTLFireability-04 276040 m, 5932 m/sec, 612702 t fired, .

Time elapsed: 805 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/405 2/32 PermAdmissibility-PT-50-CTLFireability-04 305642 m, 5920 m/sec, 678373 t fired, .

Time elapsed: 810 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 50/405 2/32 PermAdmissibility-PT-50-CTLFireability-04 335266 m, 5924 m/sec, 744462 t fired, .

Time elapsed: 815 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 55/405 3/32 PermAdmissibility-PT-50-CTLFireability-04 364797 m, 5906 m/sec, 810069 t fired, .

Time elapsed: 820 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 60/405 3/32 PermAdmissibility-PT-50-CTLFireability-04 394399 m, 5920 m/sec, 876157 t fired, .

Time elapsed: 825 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 65/405 3/32 PermAdmissibility-PT-50-CTLFireability-04 422766 m, 5673 m/sec, 939402 t fired, .

Time elapsed: 830 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 70/405 3/32 PermAdmissibility-PT-50-CTLFireability-04 450902 m, 5627 m/sec, 1002131 t fired, .

Time elapsed: 835 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 75/405 3/32 PermAdmissibility-PT-50-CTLFireability-04 480427 m, 5905 m/sec, 1067797 t fired, .

Time elapsed: 840 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 80/405 3/32 PermAdmissibility-PT-50-CTLFireability-04 509962 m, 5907 m/sec, 1133511 t fired, .

Time elapsed: 845 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 85/405 4/32 PermAdmissibility-PT-50-CTLFireability-04 539490 m, 5905 m/sec, 1199503 t fired, .

Time elapsed: 850 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 90/405 4/32 PermAdmissibility-PT-50-CTLFireability-04 568992 m, 5900 m/sec, 1265411 t fired, .

Time elapsed: 855 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 95/405 4/32 PermAdmissibility-PT-50-CTLFireability-04 598525 m, 5906 m/sec, 1331200 t fired, .

Time elapsed: 860 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 100/405 4/32 PermAdmissibility-PT-50-CTLFireability-04 628086 m, 5912 m/sec, 1397114 t fired, .

Time elapsed: 865 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 105/405 4/32 PermAdmissibility-PT-50-CTLFireability-04 657757 m, 5934 m/sec, 1463298 t fired, .

Time elapsed: 870 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 110/405 5/32 PermAdmissibility-PT-50-CTLFireability-04 685383 m, 5525 m/sec, 1524274 t fired, .

Time elapsed: 875 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 115/405 5/32 PermAdmissibility-PT-50-CTLFireability-04 714999 m, 5923 m/sec, 1589775 t fired, .

Time elapsed: 880 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 120/405 5/32 PermAdmissibility-PT-50-CTLFireability-04 744624 m, 5925 m/sec, 1655462 t fired, .

Time elapsed: 885 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 125/405 5/32 PermAdmissibility-PT-50-CTLFireability-04 774164 m, 5908 m/sec, 1721248 t fired, .

Time elapsed: 890 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 130/405 5/32 PermAdmissibility-PT-50-CTLFireability-04 803731 m, 5913 m/sec, 1787066 t fired, .

Time elapsed: 895 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 135/405 5/32 PermAdmissibility-PT-50-CTLFireability-04 830818 m, 5417 m/sec, 1847434 t fired, .

Time elapsed: 900 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 140/405 6/32 PermAdmissibility-PT-50-CTLFireability-04 860348 m, 5906 m/sec, 1913040 t fired, .

Time elapsed: 905 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 145/405 6/32 PermAdmissibility-PT-50-CTLFireability-04 889860 m, 5902 m/sec, 1978923 t fired, .

Time elapsed: 910 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 150/405 6/32 PermAdmissibility-PT-50-CTLFireability-04 918785 m, 5785 m/sec, 2043410 t fired, .

Time elapsed: 915 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 155/405 6/32 PermAdmissibility-PT-50-CTLFireability-04 948331 m, 5909 m/sec, 2109296 t fired, .

Time elapsed: 920 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 160/405 6/32 PermAdmissibility-PT-50-CTLFireability-04 977864 m, 5906 m/sec, 2175018 t fired, .

Time elapsed: 925 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 165/405 6/32 PermAdmissibility-PT-50-CTLFireability-04 1007418 m, 5910 m/sec, 2240780 t fired, .

Time elapsed: 930 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 170/405 6/32 PermAdmissibility-PT-50-CTLFireability-04 1036979 m, 5912 m/sec, 2306655 t fired, .

Time elapsed: 935 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 175/405 7/32 PermAdmissibility-PT-50-CTLFireability-04 1066528 m, 5909 m/sec, 2372630 t fired, .

Time elapsed: 940 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 180/405 7/32 PermAdmissibility-PT-50-CTLFireability-04 1096046 m, 5903 m/sec, 2438529 t fired, .

Time elapsed: 945 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 185/405 7/32 PermAdmissibility-PT-50-CTLFireability-04 1125590 m, 5908 m/sec, 2504477 t fired, .

Time elapsed: 950 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 190/405 7/32 PermAdmissibility-PT-50-CTLFireability-04 1154211 m, 5724 m/sec, 2568309 t fired, .

Time elapsed: 955 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 195/405 7/32 PermAdmissibility-PT-50-CTLFireability-04 1184125 m, 5982 m/sec, 2634020 t fired, .

Time elapsed: 960 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 200/405 7/32 PermAdmissibility-PT-50-CTLFireability-04 1211349 m, 5444 m/sec, 2694361 t fired, .

Time elapsed: 965 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 205/405 8/32 PermAdmissibility-PT-50-CTLFireability-04 1240940 m, 5918 m/sec, 2760169 t fired, .

Time elapsed: 970 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 210/405 8/32 PermAdmissibility-PT-50-CTLFireability-04 1270507 m, 5913 m/sec, 2825988 t fired, .

Time elapsed: 975 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 215/405 8/32 PermAdmissibility-PT-50-CTLFireability-04 1300063 m, 5911 m/sec, 2891621 t fired, .

Time elapsed: 980 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 220/405 8/32 PermAdmissibility-PT-50-CTLFireability-04 1329579 m, 5903 m/sec, 2957519 t fired, .

Time elapsed: 985 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 225/405 8/32 PermAdmissibility-PT-50-CTLFireability-04 1359129 m, 5910 m/sec, 3023423 t fired, .

Time elapsed: 990 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 230/405 9/32 PermAdmissibility-PT-50-CTLFireability-04 1388626 m, 5899 m/sec, 3088925 t fired, .

Time elapsed: 995 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 235/405 9/32 PermAdmissibility-PT-50-CTLFireability-04 1418177 m, 5910 m/sec, 3154895 t fired, .

Time elapsed: 1000 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 240/405 9/32 PermAdmissibility-PT-50-CTLFireability-04 1447679 m, 5900 m/sec, 3220713 t fired, .

Time elapsed: 1005 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 245/405 9/32 PermAdmissibility-PT-50-CTLFireability-04 1477221 m, 5908 m/sec, 3286605 t fired, .

Time elapsed: 1010 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 250/405 9/32 PermAdmissibility-PT-50-CTLFireability-04 1506719 m, 5899 m/sec, 3352389 t fired, .

Time elapsed: 1015 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 255/405 9/32 PermAdmissibility-PT-50-CTLFireability-04 1536243 m, 5904 m/sec, 3418237 t fired, .

Time elapsed: 1020 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 260/405 10/32 PermAdmissibility-PT-50-CTLFireability-04 1565771 m, 5905 m/sec, 3483989 t fired, .

Time elapsed: 1025 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 265/405 10/32 PermAdmissibility-PT-50-CTLFireability-04 1595303 m, 5906 m/sec, 3549740 t fired, .

Time elapsed: 1030 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 270/405 10/32 PermAdmissibility-PT-50-CTLFireability-04 1625050 m, 5949 m/sec, 3615964 t fired, .

Time elapsed: 1035 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 275/405 10/32 PermAdmissibility-PT-50-CTLFireability-04 1651047 m, 5199 m/sec, 3673032 t fired, .

Time elapsed: 1040 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 280/405 10/32 PermAdmissibility-PT-50-CTLFireability-04 1675326 m, 4855 m/sec, 3726949 t fired, .

Time elapsed: 1045 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 285/405 10/32 PermAdmissibility-PT-50-CTLFireability-04 1699515 m, 4837 m/sec, 3780831 t fired, .

Time elapsed: 1050 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 290/405 10/32 PermAdmissibility-PT-50-CTLFireability-04 1723683 m, 4833 m/sec, 3834720 t fired, .

Time elapsed: 1055 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 295/405 11/32 PermAdmissibility-PT-50-CTLFireability-04 1746819 m, 4627 m/sec, 3886315 t fired, .

Time elapsed: 1060 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 300/405 11/32 PermAdmissibility-PT-50-CTLFireability-04 1770945 m, 4825 m/sec, 3939973 t fired, .

Time elapsed: 1065 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 305/405 11/32 PermAdmissibility-PT-50-CTLFireability-04 1795055 m, 4822 m/sec, 3994078 t fired, .

Time elapsed: 1070 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 310/405 11/32 PermAdmissibility-PT-50-CTLFireability-04 1817191 m, 4427 m/sec, 4043650 t fired, .

Time elapsed: 1075 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 315/405 11/32 PermAdmissibility-PT-50-CTLFireability-04 1838225 m, 4206 m/sec, 4090379 t fired, .

Time elapsed: 1080 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 320/405 11/32 PermAdmissibility-PT-50-CTLFireability-04 1859314 m, 4217 m/sec, 4137918 t fired, .

Time elapsed: 1085 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 325/405 11/32 PermAdmissibility-PT-50-CTLFireability-04 1879382 m, 4013 m/sec, 4182440 t fired, .

Time elapsed: 1090 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 330/405 12/32 PermAdmissibility-PT-50-CTLFireability-04 1903291 m, 4781 m/sec, 4236402 t fired, .

Time elapsed: 1095 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 335/405 12/32 PermAdmissibility-PT-50-CTLFireability-04 1927293 m, 4800 m/sec, 4289610 t fired, .

Time elapsed: 1100 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 340/405 12/32 PermAdmissibility-PT-50-CTLFireability-04 1951239 m, 4789 m/sec, 4343751 t fired, .

Time elapsed: 1105 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 345/405 12/32 PermAdmissibility-PT-50-CTLFireability-04 1975280 m, 4808 m/sec, 4397026 t fired, .

Time elapsed: 1110 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 350/405 12/32 PermAdmissibility-PT-50-CTLFireability-04 1999236 m, 4791 m/sec, 4451248 t fired, .

Time elapsed: 1115 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 355/405 12/32 PermAdmissibility-PT-50-CTLFireability-04 2020074 m, 4167 m/sec, 4497340 t fired, .

Time elapsed: 1120 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 360/405 12/32 PermAdmissibility-PT-50-CTLFireability-04 2042065 m, 4398 m/sec, 4547133 t fired, .

Time elapsed: 1125 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 365/405 12/32 PermAdmissibility-PT-50-CTLFireability-04 2065543 m, 4695 m/sec, 4599227 t fired, .

Time elapsed: 1130 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 370/405 13/32 PermAdmissibility-PT-50-CTLFireability-04 2086730 m, 4237 m/sec, 4647182 t fired, .

Time elapsed: 1135 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 375/405 13/32 PermAdmissibility-PT-50-CTLFireability-04 2108348 m, 4323 m/sec, 4695776 t fired, .

Time elapsed: 1140 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 380/405 13/32 PermAdmissibility-PT-50-CTLFireability-04 2130232 m, 4376 m/sec, 4744121 t fired, .

Time elapsed: 1145 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 385/405 13/32 PermAdmissibility-PT-50-CTLFireability-04 2154111 m, 4775 m/sec, 4798239 t fired, .

Time elapsed: 1150 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 390/405 13/32 PermAdmissibility-PT-50-CTLFireability-04 2178089 m, 4795 m/sec, 4851314 t fired, .

Time elapsed: 1155 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 395/405 13/32 PermAdmissibility-PT-50-CTLFireability-04 2201991 m, 4780 m/sec, 4905482 t fired, .

Time elapsed: 1160 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 400/405 13/32 PermAdmissibility-PT-50-CTLFireability-04 2225988 m, 4799 m/sec, 4958765 t fired, .

Time elapsed: 1165 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 405/405 14/32 PermAdmissibility-PT-50-CTLFireability-04 2249819 m, 4766 m/sec, 5012672 t fired, .

Time elapsed: 1170 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-04 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 1 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1175 secs. Pages in use: 85
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 PermAdmissibility-PT-50-CTLFireability-03
lola: time limit : 404 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 13 (type EXCL) for 12 PermAdmissibility-PT-50-CTLFireability-04
lola: time limit : 2425 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/404 6/32 PermAdmissibility-PT-50-CTLFireability-03 1189457 m, 237891 m/sec, 1783411 t fired, .
13 CTL EXCL 4/2425 1/5 PermAdmissibility-PT-50-CTLFireability-04 31612 m, -443641 m/sec, 69963 t fired, .

Time elapsed: 1180 secs. Pages in use: 85
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/404 12/32 PermAdmissibility-PT-50-CTLFireability-03 2423633 m, 246835 m/sec, 3729829 t fired, .
13 CTL EXCL 9/346 1/5 PermAdmissibility-PT-50-CTLFireability-04 69364 m, 7550 m/sec, 153846 t fired, .

Time elapsed: 1185 secs. Pages in use: 85
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/404 17/32 PermAdmissibility-PT-50-CTLFireability-03 3640753 m, 243424 m/sec, 5681643 t fired, .
13 CTL EXCL 14/346 1/5 PermAdmissibility-PT-50-CTLFireability-04 107113 m, 7549 m/sec, 237824 t fired, .

Time elapsed: 1190 secs. Pages in use: 85
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/404 23/32 PermAdmissibility-PT-50-CTLFireability-03 4827020 m, 237253 m/sec, 7596975 t fired, .
13 CTL EXCL 19/346 1/5 PermAdmissibility-PT-50-CTLFireability-04 144786 m, 7534 m/sec, 321667 t fired, .

Time elapsed: 1195 secs. Pages in use: 91
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/404 28/32 PermAdmissibility-PT-50-CTLFireability-03 6019378 m, 238471 m/sec, 9564239 t fired, .
13 CTL EXCL 24/346 2/5 PermAdmissibility-PT-50-CTLFireability-04 182239 m, 7490 m/sec, 405079 t fired, .

Time elapsed: 1200 secs. Pages in use: 97
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 29/346 2/5 PermAdmissibility-PT-50-CTLFireability-04 212263 m, 6004 m/sec, 471221 t fired, .

Time elapsed: 1205 secs. Pages in use: 101
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 34/404 2/5 PermAdmissibility-PT-50-CTLFireability-04 239671 m, 5481 m/sec, 531866 t fired, .

Time elapsed: 1210 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 39/404 2/5 PermAdmissibility-PT-50-CTLFireability-04 265772 m, 5220 m/sec, 589840 t fired, .

Time elapsed: 1215 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 44/404 2/5 PermAdmissibility-PT-50-CTLFireability-04 291544 m, 5154 m/sec, 647129 t fired, .

Time elapsed: 1220 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 49/404 2/5 PermAdmissibility-PT-50-CTLFireability-04 321043 m, 5899 m/sec, 712770 t fired, .

Time elapsed: 1225 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 54/404 3/5 PermAdmissibility-PT-50-CTLFireability-04 350506 m, 5892 m/sec, 778416 t fired, .

Time elapsed: 1230 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 59/404 3/5 PermAdmissibility-PT-50-CTLFireability-04 379931 m, 5885 m/sec, 843986 t fired, .

Time elapsed: 1235 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 64/404 3/5 PermAdmissibility-PT-50-CTLFireability-04 409382 m, 5890 m/sec, 909390 t fired, .

Time elapsed: 1240 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 69/404 3/5 PermAdmissibility-PT-50-CTLFireability-04 438834 m, 5890 m/sec, 975185 t fired, .

Time elapsed: 1245 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 74/404 3/5 PermAdmissibility-PT-50-CTLFireability-04 468272 m, 5887 m/sec, 1040810 t fired, .

Time elapsed: 1250 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 79/404 3/5 PermAdmissibility-PT-50-CTLFireability-04 497726 m, 5890 m/sec, 1106479 t fired, .

Time elapsed: 1255 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 84/404 4/5 PermAdmissibility-PT-50-CTLFireability-04 527176 m, 5890 m/sec, 1172152 t fired, .

Time elapsed: 1260 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 89/404 4/5 PermAdmissibility-PT-50-CTLFireability-04 553875 m, 5339 m/sec, 1231693 t fired, .

Time elapsed: 1265 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 94/404 4/5 PermAdmissibility-PT-50-CTLFireability-04 580536 m, 5332 m/sec, 1291132 t fired, .

Time elapsed: 1270 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 99/404 4/5 PermAdmissibility-PT-50-CTLFireability-04 609752 m, 5843 m/sec, 1356226 t fired, .

Time elapsed: 1275 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 104/404 4/5 PermAdmissibility-PT-50-CTLFireability-04 636630 m, 5375 m/sec, 1416172 t fired, .

Time elapsed: 1280 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 109/404 4/5 PermAdmissibility-PT-50-CTLFireability-04 665757 m, 5825 m/sec, 1481036 t fired, .

Time elapsed: 1285 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 114/404 5/5 PermAdmissibility-PT-50-CTLFireability-04 695323 m, 5913 m/sec, 1546202 t fired, .

Time elapsed: 1290 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 119/404 5/5 PermAdmissibility-PT-50-CTLFireability-04 725101 m, 5955 m/sec, 1612235 t fired, .

Time elapsed: 1295 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 124/404 5/5 PermAdmissibility-PT-50-CTLFireability-04 754798 m, 5939 m/sec, 1678244 t fired, .

Time elapsed: 1300 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 129/404 5/5 PermAdmissibility-PT-50-CTLFireability-04 784495 m, 5939 m/sec, 1744252 t fired, .

Time elapsed: 1305 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 134/404 5/5 PermAdmissibility-PT-50-CTLFireability-04 814130 m, 5927 m/sec, 1810124 t fired, .

Time elapsed: 1310 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 139/404 5/5 PermAdmissibility-PT-50-CTLFireability-04 843797 m, 5933 m/sec, 1876290 t fired, .

Time elapsed: 1315 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1320 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 PermAdmissibility-PT-50-CTLFireability-01
lola: time limit : 456 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/456 2/32 PermAdmissibility-PT-50-CTLFireability-01 339664 m, 67932 m/sec, 2884826 t fired, .

Time elapsed: 1325 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/456 4/32 PermAdmissibility-PT-50-CTLFireability-01 675207 m, 67108 m/sec, 6054162 t fired, .

Time elapsed: 1330 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/456 6/32 PermAdmissibility-PT-50-CTLFireability-01 1006392 m, 66237 m/sec, 9204294 t fired, .

Time elapsed: 1335 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/456 8/32 PermAdmissibility-PT-50-CTLFireability-01 1334664 m, 65654 m/sec, 12340240 t fired, .

Time elapsed: 1340 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 26/456 10/32 PermAdmissibility-PT-50-CTLFireability-01 1656941 m, 64455 m/sec, 15449591 t fired, .

Time elapsed: 1346 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 31/456 12/32 PermAdmissibility-PT-50-CTLFireability-01 1978063 m, 64224 m/sec, 18551128 t fired, .

Time elapsed: 1351 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 36/456 14/32 PermAdmissibility-PT-50-CTLFireability-01 2297521 m, 63891 m/sec, 21639194 t fired, .

Time elapsed: 1356 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 41/456 16/32 PermAdmissibility-PT-50-CTLFireability-01 2614101 m, 63316 m/sec, 24715333 t fired, .

Time elapsed: 1361 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 46/456 18/32 PermAdmissibility-PT-50-CTLFireability-01 2931215 m, 63422 m/sec, 27813638 t fired, .

Time elapsed: 1366 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 51/456 19/32 PermAdmissibility-PT-50-CTLFireability-01 3197863 m, 53329 m/sec, 31488417 t fired, .

Time elapsed: 1371 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 56/456 20/32 PermAdmissibility-PT-50-CTLFireability-01 3434867 m, 47400 m/sec, 35236832 t fired, .

Time elapsed: 1376 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 61/456 22/32 PermAdmissibility-PT-50-CTLFireability-01 3665154 m, 46057 m/sec, 38953552 t fired, .

Time elapsed: 1381 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 66/456 23/32 PermAdmissibility-PT-50-CTLFireability-01 3892477 m, 45464 m/sec, 42638824 t fired, .

Time elapsed: 1386 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 71/456 24/32 PermAdmissibility-PT-50-CTLFireability-01 4115904 m, 44685 m/sec, 46251081 t fired, .

Time elapsed: 1391 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 76/456 26/32 PermAdmissibility-PT-50-CTLFireability-01 4345935 m, 46006 m/sec, 49912060 t fired, .

Time elapsed: 1396 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 81/456 27/32 PermAdmissibility-PT-50-CTLFireability-01 4560738 m, 42960 m/sec, 53612524 t fired, .

Time elapsed: 1401 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 86/456 28/32 PermAdmissibility-PT-50-CTLFireability-01 4785777 m, 45007 m/sec, 57202466 t fired, .

Time elapsed: 1406 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 91/456 29/32 PermAdmissibility-PT-50-CTLFireability-01 4997368 m, 42318 m/sec, 60882014 t fired, .

Time elapsed: 1411 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 96/456 31/32 PermAdmissibility-PT-50-CTLFireability-01 5214971 m, 43520 m/sec, 64441096 t fired, .

Time elapsed: 1416 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 101/456 32/32 PermAdmissibility-PT-50-CTLFireability-01 5432070 m, 43419 m/sec, 68085744 t fired, .

Time elapsed: 1421 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1426 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 PermAdmissibility-PT-50-CTLFireability-00
lola: time limit : 543 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/543 6/32 PermAdmissibility-PT-50-CTLFireability-00 1078150 m, 215630 m/sec, 3147881 t fired, .

Time elapsed: 1431 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/543 11/32 PermAdmissibility-PT-50-CTLFireability-00 2178354 m, 220040 m/sec, 6505549 t fired, .

Time elapsed: 1436 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/543 16/32 PermAdmissibility-PT-50-CTLFireability-00 3253254 m, 214980 m/sec, 9810631 t fired, .

Time elapsed: 1441 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/543 21/32 PermAdmissibility-PT-50-CTLFireability-00 4323865 m, 214122 m/sec, 13093796 t fired, .

Time elapsed: 1446 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/543 26/32 PermAdmissibility-PT-50-CTLFireability-00 5350560 m, 205339 m/sec, 16336675 t fired, .

Time elapsed: 1451 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/543 31/32 PermAdmissibility-PT-50-CTLFireability-00 6400039 m, 209895 m/sec, 19569569 t fired, .

Time elapsed: 1456 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 1 0 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1461 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 87 (type EXCL) for 21 PermAdmissibility-PT-50-CTLFireability-07
lola: time limit : 713 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 5/713 3/32 PermAdmissibility-PT-50-CTLFireability-07 482064 m, 96412 m/sec, 3836974 t fired, .

Time elapsed: 1466 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 10/713 5/32 PermAdmissibility-PT-50-CTLFireability-07 875718 m, 78730 m/sec, 8161472 t fired, .

Time elapsed: 1471 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 15/713 7/32 PermAdmissibility-PT-50-CTLFireability-07 1163302 m, 57516 m/sec, 12651628 t fired, .

Time elapsed: 1476 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 20/713 8/32 PermAdmissibility-PT-50-CTLFireability-07 1429164 m, 53172 m/sec, 17089432 t fired, .

Time elapsed: 1481 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 25/713 10/32 PermAdmissibility-PT-50-CTLFireability-07 1705926 m, 55352 m/sec, 21482389 t fired, .

Time elapsed: 1486 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 30/713 11/32 PermAdmissibility-PT-50-CTLFireability-07 1963507 m, 51516 m/sec, 25834293 t fired, .

Time elapsed: 1491 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 35/713 13/32 PermAdmissibility-PT-50-CTLFireability-07 2223354 m, 51969 m/sec, 30186576 t fired, .

Time elapsed: 1496 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 40/713 14/32 PermAdmissibility-PT-50-CTLFireability-07 2483878 m, 52104 m/sec, 34517119 t fired, .

Time elapsed: 1501 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 45/713 15/32 PermAdmissibility-PT-50-CTLFireability-07 2744633 m, 52151 m/sec, 38817969 t fired, .

Time elapsed: 1506 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 50/713 17/32 PermAdmissibility-PT-50-CTLFireability-07 3041821 m, 59437 m/sec, 43244683 t fired, .

Time elapsed: 1511 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 55/713 18/32 PermAdmissibility-PT-50-CTLFireability-07 3292112 m, 50058 m/sec, 47663583 t fired, .

Time elapsed: 1516 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 60/713 20/32 PermAdmissibility-PT-50-CTLFireability-07 3539964 m, 49570 m/sec, 52055653 t fired, .

Time elapsed: 1521 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 65/713 21/32 PermAdmissibility-PT-50-CTLFireability-07 3778758 m, 47758 m/sec, 56419026 t fired, .

Time elapsed: 1526 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 70/713 22/32 PermAdmissibility-PT-50-CTLFireability-07 4008570 m, 45962 m/sec, 60683083 t fired, .

Time elapsed: 1531 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 75/713 23/32 PermAdmissibility-PT-50-CTLFireability-07 4227683 m, 43822 m/sec, 64820601 t fired, .

Time elapsed: 1536 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 80/713 25/32 PermAdmissibility-PT-50-CTLFireability-07 4455417 m, 45546 m/sec, 69087128 t fired, .

Time elapsed: 1541 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 85/713 26/32 PermAdmissibility-PT-50-CTLFireability-07 4682696 m, 45455 m/sec, 73171012 t fired, .

Time elapsed: 1546 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 90/713 27/32 PermAdmissibility-PT-50-CTLFireability-07 4899766 m, 43414 m/sec, 77397499 t fired, .

Time elapsed: 1551 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 95/713 28/32 PermAdmissibility-PT-50-CTLFireability-07 5130077 m, 46062 m/sec, 81610116 t fired, .

Time elapsed: 1556 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 100/713 29/32 PermAdmissibility-PT-50-CTLFireability-07 5347918 m, 43568 m/sec, 85835445 t fired, .

Time elapsed: 1561 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 105/713 31/32 PermAdmissibility-PT-50-CTLFireability-07 5576096 m, 45635 m/sec, 90045123 t fired, .

Time elapsed: 1566 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 1 0 11 0 0 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
87 AGEF EXCL 110/713 32/32 PermAdmissibility-PT-50-CTLFireability-07 5793122 m, 43405 m/sec, 94247716 t fired, .

Time elapsed: 1571 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 87 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1576 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 48 (type EXCL) for 47 PermAdmissibility-PT-50-CTLFireability-09
lola: time limit : 1012 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 5/1012 1/32 PermAdmissibility-PT-50-CTLFireability-09 116240 m, 23248 m/sec, 859441 t fired, .

Time elapsed: 1581 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 10/1012 2/32 PermAdmissibility-PT-50-CTLFireability-09 235593 m, 23870 m/sec, 1818137 t fired, .

Time elapsed: 1586 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 15/1012 2/32 PermAdmissibility-PT-50-CTLFireability-09 353932 m, 23667 m/sec, 2781017 t fired, .

Time elapsed: 1591 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 20/1012 3/32 PermAdmissibility-PT-50-CTLFireability-09 471250 m, 23463 m/sec, 3746097 t fired, .

Time elapsed: 1596 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 25/1012 4/32 PermAdmissibility-PT-50-CTLFireability-09 588314 m, 23412 m/sec, 4709665 t fired, .

Time elapsed: 1601 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 30/1012 4/32 PermAdmissibility-PT-50-CTLFireability-09 705395 m, 23416 m/sec, 5675553 t fired, .

Time elapsed: 1606 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 35/1012 5/32 PermAdmissibility-PT-50-CTLFireability-09 787593 m, 16439 m/sec, 6780308 t fired, .

Time elapsed: 1611 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 40/1012 5/32 PermAdmissibility-PT-50-CTLFireability-09 861751 m, 14831 m/sec, 7922447 t fired, .

Time elapsed: 1616 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 45/1012 5/32 PermAdmissibility-PT-50-CTLFireability-09 934266 m, 14503 m/sec, 9076926 t fired, .

Time elapsed: 1621 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 50/1012 6/32 PermAdmissibility-PT-50-CTLFireability-09 1005820 m, 14310 m/sec, 10234080 t fired, .

Time elapsed: 1626 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 55/1012 6/32 PermAdmissibility-PT-50-CTLFireability-09 1076607 m, 14157 m/sec, 11332473 t fired, .

Time elapsed: 1631 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 60/1012 6/32 PermAdmissibility-PT-50-CTLFireability-09 1149263 m, 14531 m/sec, 12488574 t fired, .

Time elapsed: 1636 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 65/1012 7/32 PermAdmissibility-PT-50-CTLFireability-09 1218679 m, 13883 m/sec, 13635204 t fired, .

Time elapsed: 1641 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 70/1012 7/32 PermAdmissibility-PT-50-CTLFireability-09 1281601 m, 12584 m/sec, 14684788 t fired, .

Time elapsed: 1646 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 75/1012 7/32 PermAdmissibility-PT-50-CTLFireability-09 1351543 m, 13988 m/sec, 15777123 t fired, .

Time elapsed: 1651 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 80/1012 8/32 PermAdmissibility-PT-50-CTLFireability-09 1419321 m, 13555 m/sec, 16935530 t fired, .

Time elapsed: 1656 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 85/1012 8/32 PermAdmissibility-PT-50-CTLFireability-09 1496535 m, 15442 m/sec, 18078847 t fired, .

Time elapsed: 1661 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 90/1012 9/32 PermAdmissibility-PT-50-CTLFireability-09 1559095 m, 12512 m/sec, 19242271 t fired, .

Time elapsed: 1666 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 95/1012 9/32 PermAdmissibility-PT-50-CTLFireability-09 1629218 m, 14024 m/sec, 20394214 t fired, .

Time elapsed: 1671 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 100/1012 9/32 PermAdmissibility-PT-50-CTLFireability-09 1708180 m, 15792 m/sec, 21529414 t fired, .

Time elapsed: 1676 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 105/1012 10/32 PermAdmissibility-PT-50-CTLFireability-09 1768471 m, 12058 m/sec, 22698316 t fired, .

Time elapsed: 1681 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 110/1012 10/32 PermAdmissibility-PT-50-CTLFireability-09 1839111 m, 14128 m/sec, 23839777 t fired, .

Time elapsed: 1686 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 115/1012 10/32 PermAdmissibility-PT-50-CTLFireability-09 1916105 m, 15398 m/sec, 24974333 t fired, .

Time elapsed: 1691 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 120/1012 11/32 PermAdmissibility-PT-50-CTLFireability-09 1978939 m, 12566 m/sec, 26133648 t fired, .

Time elapsed: 1696 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 125/1012 11/32 PermAdmissibility-PT-50-CTLFireability-09 2047171 m, 13646 m/sec, 27284623 t fired, .

Time elapsed: 1701 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 130/1012 11/32 PermAdmissibility-PT-50-CTLFireability-09 2114774 m, 13520 m/sec, 28442970 t fired, .

Time elapsed: 1706 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 135/1012 12/32 PermAdmissibility-PT-50-CTLFireability-09 2191860 m, 15417 m/sec, 29574339 t fired, .

Time elapsed: 1711 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 140/1012 12/32 PermAdmissibility-PT-50-CTLFireability-09 2253955 m, 12419 m/sec, 30732196 t fired, .

Time elapsed: 1716 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 145/1012 12/32 PermAdmissibility-PT-50-CTLFireability-09 2322999 m, 13808 m/sec, 31885280 t fired, .

Time elapsed: 1721 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 150/1012 13/32 PermAdmissibility-PT-50-CTLFireability-09 2396846 m, 14769 m/sec, 33000709 t fired, .

Time elapsed: 1726 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 155/1012 13/32 PermAdmissibility-PT-50-CTLFireability-09 2461427 m, 12916 m/sec, 34078617 t fired, .

Time elapsed: 1731 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 160/1012 13/32 PermAdmissibility-PT-50-CTLFireability-09 2524786 m, 12671 m/sec, 35234079 t fired, .

Time elapsed: 1736 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 165/1012 14/32 PermAdmissibility-PT-50-CTLFireability-09 2593902 m, 13823 m/sec, 36385705 t fired, .

Time elapsed: 1741 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 170/1012 14/32 PermAdmissibility-PT-50-CTLFireability-09 2666736 m, 14566 m/sec, 37495481 t fired, .

Time elapsed: 1746 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 175/1012 14/32 PermAdmissibility-PT-50-CTLFireability-09 2731576 m, 12968 m/sec, 38562192 t fired, .

Time elapsed: 1751 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 180/1012 15/32 PermAdmissibility-PT-50-CTLFireability-09 2790228 m, 11730 m/sec, 39606363 t fired, .

Time elapsed: 1756 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 185/1012 15/32 PermAdmissibility-PT-50-CTLFireability-09 2873214 m, 16597 m/sec, 40722494 t fired, .

Time elapsed: 1761 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 190/1012 15/32 PermAdmissibility-PT-50-CTLFireability-09 2942336 m, 13824 m/sec, 41883387 t fired, .

Time elapsed: 1766 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 195/1012 16/32 PermAdmissibility-PT-50-CTLFireability-09 3024410 m, 16414 m/sec, 42986069 t fired, .

Time elapsed: 1771 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 200/1012 16/32 PermAdmissibility-PT-50-CTLFireability-09 3093641 m, 13846 m/sec, 44088640 t fired, .

Time elapsed: 1776 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 205/1012 16/32 PermAdmissibility-PT-50-CTLFireability-09 3158627 m, 12997 m/sec, 45233352 t fired, .

Time elapsed: 1781 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 210/1012 17/32 PermAdmissibility-PT-50-CTLFireability-09 3227214 m, 13717 m/sec, 46398311 t fired, .

Time elapsed: 1786 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 215/1012 17/32 PermAdmissibility-PT-50-CTLFireability-09 3289163 m, 12389 m/sec, 47604104 t fired, .

Time elapsed: 1791 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 220/1012 17/32 PermAdmissibility-PT-50-CTLFireability-09 3356920 m, 13551 m/sec, 48774831 t fired, .

Time elapsed: 1796 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 225/1012 18/32 PermAdmissibility-PT-50-CTLFireability-09 3423444 m, 13304 m/sec, 49954420 t fired, .

Time elapsed: 1801 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 230/1012 18/32 PermAdmissibility-PT-50-CTLFireability-09 3485596 m, 12430 m/sec, 51160700 t fired, .

Time elapsed: 1806 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 235/1012 18/32 PermAdmissibility-PT-50-CTLFireability-09 3551326 m, 13146 m/sec, 52278912 t fired, .

Time elapsed: 1811 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 240/1012 19/32 PermAdmissibility-PT-50-CTLFireability-09 3616381 m, 13011 m/sec, 53462610 t fired, .

Time elapsed: 1816 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 245/1012 19/32 PermAdmissibility-PT-50-CTLFireability-09 3679380 m, 12599 m/sec, 54660104 t fired, .

Time elapsed: 1821 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 250/1012 19/32 PermAdmissibility-PT-50-CTLFireability-09 3747744 m, 13672 m/sec, 55836638 t fired, .

Time elapsed: 1826 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 255/1012 20/32 PermAdmissibility-PT-50-CTLFireability-09 3809220 m, 12295 m/sec, 57021720 t fired, .

Time elapsed: 1831 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 260/1012 20/32 PermAdmissibility-PT-50-CTLFireability-09 3872754 m, 12706 m/sec, 58201669 t fired, .

Time elapsed: 1836 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 265/1012 20/32 PermAdmissibility-PT-50-CTLFireability-09 3934762 m, 12401 m/sec, 59384445 t fired, .

Time elapsed: 1841 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 270/1012 21/32 PermAdmissibility-PT-50-CTLFireability-09 3993745 m, 11796 m/sec, 60518417 t fired, .

Time elapsed: 1846 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 275/1012 21/32 PermAdmissibility-PT-50-CTLFireability-09 4063460 m, 13943 m/sec, 61673893 t fired, .

Time elapsed: 1851 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 280/1012 21/32 PermAdmissibility-PT-50-CTLFireability-09 4122768 m, 11861 m/sec, 62875577 t fired, .

Time elapsed: 1856 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 285/1012 22/32 PermAdmissibility-PT-50-CTLFireability-09 4188398 m, 13126 m/sec, 64058002 t fired, .

Time elapsed: 1861 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 290/1012 22/32 PermAdmissibility-PT-50-CTLFireability-09 4250207 m, 12361 m/sec, 65257664 t fired, .

Time elapsed: 1866 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 295/1012 22/32 PermAdmissibility-PT-50-CTLFireability-09 4316020 m, 13162 m/sec, 66444674 t fired, .

Time elapsed: 1871 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 300/1012 23/32 PermAdmissibility-PT-50-CTLFireability-09 4382552 m, 13306 m/sec, 67608459 t fired, .

Time elapsed: 1876 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 305/1012 23/32 PermAdmissibility-PT-50-CTLFireability-09 4441684 m, 11826 m/sec, 68809090 t fired, .

Time elapsed: 1881 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 310/1012 23/32 PermAdmissibility-PT-50-CTLFireability-09 4505285 m, 12720 m/sec, 69993082 t fired, .

Time elapsed: 1886 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 315/1012 23/32 PermAdmissibility-PT-50-CTLFireability-09 4568151 m, 12573 m/sec, 71189075 t fired, .

Time elapsed: 1891 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 320/1012 24/32 PermAdmissibility-PT-50-CTLFireability-09 4631176 m, 12605 m/sec, 72381807 t fired, .

Time elapsed: 1896 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 325/1012 24/32 PermAdmissibility-PT-50-CTLFireability-09 4700970 m, 13958 m/sec, 73545142 t fired, .

Time elapsed: 1901 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 330/1012 24/32 PermAdmissibility-PT-50-CTLFireability-09 4761572 m, 12120 m/sec, 74729902 t fired, .

Time elapsed: 1906 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 335/1012 25/32 PermAdmissibility-PT-50-CTLFireability-09 4820309 m, 11747 m/sec, 75927400 t fired, .

Time elapsed: 1911 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 340/1012 25/32 PermAdmissibility-PT-50-CTLFireability-09 4884089 m, 12756 m/sec, 77105762 t fired, .

Time elapsed: 1916 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 345/1012 25/32 PermAdmissibility-PT-50-CTLFireability-09 4946303 m, 12442 m/sec, 78291328 t fired, .

Time elapsed: 1921 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 350/1012 26/32 PermAdmissibility-PT-50-CTLFireability-09 5007913 m, 12322 m/sec, 79480054 t fired, .

Time elapsed: 1926 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 355/1012 26/32 PermAdmissibility-PT-50-CTLFireability-09 5080561 m, 14529 m/sec, 80632532 t fired, .

Time elapsed: 1931 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 360/1012 26/32 PermAdmissibility-PT-50-CTLFireability-09 5140172 m, 11922 m/sec, 81810921 t fired, .

Time elapsed: 1936 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 365/1012 27/32 PermAdmissibility-PT-50-CTLFireability-09 5198600 m, 11685 m/sec, 83008301 t fired, .

Time elapsed: 1941 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 370/1012 27/32 PermAdmissibility-PT-50-CTLFireability-09 5260563 m, 12392 m/sec, 84192994 t fired, .

Time elapsed: 1946 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 375/1012 27/32 PermAdmissibility-PT-50-CTLFireability-09 5323610 m, 12609 m/sec, 85379569 t fired, .

Time elapsed: 1951 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 380/1012 28/32 PermAdmissibility-PT-50-CTLFireability-09 5385013 m, 12280 m/sec, 86566154 t fired, .

Time elapsed: 1956 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 385/1012 28/32 PermAdmissibility-PT-50-CTLFireability-09 5446458 m, 12289 m/sec, 87756322 t fired, .

Time elapsed: 1961 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 390/1012 28/32 PermAdmissibility-PT-50-CTLFireability-09 5517199 m, 14148 m/sec, 88906367 t fired, .

Time elapsed: 1966 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 395/1012 28/32 PermAdmissibility-PT-50-CTLFireability-09 5577999 m, 12160 m/sec, 90085048 t fired, .

Time elapsed: 1971 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 400/1012 29/32 PermAdmissibility-PT-50-CTLFireability-09 5636061 m, 11612 m/sec, 91279593 t fired, .

Time elapsed: 1976 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 405/1012 29/32 PermAdmissibility-PT-50-CTLFireability-09 5698540 m, 12495 m/sec, 92462534 t fired, .

Time elapsed: 1981 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 410/1012 29/32 PermAdmissibility-PT-50-CTLFireability-09 5760954 m, 12482 m/sec, 93649663 t fired, .

Time elapsed: 1986 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 415/1012 30/32 PermAdmissibility-PT-50-CTLFireability-09 5823459 m, 12501 m/sec, 94836161 t fired, .

Time elapsed: 1991 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 420/1012 30/32 PermAdmissibility-PT-50-CTLFireability-09 5882270 m, 11762 m/sec, 95971733 t fired, .

Time elapsed: 1996 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 425/1012 30/32 PermAdmissibility-PT-50-CTLFireability-09 5955132 m, 14572 m/sec, 97120385 t fired, .

Time elapsed: 2001 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 430/1012 31/32 PermAdmissibility-PT-50-CTLFireability-09 6014106 m, 11794 m/sec, 98294608 t fired, .

Time elapsed: 2006 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 435/1012 31/32 PermAdmissibility-PT-50-CTLFireability-09 6072487 m, 11676 m/sec, 99485177 t fired, .

Time elapsed: 2011 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 440/1012 31/32 PermAdmissibility-PT-50-CTLFireability-09 6129865 m, 11475 m/sec, 100681817 t fired, .

Time elapsed: 2016 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 445/1012 32/32 PermAdmissibility-PT-50-CTLFireability-09 6194748 m, 12976 m/sec, 101856818 t fired, .

Time elapsed: 2021 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 450/1012 32/32 PermAdmissibility-PT-50-CTLFireability-09 6256766 m, 12403 m/sec, 103041902 t fired, .

Time elapsed: 2026 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 455/1012 32/32 PermAdmissibility-PT-50-CTLFireability-09 6318598 m, 12366 m/sec, 104231747 t fired, .

Time elapsed: 2031 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EU EXCL 460/1012 32/32 PermAdmissibility-PT-50-CTLFireability-09 6380002 m, 12280 m/sec, 105412980 t fired, .

Time elapsed: 2036 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 48 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2041 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 PermAdmissibility-PT-50-CTLFireability-02
lola: time limit : 1559 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/1559 3/32 PermAdmissibility-PT-50-CTLFireability-02 436306 m, 87261 m/sec, 3459759 t fired, .

Time elapsed: 2046 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/1559 5/32 PermAdmissibility-PT-50-CTLFireability-02 822100 m, 77158 m/sec, 7288112 t fired, .

Time elapsed: 2051 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/1559 7/32 PermAdmissibility-PT-50-CTLFireability-02 1084036 m, 52387 m/sec, 11462197 t fired, .

Time elapsed: 2056 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/1559 8/32 PermAdmissibility-PT-50-CTLFireability-02 1339296 m, 51052 m/sec, 15540369 t fired, .

Time elapsed: 2061 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/1559 10/32 PermAdmissibility-PT-50-CTLFireability-02 1585754 m, 49291 m/sec, 19658692 t fired, .

Time elapsed: 2066 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/1559 11/32 PermAdmissibility-PT-50-CTLFireability-02 1830986 m, 49046 m/sec, 23722381 t fired, .

Time elapsed: 2071 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/1559 13/32 PermAdmissibility-PT-50-CTLFireability-02 2075382 m, 48879 m/sec, 27760473 t fired, .

Time elapsed: 2076 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/1559 14/32 PermAdmissibility-PT-50-CTLFireability-02 2316304 m, 48184 m/sec, 31772604 t fired, .

Time elapsed: 2081 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/1559 15/32 PermAdmissibility-PT-50-CTLFireability-02 2557049 m, 48149 m/sec, 35775071 t fired, .

Time elapsed: 2086 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/1559 17/32 PermAdmissibility-PT-50-CTLFireability-02 2804022 m, 49394 m/sec, 39722607 t fired, .

Time elapsed: 2091 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 55/1559 18/32 PermAdmissibility-PT-50-CTLFireability-02 3077271 m, 54649 m/sec, 43848855 t fired, .

Time elapsed: 2096 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 60/1559 20/32 PermAdmissibility-PT-50-CTLFireability-02 3311825 m, 46910 m/sec, 47941759 t fired, .

Time elapsed: 2101 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 65/1559 21/32 PermAdmissibility-PT-50-CTLFireability-02 3538671 m, 45369 m/sec, 52033181 t fired, .

Time elapsed: 2106 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 70/1559 22/32 PermAdmissibility-PT-50-CTLFireability-02 3759557 m, 44177 m/sec, 56090185 t fired, .

Time elapsed: 2111 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 75/1559 24/32 PermAdmissibility-PT-50-CTLFireability-02 3972519 m, 42592 m/sec, 60089760 t fired, .

Time elapsed: 2116 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 80/1559 25/32 PermAdmissibility-PT-50-CTLFireability-02 4189342 m, 43364 m/sec, 64080717 t fired, .

Time elapsed: 2121 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 85/1559 26/32 PermAdmissibility-PT-50-CTLFireability-02 4407062 m, 43544 m/sec, 68103437 t fired, .

Time elapsed: 2126 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 90/1559 27/32 PermAdmissibility-PT-50-CTLFireability-02 4616180 m, 41823 m/sec, 72114467 t fired, .

Time elapsed: 2131 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 95/1559 28/32 PermAdmissibility-PT-50-CTLFireability-02 4825801 m, 41924 m/sec, 76046666 t fired, .

Time elapsed: 2136 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 100/1559 30/32 PermAdmissibility-PT-50-CTLFireability-02 5035379 m, 41915 m/sec, 80011351 t fired, .

Time elapsed: 2141 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 105/1559 31/32 PermAdmissibility-PT-50-CTLFireability-02 5245909 m, 42106 m/sec, 83921779 t fired, .

Time elapsed: 2146 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 110/1559 32/32 PermAdmissibility-PT-50-CTLFireability-02 5453661 m, 41550 m/sec, 87899626 t fired, .

Time elapsed: 2151 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AXAF 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CONJ 0 0 0 0 11 0 1 3
PermAdmissibility-PT-50-CTLFireability-09: EU 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2156 secs. Pages in use: 101
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-00: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-01: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-02: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-03: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-04: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-05: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-06: AXAF unknown AGGR
PermAdmissibility-PT-50-CTLFireability-07: CONJ unknown CONJ
PermAdmissibility-PT-50-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: EU unknown AGGR
PermAdmissibility-PT-50-CTLFireability-10: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-11: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-12: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-14: DISJ false DISJ
PermAdmissibility-PT-50-CTLFireability-15: CTL true CTL model checker


Time elapsed: 2156 secs. Pages in use: 101

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-50"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PermAdmissibility-PT-50, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r263-smll-167863538400546"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-50.tgz
mv PermAdmissibility-PT-50 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;