About the Execution of LoLa+red for PermAdmissibility-PT-02
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3381.640 | 509585.00 | 524900.00 | 1797.10 | F?FFFFT?TTFFTTF? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r263-smll-167863538300514.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PermAdmissibility-PT-02, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r263-smll-167863538300514
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 9.8K Feb 26 01:19 CTLCardinality.txt
-rw-r--r-- 1 mcc users 88K Feb 26 01:19 CTLCardinality.xml
-rw-r--r-- 1 mcc users 42K Feb 26 01:18 CTLFireability.txt
-rw-r--r-- 1 mcc users 227K Feb 26 01:18 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 16:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 33K Feb 25 16:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 20K Feb 25 16:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 82K Feb 25 16:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 01:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 152K Feb 26 01:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 56K Feb 26 01:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 275K Feb 26 01:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.4K Feb 25 16:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 336K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-00
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-01
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-02
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-03
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-04
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-05
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-06
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-07
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-08
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-09
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-10
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-11
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-12
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-13
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-14
FORMULA_NAME PermAdmissibility-PT-02-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678806055584
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PermAdmissibility-PT-02
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 15:00:58] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 15:00:58] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 15:00:58] [INFO ] Load time of PNML (sax parser for PT used): 136 ms
[2023-03-14 15:00:58] [INFO ] Transformed 168 places.
[2023-03-14 15:00:58] [INFO ] Transformed 592 transitions.
[2023-03-14 15:00:58] [INFO ] Parsed PT model containing 168 places and 592 transitions and 3456 arcs in 236 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 33 ms.
Support contains 104 out of 168 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 168/168 places, 592/592 transitions.
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 104 transition count 592
Applied a total of 64 rules in 178 ms. Remains 104 /168 variables (removed 64) and now considering 592/592 (removed 0) transitions.
// Phase 1: matrix 592 rows 104 cols
[2023-03-14 15:00:59] [INFO ] Computed 16 place invariants in 46 ms
[2023-03-14 15:00:59] [INFO ] Implicit Places using invariants in 279 ms returned []
[2023-03-14 15:00:59] [INFO ] Invariant cache hit.
[2023-03-14 15:00:59] [INFO ] Implicit Places using invariants and state equation in 384 ms returned []
Implicit Place search using SMT with State Equation took 705 ms to find 0 implicit places.
[2023-03-14 15:00:59] [INFO ] Invariant cache hit.
[2023-03-14 15:01:00] [INFO ] Dead Transitions using invariants and state equation in 475 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 104/168 places, 592/592 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1362 ms. Remains : 104/168 places, 592/592 transitions.
Support contains 104 out of 104 places after structural reductions.
[2023-03-14 15:01:00] [INFO ] Flatten gal took : 190 ms
[2023-03-14 15:01:01] [INFO ] Flatten gal took : 124 ms
[2023-03-14 15:01:01] [INFO ] Input system was already deterministic with 592 transitions.
Incomplete random walk after 10000 steps, including 214 resets, run finished after 825 ms. (steps per millisecond=12 ) properties (out of 75) seen :69
Incomplete Best-First random walk after 10001 steps, including 49 resets, run finished after 239 ms. (steps per millisecond=41 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 52 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 40 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 36 resets, run finished after 103 ms. (steps per millisecond=97 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 51 resets, run finished after 76 ms. (steps per millisecond=131 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 41 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 3) seen :1
Running SMT prover for 2 properties.
[2023-03-14 15:01:03] [INFO ] Invariant cache hit.
[2023-03-14 15:01:03] [INFO ] [Real]Absence check using 0 positive and 16 generalized place invariants in 21 ms returned sat
[2023-03-14 15:01:03] [INFO ] After 156ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-14 15:01:03] [INFO ] [Nat]Absence check using 0 positive and 16 generalized place invariants in 13 ms returned sat
[2023-03-14 15:01:05] [INFO ] After 1382ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA PermAdmissibility-PT-02-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PermAdmissibility-PT-02-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-14 15:01:05] [INFO ] Flatten gal took : 60 ms
[2023-03-14 15:01:05] [INFO ] Flatten gal took : 67 ms
[2023-03-14 15:01:05] [INFO ] Input system was already deterministic with 592 transitions.
Computed a total of 104 stabilizing places and 592 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 104 transition count 592
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 13 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 15:01:05] [INFO ] Flatten gal took : 32 ms
[2023-03-14 15:01:05] [INFO ] Flatten gal took : 33 ms
[2023-03-14 15:01:06] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Graph (complete) has 975 edges and 104 vertex of which 86 are kept as prefixes of interest. Removing 18 places using SCC suffix rule.6 ms
Discarding 18 places :
Also discarding 128 output transitions
Drop transitions removed 128 transitions
Applied a total of 1 rules in 37 ms. Remains 86 /104 variables (removed 18) and now considering 464/592 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 38 ms. Remains : 86/104 places, 464/592 transitions.
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 23 ms
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 26 ms
[2023-03-14 15:01:06] [INFO ] Input system was already deterministic with 464 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 78 transition count 344
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 78 transition count 344
Applied a total of 52 rules in 8 ms. Remains 78 /104 variables (removed 26) and now considering 344/592 (removed 248) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 78/104 places, 344/592 transitions.
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 18 ms
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 21 ms
[2023-03-14 15:01:06] [INFO ] Input system was already deterministic with 344 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 91 transition count 468
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 91 transition count 468
Applied a total of 26 rules in 11 ms. Remains 91 /104 variables (removed 13) and now considering 468/592 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 91/104 places, 468/592 transitions.
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 22 ms
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 25 ms
[2023-03-14 15:01:06] [INFO ] Input system was already deterministic with 468 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Applied a total of 0 rules in 32 ms. Remains 104 /104 variables (removed 0) and now considering 592/592 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 104/104 places, 592/592 transitions.
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 37 ms
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 34 ms
[2023-03-14 15:01:06] [INFO ] Input system was already deterministic with 592 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Graph (complete) has 975 edges and 104 vertex of which 68 are kept as prefixes of interest. Removing 36 places using SCC suffix rule.3 ms
Discarding 36 places :
Also discarding 256 output transitions
Drop transitions removed 256 transitions
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 15 place count 54 transition count 210
Iterating global reduction 0 with 14 rules applied. Total rules applied 29 place count 54 transition count 210
Applied a total of 29 rules in 16 ms. Remains 54 /104 variables (removed 50) and now considering 210/592 (removed 382) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 54/104 places, 210/592 transitions.
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 8 ms
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 10 ms
[2023-03-14 15:01:06] [INFO ] Input system was already deterministic with 210 transitions.
Finished random walk after 14 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=14 )
FORMULA PermAdmissibility-PT-02-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Graph (complete) has 975 edges and 104 vertex of which 50 are kept as prefixes of interest. Removing 54 places using SCC suffix rule.3 ms
Discarding 54 places :
Also discarding 384 output transitions
Drop transitions removed 384 transitions
Applied a total of 1 rules in 9 ms. Remains 50 /104 variables (removed 54) and now considering 208/592 (removed 384) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 50/104 places, 208/592 transitions.
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 8 ms
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 9 ms
[2023-03-14 15:01:06] [INFO ] Input system was already deterministic with 208 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 6 place count 98 transition count 504
Iterating global reduction 0 with 6 rules applied. Total rules applied 12 place count 98 transition count 504
Applied a total of 12 rules in 8 ms. Remains 98 /104 variables (removed 6) and now considering 504/592 (removed 88) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 98/104 places, 504/592 transitions.
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 22 ms
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 24 ms
[2023-03-14 15:01:06] [INFO ] Input system was already deterministic with 504 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 78 transition count 344
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 78 transition count 344
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 74 place count 56 transition count 114
Iterating global reduction 0 with 22 rules applied. Total rules applied 96 place count 56 transition count 114
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 99 place count 53 transition count 90
Iterating global reduction 0 with 3 rules applied. Total rules applied 102 place count 53 transition count 90
Applied a total of 102 rules in 17 ms. Remains 53 /104 variables (removed 51) and now considering 90/592 (removed 502) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 53/104 places, 90/592 transitions.
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 5 ms
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 5 ms
[2023-03-14 15:01:06] [INFO ] Input system was already deterministic with 90 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 18 places :
Symmetric choice reduction at 0 with 18 rule applications. Total rules 18 place count 86 transition count 384
Iterating global reduction 0 with 18 rules applied. Total rules applied 36 place count 86 transition count 384
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 49 place count 73 transition count 220
Iterating global reduction 0 with 13 rules applied. Total rules applied 62 place count 73 transition count 220
Applied a total of 62 rules in 9 ms. Remains 73 /104 variables (removed 31) and now considering 220/592 (removed 372) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 73/104 places, 220/592 transitions.
[2023-03-14 15:01:06] [INFO ] Flatten gal took : 10 ms
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 13 ms
[2023-03-14 15:01:07] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 22 place count 82 transition count 364
Iterating global reduction 0 with 22 rules applied. Total rules applied 44 place count 82 transition count 364
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 60 place count 66 transition count 176
Iterating global reduction 0 with 16 rules applied. Total rules applied 76 place count 66 transition count 176
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 78 place count 64 transition count 160
Iterating global reduction 0 with 2 rules applied. Total rules applied 80 place count 64 transition count 160
Applied a total of 80 rules in 23 ms. Remains 64 /104 variables (removed 40) and now considering 160/592 (removed 432) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 64/104 places, 160/592 transitions.
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 8 ms
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 8 ms
[2023-03-14 15:01:07] [INFO ] Input system was already deterministic with 160 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 18 places :
Symmetric choice reduction at 0 with 18 rule applications. Total rules 18 place count 86 transition count 388
Iterating global reduction 0 with 18 rules applied. Total rules applied 36 place count 86 transition count 388
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 46 place count 76 transition count 262
Iterating global reduction 0 with 10 rules applied. Total rules applied 56 place count 76 transition count 262
Applied a total of 56 rules in 8 ms. Remains 76 /104 variables (removed 28) and now considering 262/592 (removed 330) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 76/104 places, 262/592 transitions.
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 13 ms
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 14 ms
[2023-03-14 15:01:07] [INFO ] Input system was already deterministic with 262 transitions.
Starting structural reductions in LTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 26 place count 78 transition count 344
Iterating global reduction 0 with 26 rules applied. Total rules applied 52 place count 78 transition count 344
Discarding 18 places :
Symmetric choice reduction at 0 with 18 rule applications. Total rules 70 place count 60 transition count 146
Iterating global reduction 0 with 18 rules applied. Total rules applied 88 place count 60 transition count 146
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 89 place count 59 transition count 138
Iterating global reduction 0 with 1 rules applied. Total rules applied 90 place count 59 transition count 138
Applied a total of 90 rules in 8 ms. Remains 59 /104 variables (removed 45) and now considering 138/592 (removed 454) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 59/104 places, 138/592 transitions.
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 7 ms
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 8 ms
[2023-03-14 15:01:07] [INFO ] Input system was already deterministic with 138 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 104/104 places, 592/592 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 87 transition count 396
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 87 transition count 396
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 39 place count 82 transition count 322
Iterating global reduction 0 with 5 rules applied. Total rules applied 44 place count 82 transition count 322
Applied a total of 44 rules in 21 ms. Remains 82 /104 variables (removed 22) and now considering 322/592 (removed 270) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 82/104 places, 322/592 transitions.
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 14 ms
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 16 ms
[2023-03-14 15:01:07] [INFO ] Input system was already deterministic with 322 transitions.
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 47 ms
[2023-03-14 15:01:07] [INFO ] Flatten gal took : 42 ms
[2023-03-14 15:01:07] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 23 ms.
[2023-03-14 15:01:07] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 104 places, 592 transitions and 2944 arcs took 5 ms.
Total runtime 9068 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PermAdmissibility-PT-02
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability
FORMULA PermAdmissibility-PT-02-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-02-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678806565169
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 7 (type EXCL) for 6 PermAdmissibility-PT-02-CTLFireability-02
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for PermAdmissibility-PT-02-CTLFireability-02
lola: result : false
lola: markings : 19
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 32 (type EXCL) for 31 PermAdmissibility-PT-02-CTLFireability-11
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for PermAdmissibility-PT-02-CTLFireability-11
lola: result : false
lola: markings : 33
lola: fired transitions : 131
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 PermAdmissibility-PT-02-CTLFireability-05
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for PermAdmissibility-PT-02-CTLFireability-05
lola: result : false
lola: markings : 19
lola: fired transitions : 18
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 26 (type EXCL) for 25 PermAdmissibility-PT-02-CTLFireability-09
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for PermAdmissibility-PT-02-CTLFireability-09
lola: result : true
lola: markings : 12
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 23 (type EXCL) for 22 PermAdmissibility-PT-02-CTLFireability-08
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type FNDP) for 34 PermAdmissibility-PT-02-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type EQUN) for 34 PermAdmissibility-PT-02-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 54 (type SRCH) for 34 PermAdmissibility-PT-02-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 51 (type FNDP) for PermAdmissibility-PT-02-CTLFireability-13
lola: result : true
lola: fired transitions : 43
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 52 (type EQUN) for PermAdmissibility-PT-02-CTLFireability-13 (obsolete)
lola: CANCELED task # 54 (type SRCH) for PermAdmissibility-PT-02-CTLFireability-13 (obsolete)
sara: try reading problem file /home/mcc/execution/376/CTLFireability-52.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 52 (type EQUN) for PermAdmissibility-PT-02-CTLFireability-13
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-02-CTLFireability-02: CTL false CTL model checker
PermAdmissibility-PT-02-CTLFireability-05: CTL false CTL model checker
PermAdmissibility-PT-02-CTLFireability-09: CTL true CTL model checker
PermAdmissibility-PT-02-CTLFireability-11: CTL false CTL model checker
PermAdmissibility-PT-02-CTLFireability-13: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-02-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-02-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 4/399 4/32 PermAdmissibility-PT-02-CTLFireability-08 788940 m, 157788 m/sec, 2025235 t fired, .
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PermAdmissibility-PT-02-CTLFireability-02: CTL false CTL model checker
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PermAdmissibility-PT-02-CTLFireability-09: CTL true CTL model checker
PermAdmissibility-PT-02-CTLFireability-11: CTL false CTL model checker
PermAdmissibility-PT-02-CTLFireability-13: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-02-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-02-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 9/399 6/32 PermAdmissibility-PT-02-CTLFireability-08 1151953 m, 72602 m/sec, 4239376 t fired, .
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PermAdmissibility-PT-02-CTLFireability-02: CTL false CTL model checker
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PermAdmissibility-PT-02-CTLFireability-09: CTL true CTL model checker
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PermAdmissibility-PT-02-CTLFireability-13: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-02-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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PermAdmissibility-PT-02-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 14/399 8/32 PermAdmissibility-PT-02-CTLFireability-08 1516446 m, 72898 m/sec, 6505883 t fired, .
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PermAdmissibility-PT-02-CTLFireability-02: CTL false CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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PermAdmissibility-PT-02-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 19/399 9/32 PermAdmissibility-PT-02-CTLFireability-08 1854993 m, 67709 m/sec, 8729239 t fired, .
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PermAdmissibility-PT-02-CTLFireability-09: CTL true CTL model checker
PermAdmissibility-PT-02-CTLFireability-11: CTL false CTL model checker
PermAdmissibility-PT-02-CTLFireability-13: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-02-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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PermAdmissibility-PT-02-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 24/399 11/32 PermAdmissibility-PT-02-CTLFireability-08 2225400 m, 74081 m/sec, 11062906 t fired, .
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PermAdmissibility-PT-02-CTLFireability-11: CTL false CTL model checker
PermAdmissibility-PT-02-CTLFireability-13: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-02-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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PermAdmissibility-PT-02-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 29/399 13/32 PermAdmissibility-PT-02-CTLFireability-08 2605208 m, 75961 m/sec, 13374723 t fired, .
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PermAdmissibility-PT-02-CTLFireability-02: CTL false CTL model checker
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PermAdmissibility-PT-02-CTLFireability-09: CTL true CTL model checker
PermAdmissibility-PT-02-CTLFireability-11: CTL false CTL model checker
PermAdmissibility-PT-02-CTLFireability-13: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-02-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-02-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
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PermAdmissibility-PT-02-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-02-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 34/399 15/32 PermAdmissibility-PT-02-CTLFireability-08 2990843 m, 77127 m/sec, 15842477 t fired, .
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PermAdmissibility-PT-02-CTLFireability-09: CTL true CTL model checker
PermAdmissibility-PT-02-CTLFireability-11: CTL false CTL model checker
PermAdmissibility-PT-02-CTLFireability-13: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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PermAdmissibility-PT-02-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
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49 CTL EXCL 42/1142 14/32 PermAdmissibility-PT-02-CTLFireability-15 2979388 m, 76494 m/sec, 21775042 t fired, .
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49 CTL EXCL 47/1142 16/32 PermAdmissibility-PT-02-CTLFireability-15 3245637 m, 53249 m/sec, 24607881 t fired, .
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49 CTL EXCL 52/1142 17/32 PermAdmissibility-PT-02-CTLFireability-15 3489097 m, 48692 m/sec, 27337232 t fired, .
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49 CTL EXCL 57/1142 19/32 PermAdmissibility-PT-02-CTLFireability-15 3955219 m, 93224 m/sec, 29372566 t fired, .
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49 CTL EXCL 62/1142 20/32 PermAdmissibility-PT-02-CTLFireability-15 4222710 m, 53498 m/sec, 32276736 t fired, .
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49 CTL EXCL 67/1142 22/32 PermAdmissibility-PT-02-CTLFireability-15 4483644 m, 52186 m/sec, 35110361 t fired, .
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49 CTL EXCL 72/1142 23/32 PermAdmissibility-PT-02-CTLFireability-15 4736192 m, 50509 m/sec, 37911438 t fired, .
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49 CTL EXCL 87/1142 27/32 PermAdmissibility-PT-02-CTLFireability-15 5608041 m, 43323 m/sec, 45351960 t fired, .
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49 CTL EXCL 97/1142 31/32 PermAdmissibility-PT-02-CTLFireability-15 6387188 m, 68990 m/sec, 50069110 t fired, .
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4 CTL EXCL 105/3224 28/32 PermAdmissibility-PT-02-CTLFireability-01 5910277 m, 60132 m/sec, 44116352 t fired, .
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PermAdmissibility-PT-02-CTLFireability-00: CTL false CTL model checker
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4 CTL EXCL 110/3224 30/32 PermAdmissibility-PT-02-CTLFireability-01 6219608 m, 61866 m/sec, 46383895 t fired, .
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4 CTL EXCL 115/3224 31/32 PermAdmissibility-PT-02-CTLFireability-01 6514785 m, 59035 m/sec, 48780407 t fired, .
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FINAL RESULTS
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PermAdmissibility-PT-02-CTLFireability-00: CTL false CTL model checker
PermAdmissibility-PT-02-CTLFireability-01: CTL unknown AGGR
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PermAdmissibility-PT-02-CTLFireability-03: CONJ false CTL model checker
PermAdmissibility-PT-02-CTLFireability-05: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-02"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PermAdmissibility-PT-02, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r263-smll-167863538300514"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-02.tgz
mv PermAdmissibility-PT-02 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;