Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r263-smll-167863538300482.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PermAdmissibility-COL-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r263-smll-167863538300482
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 6.2K Feb 26 01:21 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K Feb 26 01:21 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 26 01:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 26 01:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Feb 25 16:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:31 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:31 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 01:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Feb 26 01:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 01:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 101K Feb 26 01:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 37K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-00
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-01
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-02
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-03
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-04
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-05
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-06
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-07
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-08
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-09
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-10
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-11
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-12
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-13
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-14
FORMULA_NAME PermAdmissibility-COL-10-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678797237849

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PermAdmissibility-COL-10
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 12:34:00] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 12:34:00] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 12:34:00] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-14 12:34:01] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-14 12:34:01] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 868 ms
[2023-03-14 12:34:01] [INFO ] Imported 40 HL places and 16 HL transitions for a total of 208 PT places and 1024.0 transition bindings in 25 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 18 ms.
[2023-03-14 12:34:01] [INFO ] Built PT skeleton of HLPN with 40 places and 16 transitions 83 arcs in 16 ms.
[2023-03-14 12:34:01] [INFO ] Skeletonized 16 HLPN properties in 3 ms.
Computed a total of 40 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 40 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 12 formulas.
FORMULA PermAdmissibility-COL-10-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 12 properties that can be checked using skeleton over-approximation.
Initial state reduction rules removed 1 formulas.
FORMULA PermAdmissibility-COL-10-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 40 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 40 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Incomplete random walk after 10000 steps, including 56 resets, run finished after 113 ms. (steps per millisecond=88 ) properties (out of 22) seen :21
Finished Best-First random walk after 102 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=51 )
[2023-03-14 12:34:01] [INFO ] Flatten gal took : 30 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 9 ms
Symmetric sort wr.t. initial and guards and successors and join/free detected :input
Symmetric sort wr.t. initial detected :input
Symmetric sort wr.t. initial and guards detected :input
Applying symmetric unfolding of full symmetric sort :input domain size was 8
[2023-03-14 12:34:02] [INFO ] Unfolded HLPN to a Petri net with 40 places and 16 transitions 83 arcs in 13 ms.
[2023-03-14 12:34:02] [INFO ] Unfolded 14 HLPN properties in 1 ms.
Support contains 32 out of 40 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 40/40 places, 16/16 transitions.
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 32 transition count 16
Applied a total of 8 rules in 10 ms. Remains 32 /40 variables (removed 8) and now considering 16/16 (removed 0) transitions.
// Phase 1: matrix 16 rows 32 cols
[2023-03-14 12:34:02] [INFO ] Computed 16 place invariants in 9 ms
[2023-03-14 12:34:02] [INFO ] Implicit Places using invariants in 278 ms returned []
[2023-03-14 12:34:02] [INFO ] Invariant cache hit.
[2023-03-14 12:34:02] [INFO ] Implicit Places using invariants and state equation in 83 ms returned []
Implicit Place search using SMT with State Equation took 404 ms to find 0 implicit places.
[2023-03-14 12:34:02] [INFO ] Invariant cache hit.
[2023-03-14 12:34:02] [INFO ] Dead Transitions using invariants and state equation in 60 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 32/40 places, 16/16 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 477 ms. Remains : 32/40 places, 16/16 transitions.
Support contains 32 out of 32 places after structural reductions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 6 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 15 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Incomplete random walk after 10000 steps, including 56 resets, run finished after 128 ms. (steps per millisecond=78 ) properties (out of 32) seen :28
Finished Best-First random walk after 318 steps, including 0 resets, run visited all 4 properties in 4 ms. (steps per millisecond=79 )
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 5 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 5 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Computed a total of 32 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 32 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 30 transition count 16
Applied a total of 2 rules in 2 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 30/32 places, 16/16 transitions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 30 transition count 16
Applied a total of 2 rules in 3 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 30/32 places, 16/16 transitions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 2 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 4 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 32/32 places, 16/16 transitions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 9 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 2 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 30 transition count 16
Applied a total of 2 rules in 2 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 30/32 places, 16/16 transitions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 32/32 places, 16/16 transitions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 6 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 32/32 places, 16/16 transitions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 4 ms
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:02] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 24 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.2 ms
Discarding 8 places :
Also discarding 4 output transitions
Drop transitions removed 4 transitions
Ensure Unique test removed 1 places
Applied a total of 1 rules in 6 ms. Remains 23 /32 variables (removed 9) and now considering 12/16 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 23/32 places, 12/16 transitions.
[2023-03-14 12:34:02] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:03] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 1 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:03] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 24 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.0 ms
Discarding 8 places :
Also discarding 4 output transitions
Drop transitions removed 4 transitions
Ensure Unique test removed 1 places
Applied a total of 1 rules in 3 ms. Remains 23 /32 variables (removed 9) and now considering 12/16 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 23/32 places, 12/16 transitions.
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:03] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 20 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.0 ms
Discarding 12 places :
Also discarding 6 output transitions
Drop transitions removed 6 transitions
Applied a total of 1 rules in 3 ms. Remains 20 /32 variables (removed 12) and now considering 10/16 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 20/32 places, 10/16 transitions.
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 1 ms
[2023-03-14 12:34:03] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 2 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 32/32 places, 16/16 transitions.
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:03] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 30 transition count 16
Applied a total of 2 rules in 1 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/32 places, 16/16 transitions.
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:34:03] [INFO ] Input system was already deterministic with 16 transitions.
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:34:03] [INFO ] Flatten gal took : 4 ms
[2023-03-14 12:34:03] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 6 ms.
[2023-03-14 12:34:03] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 32 places, 16 transitions and 75 arcs took 1 ms.
Total runtime 2566 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PermAdmissibility-COL-10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA PermAdmissibility-COL-10-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-10-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678797353174

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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PermAdmissibility-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-COL-10-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
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PermAdmissibility-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-COL-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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25 CTL EXCL 5/276 7/32 PermAdmissibility-COL-10-CTLFireability-06 1485889 m, 297177 m/sec, 5274340 t fired, .

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25 CTL EXCL 10/276 12/32 PermAdmissibility-COL-10-CTLFireability-06 2806249 m, 264072 m/sec, 10790144 t fired, .

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PermAdmissibility-COL-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-COL-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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PermAdmissibility-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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52 CTL EXCL 3/299 3/32 PermAdmissibility-COL-10-CTLFireability-15 497426 m, 99485 m/sec, 4377249 t fired, .

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PermAdmissibility-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-COL-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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PermAdmissibility-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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52 CTL EXCL 8/299 5/32 PermAdmissibility-COL-10-CTLFireability-15 1167438 m, 134002 m/sec, 11077949 t fired, .

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52 CTL EXCL 13/299 8/32 PermAdmissibility-COL-10-CTLFireability-15 1794303 m, 125373 m/sec, 17403866 t fired, .

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PermAdmissibility-COL-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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52 CTL EXCL 18/299 10/32 PermAdmissibility-COL-10-CTLFireability-15 2431977 m, 127534 m/sec, 23943066 t fired, .

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52 CTL EXCL 23/299 13/32 PermAdmissibility-COL-10-CTLFireability-15 3129160 m, 139436 m/sec, 30968973 t fired, .

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52 CTL EXCL 28/299 16/32 PermAdmissibility-COL-10-CTLFireability-15 3842595 m, 142687 m/sec, 37877081 t fired, .

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52 CTL EXCL 33/299 19/32 PermAdmissibility-COL-10-CTLFireability-15 4557767 m, 143034 m/sec, 44690799 t fired, .

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37 CTL EXCL 3/1181 3/32 PermAdmissibility-COL-10-CTLFireability-08 532677 m, 106535 m/sec, 3328374 t fired, .

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37 CTL EXCL 8/1181 4/32 PermAdmissibility-COL-10-CTLFireability-08 899975 m, 73459 m/sec, 10336551 t fired, .

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37 CTL EXCL 18/1181 8/32 PermAdmissibility-COL-10-CTLFireability-08 1863064 m, 121844 m/sec, 23924827 t fired, .

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37 CTL EXCL 23/1181 10/32 PermAdmissibility-COL-10-CTLFireability-08 2347931 m, 96973 m/sec, 30566017 t fired, .

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37 CTL EXCL 28/1181 13/32 PermAdmissibility-COL-10-CTLFireability-08 2992702 m, 128954 m/sec, 38271586 t fired, .

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37 CTL EXCL 33/1181 15/32 PermAdmissibility-COL-10-CTLFireability-08 3482163 m, 97892 m/sec, 44934238 t fired, .

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37 CTL EXCL 38/1181 18/32 PermAdmissibility-COL-10-CTLFireability-08 4116682 m, 126903 m/sec, 52547795 t fired, .

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37 CTL EXCL 43/1181 20/32 PermAdmissibility-COL-10-CTLFireability-08 4668694 m, 110402 m/sec, 59510094 t fired, .

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PermAdmissibility-COL-10-CTLFireability-12: AGEF false tscc_search
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37 CTL EXCL 48/1181 22/32 PermAdmissibility-COL-10-CTLFireability-08 5238553 m, 113971 m/sec, 66567112 t fired, .

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lola: FINISHED task # 37 (type EXCL) for PermAdmissibility-COL-10-CTLFireability-08
lola: result : true
lola: markings : 5311735
lola: fired transitions : 67422317
lola: time used : 49.000000
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lola: LAUNCH task # 49 (type EXCL) for 48 PermAdmissibility-COL-10-CTLFireability-14
lola: time limit : 1747 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for PermAdmissibility-COL-10-CTLFireability-14
lola: result : true
lola: markings : 646811
lola: fired transitions : 4678344
lola: time used : 3.000000
lola: memory pages used : 3
lola: LAUNCH task # 34 (type EXCL) for 33 PermAdmissibility-COL-10-CTLFireability-07
lola: time limit : 3491 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for PermAdmissibility-COL-10-CTLFireability-07
lola: result : true
lola: markings : 161
lola: fired transitions : 400
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-COL-10-CTLFireability-00: CTL false CTL model checker
PermAdmissibility-COL-10-CTLFireability-01: CONJ true CONJ
PermAdmissibility-COL-10-CTLFireability-02: CTL true CTL model checker
PermAdmissibility-COL-10-CTLFireability-03: CTL true CTL model checker
PermAdmissibility-COL-10-CTLFireability-04: CTL true CTL model checker
PermAdmissibility-COL-10-CTLFireability-05: AXAF true state space /EXEG
PermAdmissibility-COL-10-CTLFireability-06: DISJ false DISJ
PermAdmissibility-COL-10-CTLFireability-07: CTL true CTL model checker
PermAdmissibility-COL-10-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-COL-10-CTLFireability-10: CTL true CTL model checker
PermAdmissibility-COL-10-CTLFireability-12: AGEF false tscc_search
PermAdmissibility-COL-10-CTLFireability-13: CTL true CTL model checker
PermAdmissibility-COL-10-CTLFireability-14: CTL true CTL model checker
PermAdmissibility-COL-10-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PermAdmissibility-COL-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r263-smll-167863538300482"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-10.tgz
mv PermAdmissibility-COL-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;