Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r263-smll-167863538300466.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PermAdmissibility-COL-02, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r263-smll-167863538300466
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 508K
-rw-r--r-- 1 mcc users 8.8K Feb 26 01:19 CTLCardinality.txt
-rw-r--r-- 1 mcc users 98K Feb 26 01:19 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Feb 26 01:18 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 01:18 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Feb 25 16:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.2K Feb 26 01:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 93K Feb 26 01:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K Feb 26 01:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 26 01:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 54K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-00
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-01
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-02
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-03
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-04
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-05
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-06
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-07
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-08
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-09
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-10
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-11
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-12
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-13
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-14
FORMULA_NAME PermAdmissibility-COL-02-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678796442835

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PermAdmissibility-COL-02
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 12:20:46] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 12:20:46] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 12:20:46] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-14 12:20:46] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-14 12:20:47] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 764 ms
[2023-03-14 12:20:47] [INFO ] Imported 40 HL places and 16 HL transitions for a total of 208 PT places and 1024.0 transition bindings in 26 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 27 ms.
FORMULA PermAdmissibility-COL-02-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-14 12:20:47] [INFO ] Built PT skeleton of HLPN with 40 places and 16 transitions 83 arcs in 6 ms.
[2023-03-14 12:20:47] [INFO ] Skeletonized 15 HLPN properties in 3 ms.
Initial state reduction rules removed 1 formulas.
FORMULA PermAdmissibility-COL-02-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 40 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 40 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 4 formulas.
FORMULA PermAdmissibility-COL-02-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 11 properties that can be checked using skeleton over-approximation.
Initial state reduction rules removed 2 formulas.
FORMULA PermAdmissibility-COL-02-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PermAdmissibility-COL-02-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 40 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 40 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Finished random walk after 43 steps, including 0 resets, run visited all 17 properties in 25 ms. (steps per millisecond=1 )
[2023-03-14 12:20:47] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-14 12:20:47] [INFO ] Flatten gal took : 34 ms
FORMULA PermAdmissibility-COL-02-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-14 12:20:47] [INFO ] Flatten gal took : 8 ms
Symmetric sort wr.t. initial and guards and successors and join/free detected :input
Symmetric sort wr.t. initial detected :input
Symmetric sort wr.t. initial and guards detected :input
Applying symmetric unfolding of full symmetric sort :input domain size was 8
[2023-03-14 12:20:47] [INFO ] Unfolded HLPN to a Petri net with 40 places and 16 transitions 83 arcs in 12 ms.
[2023-03-14 12:20:47] [INFO ] Unfolded 10 HLPN properties in 0 ms.
Support contains 32 out of 40 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 40/40 places, 16/16 transitions.
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 32 transition count 16
Applied a total of 8 rules in 9 ms. Remains 32 /40 variables (removed 8) and now considering 16/16 (removed 0) transitions.
// Phase 1: matrix 16 rows 32 cols
[2023-03-14 12:20:47] [INFO ] Computed 16 place invariants in 12 ms
[2023-03-14 12:20:47] [INFO ] Implicit Places using invariants in 210 ms returned []
[2023-03-14 12:20:47] [INFO ] Invariant cache hit.
[2023-03-14 12:20:47] [INFO ] Implicit Places using invariants and state equation in 109 ms returned []
Implicit Place search using SMT with State Equation took 357 ms to find 0 implicit places.
[2023-03-14 12:20:47] [INFO ] Invariant cache hit.
[2023-03-14 12:20:48] [INFO ] Dead Transitions using invariants and state equation in 87 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 32/40 places, 16/16 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 469 ms. Remains : 32/40 places, 16/16 transitions.
Support contains 32 out of 32 places after structural reductions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 6 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 7 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 16 transitions.
Finished random walk after 43 steps, including 0 resets, run visited all 20 properties in 8 ms. (steps per millisecond=5 )
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 4 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 5 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 16 transitions.
Computed a total of 32 stabilizing places and 16 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 32 transition count 16
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 32 /32 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 32/32 places, 16/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 19 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 4 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 1 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 4 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 4 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 1 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 4 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 24 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 4 output transitions
Drop transitions removed 4 transitions
Ensure Unique test removed 2 places
Applied a total of 1 rules in 7 ms. Remains 22 /32 variables (removed 10) and now considering 12/16 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 22/32 places, 12/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 12 transitions.
Finished random walk after 31 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=15 )
FORMULA PermAdmissibility-COL-02-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 20 are kept as prefixes of interest. Removing 12 places using SCC suffix rule.1 ms
Discarding 12 places :
Also discarding 6 output transitions
Drop transitions removed 6 transitions
Ensure Unique test removed 1 places
Applied a total of 1 rules in 3 ms. Remains 19 /32 variables (removed 13) and now considering 10/16 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 19/32 places, 10/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 3 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 31 transition count 16
Applied a total of 1 rules in 1 ms. Remains 31 /32 variables (removed 1) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 31/32 places, 16/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Applied a total of 0 rules in 2 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 30/32 places, 16/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 16 transitions.
Finished random walk after 34 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=17 )
FORMULA PermAdmissibility-COL-02-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Ensure Unique test removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 30 transition count 16
Applied a total of 2 rules in 1 ms. Remains 30 /32 variables (removed 2) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/32 places, 16/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 12 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 32/32 places, 16/16 transitions.
Graph (complete) has 81 edges and 32 vertex of which 28 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.0 ms
Discarding 4 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Ensure Unique test removed 2 places
Applied a total of 1 rules in 2 ms. Remains 26 /32 variables (removed 6) and now considering 14/16 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 26/32 places, 14/16 transitions.
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 2 ms
[2023-03-14 12:20:48] [INFO ] Input system was already deterministic with 14 transitions.
Finished random walk after 37 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=18 )
FORMULA PermAdmissibility-COL-02-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 3 ms
[2023-03-14 12:20:48] [INFO ] Flatten gal took : 4 ms
[2023-03-14 12:20:48] [INFO ] Export to MCC of 7 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-14 12:20:48] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 32 places, 16 transitions and 75 arcs took 1 ms.
Total runtime 2118 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PermAdmissibility-COL-02
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/365
CTLFireability

FORMULA PermAdmissibility-COL-02-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-02-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-02-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-02-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-02-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-02-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PermAdmissibility-COL-02-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678796449713

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/365/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/365/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/365/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 1 (type EXCL) for 0 PermAdmissibility-COL-02-CTLFireability-00
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 1 (type EXCL) for PermAdmissibility-COL-02-CTLFireability-00
lola: result : false
lola: markings : 15
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 20 (type EXCL) for 19 PermAdmissibility-COL-02-CTLFireability-09
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 20 (type EXCL) for PermAdmissibility-COL-02-CTLFireability-09
lola: result : false
lola: markings : 32
lola: fired transitions : 64
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 PermAdmissibility-COL-02-CTLFireability-11
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for PermAdmissibility-COL-02-CTLFireability-11
lola: result : true
lola: markings : 152
lola: fired transitions : 652
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 6 PermAdmissibility-COL-02-CTLFireability-03
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for PermAdmissibility-COL-02-CTLFireability-03
lola: result : false
lola: markings : 22
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 PermAdmissibility-COL-02-CTLFireability-02
lola: time limit : 1200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for PermAdmissibility-COL-02-CTLFireability-02
lola: result : false
lola: markings : 14
lola: fired transitions : 16
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 PermAdmissibility-COL-02-CTLFireability-07
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for PermAdmissibility-COL-02-CTLFireability-07
lola: result : false
lola: markings : 153
lola: fired transitions : 531
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 PermAdmissibility-COL-02-CTLFireability-08
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for PermAdmissibility-COL-02-CTLFireability-08
lola: result : false
lola: markings : 151
lola: fired transitions : 546
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-COL-02-CTLFireability-00: CTL false CTL model checker
PermAdmissibility-COL-02-CTLFireability-02: CTL false CTL model checker
PermAdmissibility-COL-02-CTLFireability-03: CONJ false CTL model checker
PermAdmissibility-COL-02-CTLFireability-07: CTL false CTL model checker
PermAdmissibility-COL-02-CTLFireability-08: CTL false CTL model checker
PermAdmissibility-COL-02-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-COL-02-CTLFireability-11: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-02"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PermAdmissibility-COL-02, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r263-smll-167863538300466"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-02.tgz
mv PermAdmissibility-COL-02 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;