About the Execution of LoLa+red for NoC3x3-PT-5A
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6193.680 | 564294.00 | 589626.00 | 1995.50 | ?FT???TT?TFFT?TT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r263-smll-167863538000290.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is NoC3x3-PT-5A, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r263-smll-167863538000290
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 696K
-rw-r--r-- 1 mcc users 7.4K Feb 26 09:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 26 09:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 26 09:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 26 09:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:28 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:28 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:28 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.1K Feb 26 09:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 26 09:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Feb 26 09:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 77K Feb 26 09:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 16:28 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:28 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 248K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-00
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-01
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-02
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-03
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-04
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-05
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-06
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-07
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-08
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-09
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-10
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-11
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-12
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-13
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-14
FORMULA_NAME NoC3x3-PT-5A-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678757741341
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=NoC3x3-PT-5A
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-14 01:35:44] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-14 01:35:44] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-14 01:35:44] [INFO ] Load time of PNML (sax parser for PT used): 208 ms
[2023-03-14 01:35:44] [INFO ] Transformed 417 places.
[2023-03-14 01:35:44] [INFO ] Transformed 933 transitions.
[2023-03-14 01:35:44] [INFO ] Found NUPN structural information;
[2023-03-14 01:35:44] [INFO ] Parsed PT model containing 417 places and 933 transitions and 3585 arcs in 357 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 24 ms.
Support contains 212 out of 417 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 417/417 places, 933/933 transitions.
Discarding 38 places :
Symmetric choice reduction at 0 with 38 rule applications. Total rules 38 place count 379 transition count 861
Iterating global reduction 0 with 38 rules applied. Total rules applied 76 place count 379 transition count 861
Drop transitions removed 33 transitions
Redundant transition composition rules discarded 33 transitions
Iterating global reduction 0 with 33 rules applied. Total rules applied 109 place count 379 transition count 828
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 110 place count 378 transition count 828
Applied a total of 110 rules in 126 ms. Remains 378 /417 variables (removed 39) and now considering 828/933 (removed 105) transitions.
[2023-03-14 01:35:45] [INFO ] Flow matrix only has 795 transitions (discarded 33 similar events)
// Phase 1: matrix 795 rows 378 cols
[2023-03-14 01:35:45] [INFO ] Computed 65 place invariants in 31 ms
[2023-03-14 01:35:45] [INFO ] Implicit Places using invariants in 543 ms returned [84, 120, 174, 287, 323]
Discarding 5 places :
Implicit Place search using SMT only with invariants took 586 ms to find 5 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 373/417 places, 828/933 transitions.
Applied a total of 0 rules in 25 ms. Remains 373 /373 variables (removed 0) and now considering 828/828 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 738 ms. Remains : 373/417 places, 828/933 transitions.
Support contains 212 out of 373 places after structural reductions.
[2023-03-14 01:35:46] [INFO ] Flatten gal took : 161 ms
[2023-03-14 01:35:46] [INFO ] Flatten gal took : 110 ms
[2023-03-14 01:35:46] [INFO ] Input system was already deterministic with 828 transitions.
Support contains 210 out of 373 places (down from 212) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 818 ms. (steps per millisecond=12 ) properties (out of 108) seen :91
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0
Running SMT prover for 17 properties.
[2023-03-14 01:35:47] [INFO ] Flow matrix only has 795 transitions (discarded 33 similar events)
// Phase 1: matrix 795 rows 373 cols
[2023-03-14 01:35:47] [INFO ] Computed 60 place invariants in 13 ms
[2023-03-14 01:35:48] [INFO ] [Real]Absence check using 60 positive place invariants in 26 ms returned sat
[2023-03-14 01:35:48] [INFO ] After 422ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:16
[2023-03-14 01:35:48] [INFO ] [Nat]Absence check using 60 positive place invariants in 28 ms returned sat
[2023-03-14 01:35:50] [INFO ] After 1463ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :16
[2023-03-14 01:35:50] [INFO ] State equation strengthened by 21 read => feed constraints.
[2023-03-14 01:35:52] [INFO ] After 2312ms SMT Verify possible using 21 Read/Feed constraints in natural domain returned unsat :1 sat :16
[2023-03-14 01:35:53] [INFO ] Deduced a trap composed of 20 places in 116 ms of which 10 ms to minimize.
[2023-03-14 01:35:53] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 256 ms
[2023-03-14 01:35:55] [INFO ] After 4867ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :16
Attempting to minimize the solution found.
Minimization took 1922 ms.
[2023-03-14 01:35:56] [INFO ] After 8778ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :16
Fused 17 Parikh solutions to 16 different solutions.
Parikh walk visited 0 properties in 392 ms.
Support contains 61 out of 373 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 373/373 places, 828/828 transitions.
Discarding 31 places :
Symmetric choice reduction at 0 with 31 rule applications. Total rules 31 place count 342 transition count 751
Iterating global reduction 0 with 31 rules applied. Total rules applied 62 place count 342 transition count 751
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 64 place count 342 transition count 749
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 65 place count 341 transition count 745
Iterating global reduction 1 with 1 rules applied. Total rules applied 66 place count 341 transition count 745
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 68 place count 341 transition count 743
Partial Free-agglomeration rule applied 49 times.
Drop transitions removed 49 transitions
Iterating global reduction 2 with 49 rules applied. Total rules applied 117 place count 341 transition count 743
Applied a total of 117 rules in 146 ms. Remains 341 /373 variables (removed 32) and now considering 743/828 (removed 85) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 147 ms. Remains : 341/373 places, 743/828 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 413 ms. (steps per millisecond=24 ) properties (out of 16) seen :9
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-14 01:35:58] [INFO ] Flow matrix only has 737 transitions (discarded 6 similar events)
// Phase 1: matrix 737 rows 341 cols
[2023-03-14 01:35:58] [INFO ] Computed 60 place invariants in 4 ms
[2023-03-14 01:35:58] [INFO ] [Real]Absence check using 60 positive place invariants in 17 ms returned sat
[2023-03-14 01:35:58] [INFO ] After 384ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:7
[2023-03-14 01:35:58] [INFO ] [Nat]Absence check using 60 positive place invariants in 26 ms returned sat
[2023-03-14 01:35:59] [INFO ] After 823ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :7
[2023-03-14 01:35:59] [INFO ] State equation strengthened by 33 read => feed constraints.
[2023-03-14 01:36:00] [INFO ] After 903ms SMT Verify possible using 33 Read/Feed constraints in natural domain returned unsat :0 sat :7
[2023-03-14 01:36:01] [INFO ] After 1760ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :7
Attempting to minimize the solution found.
Minimization took 1341 ms.
[2023-03-14 01:36:02] [INFO ] After 4181ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :7
Parikh walk visited 0 properties in 114 ms.
Support contains 34 out of 341 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 341/341 places, 743/743 transitions.
Graph (complete) has 1749 edges and 341 vertex of which 340 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.4 ms
Discarding 1 places :
Also discarding 0 output transitions
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 6 place count 335 transition count 730
Iterating global reduction 0 with 5 rules applied. Total rules applied 11 place count 335 transition count 730
Partial Free-agglomeration rule applied 4 times.
Drop transitions removed 4 transitions
Iterating global reduction 0 with 4 rules applied. Total rules applied 15 place count 335 transition count 730
Applied a total of 15 rules in 89 ms. Remains 335 /341 variables (removed 6) and now considering 730/743 (removed 13) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 89 ms. Remains : 335/341 places, 730/743 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 314 ms. (steps per millisecond=31 ) properties (out of 7) seen :2
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-03-14 01:36:03] [INFO ] Flow matrix only has 724 transitions (discarded 6 similar events)
// Phase 1: matrix 724 rows 335 cols
[2023-03-14 01:36:03] [INFO ] Computed 59 place invariants in 18 ms
[2023-03-14 01:36:03] [INFO ] [Real]Absence check using 59 positive place invariants in 18 ms returned sat
[2023-03-14 01:36:03] [INFO ] After 158ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-14 01:36:03] [INFO ] [Nat]Absence check using 59 positive place invariants in 17 ms returned sat
[2023-03-14 01:36:04] [INFO ] After 564ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2023-03-14 01:36:04] [INFO ] State equation strengthened by 35 read => feed constraints.
[2023-03-14 01:36:04] [INFO ] After 652ms SMT Verify possible using 35 Read/Feed constraints in natural domain returned unsat :0 sat :5
[2023-03-14 01:36:05] [INFO ] After 1271ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 470 ms.
[2023-03-14 01:36:06] [INFO ] After 2465ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :5
Parikh walk visited 0 properties in 77 ms.
Support contains 24 out of 335 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 335/335 places, 730/730 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 334 transition count 728
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 334 transition count 728
Partial Free-agglomeration rule applied 6 times.
Drop transitions removed 6 transitions
Iterating global reduction 0 with 6 rules applied. Total rules applied 8 place count 334 transition count 728
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 10 place count 332 transition count 722
Iterating global reduction 0 with 2 rules applied. Total rules applied 12 place count 332 transition count 722
Applied a total of 12 rules in 87 ms. Remains 332 /335 variables (removed 3) and now considering 722/730 (removed 8) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 88 ms. Remains : 332/335 places, 722/730 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 507 ms. (steps per millisecond=19 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 5) seen :0
Interrupted probabilistic random walk after 164842 steps, run timeout after 3001 ms. (steps per millisecond=54 ) properties seen :{}
Probabilistic random walk after 164842 steps, saw 154275 distinct states, run finished after 3006 ms. (steps per millisecond=54 ) properties seen :0
Running SMT prover for 5 properties.
[2023-03-14 01:36:09] [INFO ] Flow matrix only has 717 transitions (discarded 5 similar events)
// Phase 1: matrix 717 rows 332 cols
[2023-03-14 01:36:09] [INFO ] Computed 59 place invariants in 5 ms
[2023-03-14 01:36:10] [INFO ] [Real]Absence check using 59 positive place invariants in 29 ms returned sat
[2023-03-14 01:36:10] [INFO ] After 631ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-14 01:36:10] [INFO ] [Nat]Absence check using 59 positive place invariants in 18 ms returned sat
[2023-03-14 01:36:11] [INFO ] After 541ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2023-03-14 01:36:11] [INFO ] State equation strengthened by 37 read => feed constraints.
[2023-03-14 01:36:11] [INFO ] After 425ms SMT Verify possible using 37 Read/Feed constraints in natural domain returned unsat :0 sat :5
[2023-03-14 01:36:12] [INFO ] After 906ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 219 ms.
[2023-03-14 01:36:12] [INFO ] After 1891ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :5
Parikh walk visited 0 properties in 89 ms.
Support contains 24 out of 332 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 332/332 places, 722/722 transitions.
Applied a total of 0 rules in 32 ms. Remains 332 /332 variables (removed 0) and now considering 722/722 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 32 ms. Remains : 332/332 places, 722/722 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 332/332 places, 722/722 transitions.
Applied a total of 0 rules in 23 ms. Remains 332 /332 variables (removed 0) and now considering 722/722 (removed 0) transitions.
[2023-03-14 01:36:12] [INFO ] Flow matrix only has 717 transitions (discarded 5 similar events)
[2023-03-14 01:36:12] [INFO ] Invariant cache hit.
[2023-03-14 01:36:12] [INFO ] Implicit Places using invariants in 433 ms returned [39, 215]
Discarding 2 places :
Implicit Place search using SMT only with invariants took 436 ms to find 2 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 1 : 330/332 places, 722/722 transitions.
Partial Free-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 330 transition count 722
Applied a total of 2 rules in 43 ms. Remains 330 /330 variables (removed 0) and now considering 722/722 (removed 0) transitions.
[2023-03-14 01:36:13] [INFO ] Flow matrix only has 717 transitions (discarded 5 similar events)
// Phase 1: matrix 717 rows 330 cols
[2023-03-14 01:36:13] [INFO ] Computed 57 place invariants in 3 ms
[2023-03-14 01:36:13] [INFO ] Implicit Places using invariants in 454 ms returned []
[2023-03-14 01:36:13] [INFO ] Flow matrix only has 717 transitions (discarded 5 similar events)
[2023-03-14 01:36:13] [INFO ] Invariant cache hit.
[2023-03-14 01:36:13] [INFO ] State equation strengthened by 36 read => feed constraints.
[2023-03-14 01:36:14] [INFO ] Implicit Places using invariants and state equation in 838 ms returned []
Implicit Place search using SMT with State Equation took 1295 ms to find 0 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 2 : 330/332 places, 722/722 transitions.
Finished structural reductions in REACHABILITY mode , in 2 iterations and 1810 ms. Remains : 330/332 places, 722/722 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 415 ms. (steps per millisecond=24 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 5) seen :0
Interrupted probabilistic random walk after 143599 steps, run timeout after 3001 ms. (steps per millisecond=47 ) properties seen :{}
Probabilistic random walk after 143599 steps, saw 134517 distinct states, run finished after 3003 ms. (steps per millisecond=47 ) properties seen :0
Running SMT prover for 5 properties.
[2023-03-14 01:36:17] [INFO ] Flow matrix only has 717 transitions (discarded 5 similar events)
[2023-03-14 01:36:17] [INFO ] Invariant cache hit.
[2023-03-14 01:36:18] [INFO ] [Real]Absence check using 57 positive place invariants in 15 ms returned sat
[2023-03-14 01:36:18] [INFO ] After 149ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-14 01:36:18] [INFO ] [Nat]Absence check using 57 positive place invariants in 16 ms returned sat
[2023-03-14 01:36:18] [INFO ] After 534ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2023-03-14 01:36:18] [INFO ] State equation strengthened by 36 read => feed constraints.
[2023-03-14 01:36:19] [INFO ] After 305ms SMT Verify possible using 36 Read/Feed constraints in natural domain returned unsat :0 sat :5
[2023-03-14 01:36:19] [INFO ] After 808ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 295 ms.
[2023-03-14 01:36:19] [INFO ] After 1787ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :5
Parikh walk visited 0 properties in 66 ms.
Support contains 24 out of 330 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 330/330 places, 722/722 transitions.
Applied a total of 0 rules in 19 ms. Remains 330 /330 variables (removed 0) and now considering 722/722 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 20 ms. Remains : 330/330 places, 722/722 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 330/330 places, 722/722 transitions.
Applied a total of 0 rules in 19 ms. Remains 330 /330 variables (removed 0) and now considering 722/722 (removed 0) transitions.
[2023-03-14 01:36:19] [INFO ] Flow matrix only has 717 transitions (discarded 5 similar events)
[2023-03-14 01:36:19] [INFO ] Invariant cache hit.
[2023-03-14 01:36:20] [INFO ] Implicit Places using invariants in 638 ms returned []
[2023-03-14 01:36:20] [INFO ] Flow matrix only has 717 transitions (discarded 5 similar events)
[2023-03-14 01:36:20] [INFO ] Invariant cache hit.
[2023-03-14 01:36:20] [INFO ] State equation strengthened by 36 read => feed constraints.
[2023-03-14 01:36:21] [INFO ] Implicit Places using invariants and state equation in 715 ms returned []
Implicit Place search using SMT with State Equation took 1358 ms to find 0 implicit places.
[2023-03-14 01:36:21] [INFO ] Redundant transitions in 50 ms returned []
[2023-03-14 01:36:21] [INFO ] Flow matrix only has 717 transitions (discarded 5 similar events)
[2023-03-14 01:36:21] [INFO ] Invariant cache hit.
[2023-03-14 01:36:21] [INFO ] Dead Transitions using invariants and state equation in 574 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2010 ms. Remains : 330/330 places, 722/722 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 330 transition count 717
Partial Free-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 1 with 2 rules applied. Total rules applied 7 place count 330 transition count 717
Applied a total of 7 rules in 24 ms. Remains 330 /330 variables (removed 0) and now considering 717/722 (removed 5) transitions.
Running SMT prover for 5 properties.
// Phase 1: matrix 717 rows 330 cols
[2023-03-14 01:36:22] [INFO ] Computed 57 place invariants in 2 ms
[2023-03-14 01:36:22] [INFO ] [Real]Absence check using 57 positive place invariants in 15 ms returned sat
[2023-03-14 01:36:22] [INFO ] After 146ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-14 01:36:22] [INFO ] [Nat]Absence check using 57 positive place invariants in 21 ms returned sat
[2023-03-14 01:36:23] [INFO ] After 748ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2023-03-14 01:36:23] [INFO ] After 1397ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :5
Attempting to minimize the solution found.
Minimization took 337 ms.
[2023-03-14 01:36:24] [INFO ] After 1917ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :5
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-14 01:36:24] [INFO ] Flatten gal took : 62 ms
[2023-03-14 01:36:24] [INFO ] Flatten gal took : 63 ms
[2023-03-14 01:36:24] [INFO ] Input system was already deterministic with 828 transitions.
Computed a total of 4 stabilizing places and 1 stable transitions
Graph (complete) has 1871 edges and 373 vertex of which 372 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.10 ms
Starting structural reductions in SI_CTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Discarding 37 places :
Symmetric choice reduction at 0 with 37 rule applications. Total rules 37 place count 336 transition count 735
Iterating global reduction 0 with 37 rules applied. Total rules applied 74 place count 336 transition count 735
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 76 place count 336 transition count 733
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 78 place count 334 transition count 725
Iterating global reduction 1 with 2 rules applied. Total rules applied 80 place count 334 transition count 725
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 84 place count 334 transition count 721
Applied a total of 84 rules in 64 ms. Remains 334 /373 variables (removed 39) and now considering 721/828 (removed 107) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 65 ms. Remains : 334/373 places, 721/828 transitions.
[2023-03-14 01:36:24] [INFO ] Flatten gal took : 60 ms
[2023-03-14 01:36:24] [INFO ] Flatten gal took : 60 ms
[2023-03-14 01:36:24] [INFO ] Input system was already deterministic with 721 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 44 places :
Symmetric choice reduction at 1 with 44 rule applications. Total rules 45 place count 328 transition count 716
Iterating global reduction 1 with 44 rules applied. Total rules applied 89 place count 328 transition count 716
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 91 place count 328 transition count 714
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 94 place count 325 transition count 702
Iterating global reduction 2 with 3 rules applied. Total rules applied 97 place count 325 transition count 702
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 103 place count 325 transition count 696
Applied a total of 103 rules in 20 ms. Remains 325 /373 variables (removed 48) and now considering 696/828 (removed 132) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 20 ms. Remains : 325/373 places, 696/828 transitions.
[2023-03-14 01:36:24] [INFO ] Flatten gal took : 30 ms
[2023-03-14 01:36:24] [INFO ] Flatten gal took : 34 ms
[2023-03-14 01:36:24] [INFO ] Input system was already deterministic with 696 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Graph (complete) has 1871 edges and 373 vertex of which 372 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.3 ms
Discarding 1 places :
Also discarding 0 output transitions
Discarding 39 places :
Symmetric choice reduction at 0 with 39 rule applications. Total rules 40 place count 333 transition count 728
Iterating global reduction 0 with 39 rules applied. Total rules applied 79 place count 333 transition count 728
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 81 place count 333 transition count 726
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 83 place count 331 transition count 718
Iterating global reduction 1 with 2 rules applied. Total rules applied 85 place count 331 transition count 718
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 89 place count 331 transition count 714
Applied a total of 89 rules in 33 ms. Remains 331 /373 variables (removed 42) and now considering 714/828 (removed 114) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 33 ms. Remains : 331/373 places, 714/828 transitions.
[2023-03-14 01:36:24] [INFO ] Flatten gal took : 31 ms
[2023-03-14 01:36:24] [INFO ] Flatten gal took : 30 ms
[2023-03-14 01:36:25] [INFO ] Input system was already deterministic with 714 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 42 places :
Symmetric choice reduction at 1 with 42 rule applications. Total rules 43 place count 330 transition count 722
Iterating global reduction 1 with 42 rules applied. Total rules applied 85 place count 330 transition count 722
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 87 place count 330 transition count 720
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 89 place count 328 transition count 712
Iterating global reduction 2 with 2 rules applied. Total rules applied 91 place count 328 transition count 712
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 95 place count 328 transition count 708
Applied a total of 95 rules in 13 ms. Remains 328 /373 variables (removed 45) and now considering 708/828 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 328/373 places, 708/828 transitions.
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 28 ms
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 31 ms
[2023-03-14 01:36:25] [INFO ] Input system was already deterministic with 708 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Graph (complete) has 1871 edges and 373 vertex of which 372 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 0 output transitions
Discarding 42 places :
Symmetric choice reduction at 0 with 42 rule applications. Total rules 43 place count 330 transition count 721
Iterating global reduction 0 with 42 rules applied. Total rules applied 85 place count 330 transition count 721
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 87 place count 330 transition count 719
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 90 place count 327 transition count 707
Iterating global reduction 1 with 3 rules applied. Total rules applied 93 place count 327 transition count 707
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 99 place count 327 transition count 701
Applied a total of 99 rules in 29 ms. Remains 327 /373 variables (removed 46) and now considering 701/828 (removed 127) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 327/373 places, 701/828 transitions.
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 25 ms
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 28 ms
[2023-03-14 01:36:25] [INFO ] Input system was already deterministic with 701 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 41 places :
Symmetric choice reduction at 1 with 41 rule applications. Total rules 42 place count 331 transition count 726
Iterating global reduction 1 with 41 rules applied. Total rules applied 83 place count 331 transition count 726
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 85 place count 331 transition count 724
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 88 place count 328 transition count 712
Iterating global reduction 2 with 3 rules applied. Total rules applied 91 place count 328 transition count 712
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 97 place count 328 transition count 706
Applied a total of 97 rules in 14 ms. Remains 328 /373 variables (removed 45) and now considering 706/828 (removed 122) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 328/373 places, 706/828 transitions.
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 26 ms
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 30 ms
[2023-03-14 01:36:25] [INFO ] Input system was already deterministic with 706 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 36 places :
Symmetric choice reduction at 1 with 36 rule applications. Total rules 37 place count 336 transition count 741
Iterating global reduction 1 with 36 rules applied. Total rules applied 73 place count 336 transition count 741
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 76 place count 333 transition count 729
Iterating global reduction 1 with 3 rules applied. Total rules applied 79 place count 333 transition count 729
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 85 place count 333 transition count 723
Applied a total of 85 rules in 12 ms. Remains 333 /373 variables (removed 40) and now considering 723/828 (removed 105) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 333/373 places, 723/828 transitions.
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 32 ms
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 32 ms
[2023-03-14 01:36:25] [INFO ] Input system was already deterministic with 723 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Graph (complete) has 1871 edges and 373 vertex of which 372 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 0 output transitions
Discarding 42 places :
Symmetric choice reduction at 0 with 42 rule applications. Total rules 43 place count 330 transition count 722
Iterating global reduction 0 with 42 rules applied. Total rules applied 85 place count 330 transition count 722
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 87 place count 330 transition count 720
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 89 place count 328 transition count 712
Iterating global reduction 1 with 2 rules applied. Total rules applied 91 place count 328 transition count 712
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 95 place count 328 transition count 708
Applied a total of 95 rules in 29 ms. Remains 328 /373 variables (removed 45) and now considering 708/828 (removed 120) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 328/373 places, 708/828 transitions.
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 27 ms
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 28 ms
[2023-03-14 01:36:25] [INFO ] Input system was already deterministic with 708 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Graph (complete) has 1871 edges and 373 vertex of which 372 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 0 output transitions
Discarding 40 places :
Symmetric choice reduction at 0 with 40 rule applications. Total rules 41 place count 332 transition count 728
Iterating global reduction 0 with 40 rules applied. Total rules applied 81 place count 332 transition count 728
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 83 place count 332 transition count 726
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 85 place count 330 transition count 718
Iterating global reduction 1 with 2 rules applied. Total rules applied 87 place count 330 transition count 718
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 91 place count 330 transition count 714
Applied a total of 91 rules in 27 ms. Remains 330 /373 variables (removed 43) and now considering 714/828 (removed 114) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 330/373 places, 714/828 transitions.
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 24 ms
[2023-03-14 01:36:25] [INFO ] Flatten gal took : 46 ms
[2023-03-14 01:36:26] [INFO ] Input system was already deterministic with 714 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 40 places :
Symmetric choice reduction at 1 with 40 rule applications. Total rules 41 place count 332 transition count 728
Iterating global reduction 1 with 40 rules applied. Total rules applied 81 place count 332 transition count 728
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 83 place count 332 transition count 726
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 86 place count 329 transition count 714
Iterating global reduction 2 with 3 rules applied. Total rules applied 89 place count 329 transition count 714
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 95 place count 329 transition count 708
Applied a total of 95 rules in 13 ms. Remains 329 /373 variables (removed 44) and now considering 708/828 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 329/373 places, 708/828 transitions.
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 25 ms
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 28 ms
[2023-03-14 01:36:26] [INFO ] Input system was already deterministic with 708 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 41 places :
Symmetric choice reduction at 1 with 41 rule applications. Total rules 42 place count 331 transition count 723
Iterating global reduction 1 with 41 rules applied. Total rules applied 83 place count 331 transition count 723
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 85 place count 331 transition count 721
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 86 place count 330 transition count 717
Iterating global reduction 2 with 1 rules applied. Total rules applied 87 place count 330 transition count 717
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 89 place count 330 transition count 715
Applied a total of 89 rules in 14 ms. Remains 330 /373 variables (removed 43) and now considering 715/828 (removed 113) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 330/373 places, 715/828 transitions.
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 29 ms
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 51 ms
[2023-03-14 01:36:26] [INFO ] Input system was already deterministic with 715 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 44 places :
Symmetric choice reduction at 1 with 44 rule applications. Total rules 45 place count 328 transition count 716
Iterating global reduction 1 with 44 rules applied. Total rules applied 89 place count 328 transition count 716
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 91 place count 328 transition count 714
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 94 place count 325 transition count 702
Iterating global reduction 2 with 3 rules applied. Total rules applied 97 place count 325 transition count 702
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 103 place count 325 transition count 696
Applied a total of 103 rules in 19 ms. Remains 325 /373 variables (removed 48) and now considering 696/828 (removed 132) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 19 ms. Remains : 325/373 places, 696/828 transitions.
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 36 ms
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 38 ms
[2023-03-14 01:36:26] [INFO ] Input system was already deterministic with 696 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 39 places :
Symmetric choice reduction at 1 with 39 rule applications. Total rules 40 place count 333 transition count 728
Iterating global reduction 1 with 39 rules applied. Total rules applied 79 place count 333 transition count 728
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 81 place count 333 transition count 726
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 83 place count 331 transition count 718
Iterating global reduction 2 with 2 rules applied. Total rules applied 85 place count 331 transition count 718
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 89 place count 331 transition count 714
Applied a total of 89 rules in 21 ms. Remains 331 /373 variables (removed 42) and now considering 714/828 (removed 114) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 331/373 places, 714/828 transitions.
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 39 ms
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 41 ms
[2023-03-14 01:36:26] [INFO ] Input system was already deterministic with 714 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Graph (complete) has 1871 edges and 373 vertex of which 372 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 0 output transitions
Discarding 41 places :
Symmetric choice reduction at 0 with 41 rule applications. Total rules 42 place count 331 transition count 722
Iterating global reduction 0 with 41 rules applied. Total rules applied 83 place count 331 transition count 722
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 85 place count 331 transition count 720
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 88 place count 328 transition count 708
Iterating global reduction 1 with 3 rules applied. Total rules applied 91 place count 328 transition count 708
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 97 place count 328 transition count 702
Applied a total of 97 rules in 28 ms. Remains 328 /373 variables (removed 45) and now considering 702/828 (removed 126) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 328/373 places, 702/828 transitions.
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 22 ms
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 25 ms
[2023-03-14 01:36:26] [INFO ] Input system was already deterministic with 702 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 42 places :
Symmetric choice reduction at 1 with 42 rule applications. Total rules 43 place count 330 transition count 720
Iterating global reduction 1 with 42 rules applied. Total rules applied 85 place count 330 transition count 720
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 87 place count 330 transition count 718
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 90 place count 327 transition count 706
Iterating global reduction 2 with 3 rules applied. Total rules applied 93 place count 327 transition count 706
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 99 place count 327 transition count 700
Applied a total of 99 rules in 15 ms. Remains 327 /373 variables (removed 46) and now considering 700/828 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 327/373 places, 700/828 transitions.
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 22 ms
[2023-03-14 01:36:26] [INFO ] Flatten gal took : 25 ms
[2023-03-14 01:36:27] [INFO ] Input system was already deterministic with 700 transitions.
Starting structural reductions in LTL mode, iteration 0 : 373/373 places, 828/828 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 372 transition count 828
Discarding 40 places :
Symmetric choice reduction at 1 with 40 rule applications. Total rules 41 place count 332 transition count 727
Iterating global reduction 1 with 40 rules applied. Total rules applied 81 place count 332 transition count 727
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 83 place count 332 transition count 725
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 85 place count 330 transition count 717
Iterating global reduction 2 with 2 rules applied. Total rules applied 87 place count 330 transition count 717
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 91 place count 330 transition count 713
Applied a total of 91 rules in 14 ms. Remains 330 /373 variables (removed 43) and now considering 713/828 (removed 115) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 330/373 places, 713/828 transitions.
[2023-03-14 01:36:27] [INFO ] Flatten gal took : 20 ms
[2023-03-14 01:36:27] [INFO ] Flatten gal took : 23 ms
[2023-03-14 01:36:27] [INFO ] Input system was already deterministic with 713 transitions.
[2023-03-14 01:36:27] [INFO ] Flatten gal took : 27 ms
[2023-03-14 01:36:27] [INFO ] Flatten gal took : 30 ms
[2023-03-14 01:36:27] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 10 ms.
[2023-03-14 01:36:27] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 373 places, 828 transitions and 3155 arcs took 9 ms.
Total runtime 42757 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT NoC3x3-PT-5A
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/369
CTLFireability
FORMULA NoC3x3-PT-5A-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-5A-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-5A-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-5A-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-5A-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-5A-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-5A-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-5A-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-5A-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA NoC3x3-PT-5A-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678758305635
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/369/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/369/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/369/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 7 (type EXCL) for 6 NoC3x3-PT-5A-CTLFireability-02
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for NoC3x3-PT-5A-CTLFireability-02
lola: result : true
lola: markings : 128
lola: fired transitions : 207
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 49 (type EXCL) for 42 NoC3x3-PT-5A-CTLFireability-14
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 5/211 4/32 NoC3x3-PT-5A-CTLFireability-14 759080 m, 151816 m/sec, 1254971 t fired, .
Time elapsed: 7 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 10/211 9/32 NoC3x3-PT-5A-CTLFireability-14 1691367 m, 186457 m/sec, 2798033 t fired, .
Time elapsed: 12 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 15/211 13/32 NoC3x3-PT-5A-CTLFireability-14 2541534 m, 170033 m/sec, 4315403 t fired, .
Time elapsed: 17 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 20/211 14/32 NoC3x3-PT-5A-CTLFireability-14 2566795 m, 5052 m/sec, 5830513 t fired, .
Time elapsed: 22 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 25/211 14/32 NoC3x3-PT-5A-CTLFireability-14 2566795 m, 0 m/sec, 7638000 t fired, .
Time elapsed: 27 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 30/211 14/32 NoC3x3-PT-5A-CTLFireability-14 2566795 m, 0 m/sec, 9399445 t fired, .
Time elapsed: 32 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 35/211 14/32 NoC3x3-PT-5A-CTLFireability-14 2566795 m, 0 m/sec, 11112684 t fired, .
Time elapsed: 37 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 40/211 16/32 NoC3x3-PT-5A-CTLFireability-14 3109814 m, 108603 m/sec, 12714762 t fired, .
Time elapsed: 42 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 45/211 20/32 NoC3x3-PT-5A-CTLFireability-14 3921007 m, 162238 m/sec, 14251578 t fired, .
Time elapsed: 47 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 50/211 24/32 NoC3x3-PT-5A-CTLFireability-14 4756968 m, 167192 m/sec, 15773881 t fired, .
Time elapsed: 52 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 55/211 28/32 NoC3x3-PT-5A-CTLFireability-14 5578676 m, 164341 m/sec, 17268121 t fired, .
Time elapsed: 57 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 1 0 3 0 0 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 60/211 32/32 NoC3x3-PT-5A-CTLFireability-14 6397543 m, 163773 m/sec, 18772252 t fired, .
Time elapsed: 62 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 49 (type EXCL) for NoC3x3-PT-5A-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-11: AXAG 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-14: DISJ 0 2 0 0 3 0 1 0
NoC3x3-PT-5A-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 67 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 56 (type EXCL) for 33 NoC3x3-PT-5A-CTLFireability-11
lola: time limit : 220 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for NoC3x3-PT-5A-CTLFireability-11
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 NoC3x3-PT-5A-CTLFireability-15
lola: time limit : 235 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for NoC3x3-PT-5A-CTLFireability-15
lola: result : true
lola: markings : 101
lola: fired transitions : 202
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 42 NoC3x3-PT-5A-CTLFireability-14
lola: time limit : 252 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for NoC3x3-PT-5A-CTLFireability-14
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 42 NoC3x3-PT-5A-CTLFireability-14
lola: time limit : 271 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for NoC3x3-PT-5A-CTLFireability-14
lola: result : true
lola: markings : 73
lola: fired transitions : 73
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 NoC3x3-PT-5A-CTLFireability-12
lola: time limit : 294 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for NoC3x3-PT-5A-CTLFireability-12
lola: result : true
lola: markings : 101
lola: fired transitions : 203
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 NoC3x3-PT-5A-CTLFireability-10
lola: time limit : 321 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for NoC3x3-PT-5A-CTLFireability-10
lola: result : false
lola: markings : 131
lola: fired transitions : 575
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 NoC3x3-PT-5A-CTLFireability-09
lola: time limit : 353 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for NoC3x3-PT-5A-CTLFireability-09
lola: result : true
lola: markings : 114
lola: fired transitions : 456
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 NoC3x3-PT-5A-CTLFireability-06
lola: time limit : 392 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/392 4/32 NoC3x3-PT-5A-CTLFireability-06 600678 m, 120135 m/sec, 1122833 t fired, .
Time elapsed: 72 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/392 7/32 NoC3x3-PT-5A-CTLFireability-06 1207943 m, 121453 m/sec, 2262912 t fired, .
Time elapsed: 77 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/392 9/32 NoC3x3-PT-5A-CTLFireability-06 1790261 m, 116463 m/sec, 3371989 t fired, .
Time elapsed: 82 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/392 13/32 NoC3x3-PT-5A-CTLFireability-06 2447402 m, 131428 m/sec, 4515665 t fired, .
Time elapsed: 87 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/392 15/32 NoC3x3-PT-5A-CTLFireability-06 2824154 m, 75350 m/sec, 5170305 t fired, .
Time elapsed: 92 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 19 (type EXCL) for NoC3x3-PT-5A-CTLFireability-06
lola: result : true
lola: markings : 2824154
lola: fired transitions : 5170305
lola: time used : 25.000000
lola: memory pages used : 15
lola: LAUNCH task # 10 (type EXCL) for 9 NoC3x3-PT-5A-CTLFireability-03
lola: time limit : 438 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/438 4/32 NoC3x3-PT-5A-CTLFireability-03 577554 m, 115510 m/sec, 1274693 t fired, .
Time elapsed: 97 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/438 7/32 NoC3x3-PT-5A-CTLFireability-03 1202250 m, 124939 m/sec, 2654837 t fired, .
Time elapsed: 102 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/438 10/32 NoC3x3-PT-5A-CTLFireability-03 1825971 m, 124744 m/sec, 4040456 t fired, .
Time elapsed: 107 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/438 13/32 NoC3x3-PT-5A-CTLFireability-03 2444882 m, 123782 m/sec, 5415867 t fired, .
Time elapsed: 112 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/438 16/32 NoC3x3-PT-5A-CTLFireability-03 3050844 m, 121192 m/sec, 6764321 t fired, .
Time elapsed: 117 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/438 19/32 NoC3x3-PT-5A-CTLFireability-03 3680010 m, 125833 m/sec, 8162584 t fired, .
Time elapsed: 122 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 35/438 22/32 NoC3x3-PT-5A-CTLFireability-03 4295178 m, 123033 m/sec, 9535068 t fired, .
Time elapsed: 127 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 40/438 25/32 NoC3x3-PT-5A-CTLFireability-03 4914577 m, 123879 m/sec, 10915038 t fired, .
Time elapsed: 132 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 45/438 28/32 NoC3x3-PT-5A-CTLFireability-03 5535317 m, 124148 m/sec, 12298060 t fired, .
Time elapsed: 137 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 50/438 31/32 NoC3x3-PT-5A-CTLFireability-03 6147143 m, 122365 m/sec, 13665143 t fired, .
Time elapsed: 142 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for NoC3x3-PT-5A-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 147 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 NoC3x3-PT-5A-CTLFireability-01
lola: time limit : 493 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for NoC3x3-PT-5A-CTLFireability-01
lola: result : false
lola: markings : 74
lola: fired transitions : 74
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 NoC3x3-PT-5A-CTLFireability-05
lola: time limit : 575 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/575 4/32 NoC3x3-PT-5A-CTLFireability-05 642755 m, 128551 m/sec, 1704287 t fired, .
Time elapsed: 152 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/575 7/32 NoC3x3-PT-5A-CTLFireability-05 1291739 m, 129796 m/sec, 3417734 t fired, .
Time elapsed: 157 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/575 10/32 NoC3x3-PT-5A-CTLFireability-05 1939704 m, 129593 m/sec, 5168210 t fired, .
Time elapsed: 162 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/575 10/32 NoC3x3-PT-5A-CTLFireability-05 1939704 m, 0 m/sec, 6815832 t fired, .
Time elapsed: 167 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/575 10/32 NoC3x3-PT-5A-CTLFireability-05 1939704 m, 0 m/sec, 8664260 t fired, .
Time elapsed: 172 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 30/575 10/32 NoC3x3-PT-5A-CTLFireability-05 1967848 m, 5628 m/sec, 10477505 t fired, .
Time elapsed: 177 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 35/575 12/32 NoC3x3-PT-5A-CTLFireability-05 2296274 m, 65685 m/sec, 12191319 t fired, .
Time elapsed: 182 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 40/575 14/32 NoC3x3-PT-5A-CTLFireability-05 2641554 m, 69056 m/sec, 13885693 t fired, .
Time elapsed: 187 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 45/575 17/32 NoC3x3-PT-5A-CTLFireability-05 3187682 m, 109225 m/sec, 15653341 t fired, .
Time elapsed: 192 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 50/575 20/32 NoC3x3-PT-5A-CTLFireability-05 3795224 m, 121508 m/sec, 17424254 t fired, .
Time elapsed: 197 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 55/575 23/32 NoC3x3-PT-5A-CTLFireability-05 4425428 m, 126040 m/sec, 19200051 t fired, .
Time elapsed: 202 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 60/575 25/32 NoC3x3-PT-5A-CTLFireability-05 5035915 m, 122097 m/sec, 20924970 t fired, .
Time elapsed: 207 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 65/575 28/32 NoC3x3-PT-5A-CTLFireability-05 5642289 m, 121274 m/sec, 22634471 t fired, .
Time elapsed: 212 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 70/575 31/32 NoC3x3-PT-5A-CTLFireability-05 6239033 m, 119348 m/sec, 24329691 t fired, .
Time elapsed: 217 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for NoC3x3-PT-5A-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 222 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 NoC3x3-PT-5A-CTLFireability-13
lola: time limit : 675 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/675 4/32 NoC3x3-PT-5A-CTLFireability-13 647234 m, 129446 m/sec, 1716029 t fired, .
Time elapsed: 227 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/675 7/32 NoC3x3-PT-5A-CTLFireability-13 1315497 m, 133652 m/sec, 3480990 t fired, .
Time elapsed: 232 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/675 10/32 NoC3x3-PT-5A-CTLFireability-13 1957123 m, 128325 m/sec, 5217230 t fired, .
Time elapsed: 237 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/675 14/32 NoC3x3-PT-5A-CTLFireability-13 2558927 m, 120360 m/sec, 6907904 t fired, .
Time elapsed: 242 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/675 17/32 NoC3x3-PT-5A-CTLFireability-13 3161881 m, 120590 m/sec, 8577503 t fired, .
Time elapsed: 247 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 30/675 19/32 NoC3x3-PT-5A-CTLFireability-13 3740761 m, 115776 m/sec, 10258077 t fired, .
Time elapsed: 252 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 35/675 22/32 NoC3x3-PT-5A-CTLFireability-13 4342898 m, 120427 m/sec, 11961743 t fired, .
Time elapsed: 257 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 40/675 25/32 NoC3x3-PT-5A-CTLFireability-13 4924437 m, 116307 m/sec, 13606929 t fired, .
Time elapsed: 262 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 45/675 28/32 NoC3x3-PT-5A-CTLFireability-13 5496134 m, 114339 m/sec, 15222987 t fired, .
Time elapsed: 267 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 50/675 31/32 NoC3x3-PT-5A-CTLFireability-13 6071582 m, 115089 m/sec, 16849720 t fired, .
Time elapsed: 272 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 40 (type EXCL) for NoC3x3-PT-5A-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 277 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 NoC3x3-PT-5A-CTLFireability-04
lola: time limit : 830 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/830 4/32 NoC3x3-PT-5A-CTLFireability-04 685720 m, 137144 m/sec, 1663024 t fired, .
Time elapsed: 282 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/830 8/32 NoC3x3-PT-5A-CTLFireability-04 1363339 m, 135523 m/sec, 3301796 t fired, .
Time elapsed: 287 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/830 11/32 NoC3x3-PT-5A-CTLFireability-04 1947709 m, 116874 m/sec, 4919745 t fired, .
Time elapsed: 292 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/830 14/32 NoC3x3-PT-5A-CTLFireability-04 2511156 m, 112689 m/sec, 6498509 t fired, .
Time elapsed: 297 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/830 16/32 NoC3x3-PT-5A-CTLFireability-04 3079734 m, 113715 m/sec, 8078279 t fired, .
Time elapsed: 302 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/830 19/32 NoC3x3-PT-5A-CTLFireability-04 3645229 m, 113099 m/sec, 9663011 t fired, .
Time elapsed: 307 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/830 23/32 NoC3x3-PT-5A-CTLFireability-04 4264738 m, 123901 m/sec, 11285516 t fired, .
Time elapsed: 312 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/830 26/32 NoC3x3-PT-5A-CTLFireability-04 4858003 m, 118653 m/sec, 12886020 t fired, .
Time elapsed: 317 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/830 29/32 NoC3x3-PT-5A-CTLFireability-04 5545448 m, 137489 m/sec, 14470200 t fired, .
Time elapsed: 322 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for NoC3x3-PT-5A-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 327 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 NoC3x3-PT-5A-CTLFireability-08
lola: time limit : 1091 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/1091 2/32 NoC3x3-PT-5A-CTLFireability-08 298357 m, 59671 m/sec, 1693926 t fired, .
Time elapsed: 332 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/1091 3/32 NoC3x3-PT-5A-CTLFireability-08 598705 m, 60069 m/sec, 3383145 t fired, .
Time elapsed: 337 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/1091 5/32 NoC3x3-PT-5A-CTLFireability-08 894249 m, 59108 m/sec, 5055296 t fired, .
Time elapsed: 342 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/1091 6/32 NoC3x3-PT-5A-CTLFireability-08 1191460 m, 59442 m/sec, 6729473 t fired, .
Time elapsed: 347 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/1091 8/32 NoC3x3-PT-5A-CTLFireability-08 1483248 m, 58357 m/sec, 8384037 t fired, .
Time elapsed: 352 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 30/1091 9/32 NoC3x3-PT-5A-CTLFireability-08 1770856 m, 57521 m/sec, 10012765 t fired, .
Time elapsed: 357 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 35/1091 11/32 NoC3x3-PT-5A-CTLFireability-08 2053136 m, 56456 m/sec, 11651122 t fired, .
Time elapsed: 362 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 40/1091 12/32 NoC3x3-PT-5A-CTLFireability-08 2331311 m, 55635 m/sec, 13253148 t fired, .
Time elapsed: 367 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 45/1091 14/32 NoC3x3-PT-5A-CTLFireability-08 2606812 m, 55100 m/sec, 14853113 t fired, .
Time elapsed: 372 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 50/1091 15/32 NoC3x3-PT-5A-CTLFireability-08 2892056 m, 57048 m/sec, 16481505 t fired, .
Time elapsed: 377 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 55/1091 17/32 NoC3x3-PT-5A-CTLFireability-08 3179058 m, 57400 m/sec, 18157659 t fired, .
Time elapsed: 382 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 60/1091 18/32 NoC3x3-PT-5A-CTLFireability-08 3462107 m, 56609 m/sec, 19833395 t fired, .
Time elapsed: 387 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 65/1091 19/32 NoC3x3-PT-5A-CTLFireability-08 3741795 m, 55937 m/sec, 21481814 t fired, .
Time elapsed: 392 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 70/1091 21/32 NoC3x3-PT-5A-CTLFireability-08 4027166 m, 57074 m/sec, 23154900 t fired, .
Time elapsed: 397 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 75/1091 22/32 NoC3x3-PT-5A-CTLFireability-08 4314894 m, 57545 m/sec, 24823594 t fired, .
Time elapsed: 402 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 80/1091 24/32 NoC3x3-PT-5A-CTLFireability-08 4599797 m, 56980 m/sec, 26486699 t fired, .
Time elapsed: 407 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 85/1091 25/32 NoC3x3-PT-5A-CTLFireability-08 4882868 m, 56614 m/sec, 28134898 t fired, .
Time elapsed: 412 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 90/1091 26/32 NoC3x3-PT-5A-CTLFireability-08 5164399 m, 56306 m/sec, 29768812 t fired, .
Time elapsed: 417 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 95/1091 28/32 NoC3x3-PT-5A-CTLFireability-08 5447867 m, 56693 m/sec, 31424180 t fired, .
Time elapsed: 422 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 100/1091 29/32 NoC3x3-PT-5A-CTLFireability-08 5735611 m, 57548 m/sec, 33098091 t fired, .
Time elapsed: 427 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 105/1091 30/32 NoC3x3-PT-5A-CTLFireability-08 6018687 m, 56615 m/sec, 34751009 t fired, .
Time elapsed: 432 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 110/1091 32/32 NoC3x3-PT-5A-CTLFireability-08 6301019 m, 56466 m/sec, 36401944 t fired, .
Time elapsed: 437 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for NoC3x3-PT-5A-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 442 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 21 NoC3x3-PT-5A-CTLFireability-07
lola: time limit : 1579 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/1579 4/32 NoC3x3-PT-5A-CTLFireability-07 647250 m, 129450 m/sec, 1716147 t fired, .
Time elapsed: 447 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/1579 7/32 NoC3x3-PT-5A-CTLFireability-07 1292320 m, 129014 m/sec, 3419252 t fired, .
Time elapsed: 452 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/1579 10/32 NoC3x3-PT-5A-CTLFireability-07 1902112 m, 121958 m/sec, 5064370 t fired, .
Time elapsed: 457 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/1579 13/32 NoC3x3-PT-5A-CTLFireability-07 2461061 m, 111789 m/sec, 6626923 t fired, .
Time elapsed: 462 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 22 (type EXCL) for NoC3x3-PT-5A-CTLFireability-07
lola: result : true
lola: markings : 2461061
lola: fired transitions : 6626923
lola: time used : 21.000000
lola: memory pages used : 13
lola: LAUNCH task # 1 (type EXCL) for 0 NoC3x3-PT-5A-CTLFireability-00
lola: time limit : 3137 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 4/3137 3/32 NoC3x3-PT-5A-CTLFireability-00 484885 m, 96977 m/sec, 1374399 t fired, .
Time elapsed: 467 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 9/3137 6/32 NoC3x3-PT-5A-CTLFireability-00 1063273 m, 115677 m/sec, 3058414 t fired, .
Time elapsed: 472 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 14/3137 9/32 NoC3x3-PT-5A-CTLFireability-00 1636319 m, 114609 m/sec, 4723903 t fired, .
Time elapsed: 477 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 19/3137 12/32 NoC3x3-PT-5A-CTLFireability-00 2185860 m, 109908 m/sec, 6338848 t fired, .
Time elapsed: 482 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 24/3137 14/32 NoC3x3-PT-5A-CTLFireability-00 2751928 m, 113213 m/sec, 7947695 t fired, .
Time elapsed: 487 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 29/3137 17/32 NoC3x3-PT-5A-CTLFireability-00 3310201 m, 111654 m/sec, 9519617 t fired, .
Time elapsed: 492 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 34/3137 20/32 NoC3x3-PT-5A-CTLFireability-00 3874271 m, 112814 m/sec, 11104145 t fired, .
Time elapsed: 497 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 39/3137 23/32 NoC3x3-PT-5A-CTLFireability-00 4428113 m, 110768 m/sec, 12662374 t fired, .
Time elapsed: 502 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 44/3137 25/32 NoC3x3-PT-5A-CTLFireability-00 4983787 m, 111134 m/sec, 14221570 t fired, .
Time elapsed: 507 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 49/3137 30/32 NoC3x3-PT-5A-CTLFireability-00 5970775 m, 197397 m/sec, 15657573 t fired, .
Time elapsed: 512 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for NoC3x3-PT-5A-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
NoC3x3-PT-5A-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NoC3x3-PT-5A-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 517 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NoC3x3-PT-5A-CTLFireability-00: CTL unknown AGGR
NoC3x3-PT-5A-CTLFireability-01: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-02: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-03: CTL unknown AGGR
NoC3x3-PT-5A-CTLFireability-04: CTL unknown AGGR
NoC3x3-PT-5A-CTLFireability-05: CTL unknown AGGR
NoC3x3-PT-5A-CTLFireability-06: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-07: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-08: CTL unknown AGGR
NoC3x3-PT-5A-CTLFireability-09: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-10: CTL false CTL model checker
NoC3x3-PT-5A-CTLFireability-11: AXAG false state space /EXEF
NoC3x3-PT-5A-CTLFireability-12: CTL true CTL model checker
NoC3x3-PT-5A-CTLFireability-13: CTL unknown AGGR
NoC3x3-PT-5A-CTLFireability-14: DISJ true CTL model checker
NoC3x3-PT-5A-CTLFireability-15: CTL true CTL model checker
Time elapsed: 517 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="NoC3x3-PT-5A"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is NoC3x3-PT-5A, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r263-smll-167863538000290"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/NoC3x3-PT-5A.tgz
mv NoC3x3-PT-5A execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;