Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r263-smll-167863537600034.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is NQueens-PT-12, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r263-smll-167863537600034
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 660K
-rw-r--r-- 1 mcc users 6.7K Feb 26 17:10 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K Feb 26 17:10 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 17:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 17:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 17:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 183K Feb 26 17:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 17:10 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 77K Feb 26 17:10 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 134K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME NQueens-PT-12-CTLFireability-00
FORMULA_NAME NQueens-PT-12-CTLFireability-01
FORMULA_NAME NQueens-PT-12-CTLFireability-02
FORMULA_NAME NQueens-PT-12-CTLFireability-03
FORMULA_NAME NQueens-PT-12-CTLFireability-04
FORMULA_NAME NQueens-PT-12-CTLFireability-05
FORMULA_NAME NQueens-PT-12-CTLFireability-06
FORMULA_NAME NQueens-PT-12-CTLFireability-07
FORMULA_NAME NQueens-PT-12-CTLFireability-08
FORMULA_NAME NQueens-PT-12-CTLFireability-09
FORMULA_NAME NQueens-PT-12-CTLFireability-10
FORMULA_NAME NQueens-PT-12-CTLFireability-11
FORMULA_NAME NQueens-PT-12-CTLFireability-12
FORMULA_NAME NQueens-PT-12-CTLFireability-13
FORMULA_NAME NQueens-PT-12-CTLFireability-14
FORMULA_NAME NQueens-PT-12-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678706980658

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=NQueens-PT-12
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-13 11:29:43] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-13 11:29:43] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-13 11:29:43] [INFO ] Load time of PNML (sax parser for PT used): 142 ms
[2023-03-13 11:29:43] [INFO ] Transformed 216 places.
[2023-03-13 11:29:43] [INFO ] Transformed 144 transitions.
[2023-03-13 11:29:43] [INFO ] Parsed PT model containing 216 places and 144 transitions and 720 arcs in 294 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 20 ms.
Reduce places removed 2 places and 0 transitions.
Support contains 67 out of 214 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 214/214 places, 144/144 transitions.
Reduce places removed 144 places and 0 transitions.
Iterating post reduction 0 with 144 rules applied. Total rules applied 144 place count 70 transition count 144
Applied a total of 144 rules in 31 ms. Remains 70 /214 variables (removed 144) and now considering 144/144 (removed 0) transitions.
// Phase 1: matrix 144 rows 70 cols
[2023-03-13 11:29:44] [INFO ] Computed 7 place invariants in 31 ms
[2023-03-13 11:29:44] [INFO ] Implicit Places using invariants in 332 ms returned []
[2023-03-13 11:29:44] [INFO ] Invariant cache hit.
[2023-03-13 11:29:44] [INFO ] Implicit Places using invariants and state equation in 238 ms returned [69]
Discarding 1 places :
Implicit Place search using SMT with State Equation took 714 ms to find 1 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 69/214 places, 144/144 transitions.
Applied a total of 0 rules in 3 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 749 ms. Remains : 69/214 places, 144/144 transitions.
Support contains 67 out of 69 places after structural reductions.
[2023-03-13 11:29:45] [INFO ] Flatten gal took : 135 ms
[2023-03-13 11:29:45] [INFO ] Flatten gal took : 45 ms
[2023-03-13 11:29:45] [INFO ] Input system was already deterministic with 144 transitions.
Finished random walk after 46 steps, including 4 resets, run visited all 73 properties in 32 ms. (steps per millisecond=1 )
[2023-03-13 11:29:45] [INFO ] Flatten gal took : 28 ms
[2023-03-13 11:29:45] [INFO ] Flatten gal took : 35 ms
[2023-03-13 11:29:45] [INFO ] Input system was already deterministic with 144 transitions.
Computed a total of 69 stabilizing places and 144 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 69 transition count 144
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 3 formulas.
FORMULA NQueens-PT-12-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA NQueens-PT-12-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in SI_CTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 13 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:45] [INFO ] Flatten gal took : 31 ms
[2023-03-13 11:29:45] [INFO ] Flatten gal took : 26 ms
[2023-03-13 11:29:45] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 4 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:45] [INFO ] Flatten gal took : 29 ms
[2023-03-13 11:29:45] [INFO ] Flatten gal took : 25 ms
[2023-03-13 11:29:45] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 3 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:45] [INFO ] Flatten gal took : 27 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 16 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 4 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 14 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 16 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 13 ms
FORMULA NQueens-PT-12-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 12 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Support contains 0 out of 69 places (down from 19) after GAL structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 11 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 11 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 9 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 2 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 9 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 2 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 9 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 5 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 9 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 2 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 11 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 4 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 11 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 69/69 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 69 /69 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 69/69 places, 144/144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 9 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 9 ms
[2023-03-13 11:29:46] [INFO ] Input system was already deterministic with 144 transitions.
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Flatten gal took : 10 ms
[2023-03-13 11:29:46] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-13 11:29:46] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 69 places, 144 transitions and 575 arcs took 1 ms.
Total runtime 3162 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT NQueens-PT-12
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA NQueens-PT-12-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA NQueens-PT-12-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA NQueens-PT-12-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA NQueens-PT-12-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA NQueens-PT-12-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA NQueens-PT-12-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA NQueens-PT-12-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678707338323

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:314
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lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:331
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lola: rewrite Frontend/Parser/formula_rewrite.k:334
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23 CTL EXCL 5/327 7/32 NQueens-PT-12-CTLFireability-08 1333514 m, 266702 m/sec, 2262650 t fired, .

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23 CTL EXCL 10/327 13/32 NQueens-PT-12-CTLFireability-08 2683421 m, 269981 m/sec, 4602978 t fired, .

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23 CTL EXCL 15/327 19/32 NQueens-PT-12-CTLFireability-08 3948577 m, 253031 m/sec, 6836832 t fired, .

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23 CTL EXCL 20/327 25/32 NQueens-PT-12-CTLFireability-08 5197080 m, 249700 m/sec, 9023000 t fired, .

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23 CTL EXCL 25/327 31/32 NQueens-PT-12-CTLFireability-08 6383793 m, 237342 m/sec, 11110153 t fired, .

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41 CTL EXCL 5/356 8/32 NQueens-PT-12-CTLFireability-15 1575237 m, 315047 m/sec, 2680756 t fired, .

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41 CTL EXCL 10/356 15/32 NQueens-PT-12-CTLFireability-15 3014851 m, 287922 m/sec, 5153153 t fired, .

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41 CTL EXCL 15/356 21/32 NQueens-PT-12-CTLFireability-15 4410472 m, 279124 m/sec, 7534890 t fired, .

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41 CTL EXCL 20/356 28/32 NQueens-PT-12-CTLFireability-15 5752588 m, 268423 m/sec, 9893309 t fired, .

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NQueens-PT-12-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NQueens-PT-12-CTLFireability-11: EG 0 0 0 0 1 0 1 0
NQueens-PT-12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
NQueens-PT-12-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 25/828 21/32 NQueens-PT-12-CTLFireability-13 4399301 m, 172585 m/sec, 12587717 t fired, .

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NQueens-PT-12-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
NQueens-PT-12-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
NQueens-PT-12-CTLFireability-11: EG 0 0 0 0 1 0 1 0
NQueens-PT-12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
NQueens-PT-12-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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35 CTL EXCL 30/828 25/32 NQueens-PT-12-CTLFireability-13 5224367 m, 165013 m/sec, 14983721 t fired, .

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35 CTL EXCL 35/828 29/32 NQueens-PT-12-CTLFireability-13 6024856 m, 160097 m/sec, 17279058 t fired, .

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1 CTL EXCL 5/1091 8/32 NQueens-PT-12-CTLFireability-00 1582123 m, 316424 m/sec, 2577643 t fired, .

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1 CTL EXCL 10/1091 15/32 NQueens-PT-12-CTLFireability-00 3139757 m, 311526 m/sec, 5163433 t fired, .

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1 CTL EXCL 20/1091 29/32 NQueens-PT-12-CTLFireability-00 6053281 m, 284768 m/sec, 10087245 t fired, .

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NQueens-PT-12-CTLFireability-11: EG 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
NQueens-PT-12-CTLFireability-00: CTL unknown AGGR
NQueens-PT-12-CTLFireability-02: CTL unknown AGGR
NQueens-PT-12-CTLFireability-03: DISJ false DISJ
NQueens-PT-12-CTLFireability-04: CTL false CTL model checker
NQueens-PT-12-CTLFireability-06: CTL false CTL model checker
NQueens-PT-12-CTLFireability-07: CTL true CTL model checker
NQueens-PT-12-CTLFireability-08: CTL unknown AGGR
NQueens-PT-12-CTLFireability-10: CTL false CTL model checker
NQueens-PT-12-CTLFireability-11: EG unknown AGGR
NQueens-PT-12-CTLFireability-12: CTL true CTL model checker
NQueens-PT-12-CTLFireability-13: CTL unknown AGGR
NQueens-PT-12-CTLFireability-14: CTL false CTL model checker
NQueens-PT-12-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="NQueens-PT-12"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is NQueens-PT-12, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r263-smll-167863537600034"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/NQueens-PT-12.tgz
mv NQueens-PT-12 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;