About the Execution of LoLa+red for MAPKbis-PT-5320
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1043.836 | 134686.00 | 136107.00 | 451.80 | TFTTTFFTFF?TFTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416400642.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is MAPKbis-PT-5320, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416400642
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 768K
-rw-r--r-- 1 mcc users 8.3K Feb 25 16:19 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 16:19 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 16:03 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 16:03 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 16:22 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 16:22 LTLFireability.txt
-rw-r--r-- 1 mcc users 21K Feb 25 16:22 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 16:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 131K Feb 25 16:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 40K Feb 25 16:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 153K Feb 25 16:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 170K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-00
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-01
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-02
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-03
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-04
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-05
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-06
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-07
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-08
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-09
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-10
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-11
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-12
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-13
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-14
FORMULA_NAME MAPKbis-PT-5320-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679471036976
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=MAPKbis-PT-5320
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 07:43:58] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 07:43:58] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 07:43:58] [INFO ] Load time of PNML (sax parser for PT used): 49 ms
[2023-03-22 07:43:58] [INFO ] Transformed 106 places.
[2023-03-22 07:43:58] [INFO ] Transformed 173 transitions.
[2023-03-22 07:43:58] [INFO ] Found NUPN structural information;
[2023-03-22 07:43:58] [INFO ] Parsed PT model containing 106 places and 173 transitions and 986 arcs in 110 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Deduced a syphon composed of 29 places in 1 ms
Reduce places removed 33 places and 106 transitions.
Reduce places removed 25 places and 0 transitions.
FORMULA MAPKbis-PT-5320-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5320-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5320-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 27 out of 48 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 48/48 places, 67/67 transitions.
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 48 transition count 65
Applied a total of 2 rules in 11 ms. Remains 48 /48 variables (removed 0) and now considering 65/67 (removed 2) transitions.
[2023-03-22 07:43:58] [INFO ] Flow matrix only has 47 transitions (discarded 18 similar events)
// Phase 1: matrix 47 rows 48 cols
[2023-03-22 07:43:58] [INFO ] Computed 24 place invariants in 7 ms
[2023-03-22 07:43:58] [INFO ] Implicit Places using invariants in 169 ms returned []
[2023-03-22 07:43:58] [INFO ] Flow matrix only has 47 transitions (discarded 18 similar events)
[2023-03-22 07:43:58] [INFO ] Invariant cache hit.
[2023-03-22 07:43:58] [INFO ] State equation strengthened by 23 read => feed constraints.
[2023-03-22 07:43:58] [INFO ] Implicit Places using invariants and state equation in 91 ms returned []
Implicit Place search using SMT with State Equation took 283 ms to find 0 implicit places.
[2023-03-22 07:43:58] [INFO ] Flow matrix only has 47 transitions (discarded 18 similar events)
[2023-03-22 07:43:58] [INFO ] Invariant cache hit.
[2023-03-22 07:43:58] [INFO ] Dead Transitions using invariants and state equation in 71 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 48/48 places, 65/67 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 367 ms. Remains : 48/48 places, 65/67 transitions.
Support contains 27 out of 48 places after structural reductions.
[2023-03-22 07:43:59] [INFO ] Initial state reduction rules for CTL removed 7 formulas.
[2023-03-22 07:43:59] [INFO ] Flatten gal took : 23 ms
FORMULA MAPKbis-PT-5320-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5320-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5320-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5320-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5320-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5320-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPKbis-PT-5320-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-22 07:43:59] [INFO ] Flatten gal took : 8 ms
[2023-03-22 07:43:59] [INFO ] Input system was already deterministic with 65 transitions.
Support contains 22 out of 48 places (down from 27) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 286 resets, run finished after 329 ms. (steps per millisecond=30 ) properties (out of 12) seen :9
Incomplete Best-First random walk after 10000 steps, including 30 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
[2023-03-22 07:43:59] [INFO ] Flow matrix only has 47 transitions (discarded 18 similar events)
[2023-03-22 07:43:59] [INFO ] Invariant cache hit.
[2023-03-22 07:43:59] [INFO ] [Real]Absence check using 24 positive place invariants in 4 ms returned sat
[2023-03-22 07:43:59] [INFO ] After 24ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:2
[2023-03-22 07:43:59] [INFO ] State equation strengthened by 23 read => feed constraints.
[2023-03-22 07:43:59] [INFO ] After 5ms SMT Verify possible using 23 Read/Feed constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-22 07:43:59] [INFO ] After 95ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-22 07:43:59] [INFO ] [Nat]Absence check using 24 positive place invariants in 3 ms returned sat
[2023-03-22 07:43:59] [INFO ] After 23ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-22 07:43:59] [INFO ] After 16ms SMT Verify possible using 23 Read/Feed constraints in natural domain returned unsat :0 sat :3
[2023-03-22 07:43:59] [INFO ] After 40ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 27 ms.
[2023-03-22 07:43:59] [INFO ] After 141ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Parikh walk visited 0 properties in 5 ms.
Support contains 9 out of 48 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 48/48 places, 65/65 transitions.
Graph (complete) has 125 edges and 48 vertex of which 28 are kept as prefixes of interest. Removing 20 places using SCC suffix rule.2 ms
Discarding 20 places :
Also discarding 6 output transitions
Drop transitions removed 6 transitions
Drop transitions removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 0 with 18 rules applied. Total rules applied 19 place count 28 transition count 41
Applied a total of 19 rules in 14 ms. Remains 28 /48 variables (removed 20) and now considering 41/65 (removed 24) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 14 ms. Remains : 28/48 places, 41/65 transitions.
Incomplete random walk after 10000 steps, including 479 resets, run finished after 105 ms. (steps per millisecond=95 ) properties (out of 3) seen :1
Incomplete Best-First random walk after 10001 steps, including 88 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-22 07:44:00] [INFO ] Flow matrix only has 27 transitions (discarded 14 similar events)
// Phase 1: matrix 27 rows 28 cols
[2023-03-22 07:44:00] [INFO ] Computed 14 place invariants in 0 ms
[2023-03-22 07:44:00] [INFO ] [Real]Absence check using 14 positive place invariants in 2 ms returned sat
[2023-03-22 07:44:00] [INFO ] After 65ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-22 07:44:00] [INFO ] [Nat]Absence check using 14 positive place invariants in 1 ms returned sat
[2023-03-22 07:44:00] [INFO ] After 10ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-22 07:44:00] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-22 07:44:00] [INFO ] After 5ms SMT Verify possible using 13 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-22 07:44:00] [INFO ] After 12ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-22 07:44:00] [INFO ] After 54ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 1 ms.
Support contains 8 out of 28 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 28/28 places, 41/41 transitions.
Applied a total of 0 rules in 2 ms. Remains 28 /28 variables (removed 0) and now considering 41/41 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2 ms. Remains : 28/28 places, 41/41 transitions.
Incomplete random walk after 10000 steps, including 484 resets, run finished after 98 ms. (steps per millisecond=102 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 90 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 2) seen :0
Probably explored full state space saw : 7937 states, properties seen :1
Probabilistic random walk after 58882 steps, saw 7937 distinct states, run finished after 110 ms. (steps per millisecond=535 ) properties seen :1
Explored full state space saw : 7937 states, properties seen :0
Exhaustive walk after 58882 steps, saw 7937 distinct states, run finished after 53 ms. (steps per millisecond=1110 ) properties seen :0
Successfully simplified 1 atomic propositions for a total of 4 simplifications.
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:44:00] [INFO ] Input system was already deterministic with 65 transitions.
Computed a total of 2 stabilizing places and 1 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 48/48 places, 65/65 transitions.
Applied a total of 0 rules in 4 ms. Remains 48 /48 variables (removed 0) and now considering 65/65 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 48/48 places, 65/65 transitions.
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 5 ms
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:44:00] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 48/48 places, 65/65 transitions.
Applied a total of 0 rules in 1 ms. Remains 48 /48 variables (removed 0) and now considering 65/65 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 48/48 places, 65/65 transitions.
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:44:00] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 48/48 places, 65/65 transitions.
Applied a total of 0 rules in 1 ms. Remains 48 /48 variables (removed 0) and now considering 65/65 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 48/48 places, 65/65 transitions.
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 3 ms
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:44:00] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 48/48 places, 65/65 transitions.
Applied a total of 0 rules in 8 ms. Remains 48 /48 variables (removed 0) and now considering 65/65 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 48/48 places, 65/65 transitions.
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 3 ms
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 3 ms
[2023-03-22 07:44:00] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 48/48 places, 65/65 transitions.
Applied a total of 0 rules in 1 ms. Remains 48 /48 variables (removed 0) and now considering 65/65 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 48/48 places, 65/65 transitions.
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:44:00] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 48/48 places, 65/65 transitions.
Applied a total of 0 rules in 1 ms. Remains 48 /48 variables (removed 0) and now considering 65/65 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 48/48 places, 65/65 transitions.
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 3 ms
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 3 ms
[2023-03-22 07:44:00] [INFO ] Input system was already deterministic with 65 transitions.
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 3 ms
[2023-03-22 07:44:00] [INFO ] Flatten gal took : 4 ms
[2023-03-22 07:44:00] [INFO ] Export to MCC of 6 properties in file /home/mcc/execution/CTLFireability.sr.xml took 1 ms.
[2023-03-22 07:44:00] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 48 places, 65 transitions and 322 arcs took 0 ms.
Total runtime 2367 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT MAPKbis-PT-5320
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA MAPKbis-PT-5320-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5320-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5320-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5320-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPKbis-PT-5320-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679471171662
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 4 (type EXCL) for 3 MAPKbis-PT-5320-CTLFireability-07
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for MAPKbis-PT-5320-CTLFireability-07
lola: result : true
lola: markings : 25
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 MAPKbis-PT-5320-CTLFireability-00
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:776
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 1 (type EXCL) for MAPKbis-PT-5320-CTLFireability-00
lola: result : true
lola: markings : 11911
lola: fired transitions : 71799
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 MAPKbis-PT-5320-CTLFireability-14
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for MAPKbis-PT-5320-CTLFireability-14
lola: result : false
lola: markings : 20409
lola: fired transitions : 126517
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 MAPKbis-PT-5320-CTLFireability-11
lola: time limit : 1200 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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lola: FINISHED task # 13 (type EXCL) for MAPKbis-PT-5320-CTLFireability-11
lola: result : true
lola: markings : 4198688
lola: fired transitions : 50756632
lola: time used : 41.000000
lola: memory pages used : 17
lola: LAUNCH task # 18 (type EXCL) for 6 MAPKbis-PT-5320-CTLFireability-08
lola: time limit : 1779 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for MAPKbis-PT-5320-CTLFireability-08
lola: result : true
lola: markings : 724
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MAPKbis-PT-5320"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is MAPKbis-PT-5320, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416400642"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MAPKbis-PT-5320.tgz
mv MAPKbis-PT-5320 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;