Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416300610.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is MAPK-PT-02560, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416300610
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 504K
-rw-r--r-- 1 mcc users 9.7K Feb 26 10:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 104K Feb 26 10:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.5K Feb 26 10:51 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 10:51 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:22 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:22 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:22 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 10:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 26 10:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Feb 26 10:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 26 10:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 25K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME MAPK-PT-02560-CTLFireability-00
FORMULA_NAME MAPK-PT-02560-CTLFireability-01
FORMULA_NAME MAPK-PT-02560-CTLFireability-02
FORMULA_NAME MAPK-PT-02560-CTLFireability-03
FORMULA_NAME MAPK-PT-02560-CTLFireability-04
FORMULA_NAME MAPK-PT-02560-CTLFireability-05
FORMULA_NAME MAPK-PT-02560-CTLFireability-06
FORMULA_NAME MAPK-PT-02560-CTLFireability-07
FORMULA_NAME MAPK-PT-02560-CTLFireability-08
FORMULA_NAME MAPK-PT-02560-CTLFireability-09
FORMULA_NAME MAPK-PT-02560-CTLFireability-10
FORMULA_NAME MAPK-PT-02560-CTLFireability-11
FORMULA_NAME MAPK-PT-02560-CTLFireability-12
FORMULA_NAME MAPK-PT-02560-CTLFireability-13
FORMULA_NAME MAPK-PT-02560-CTLFireability-14
FORMULA_NAME MAPK-PT-02560-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679467798957

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=MAPK-PT-02560
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 06:50:00] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 06:50:00] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 06:50:00] [INFO ] Load time of PNML (sax parser for PT used): 22 ms
[2023-03-22 06:50:00] [INFO ] Transformed 22 places.
[2023-03-22 06:50:00] [INFO ] Transformed 30 transitions.
[2023-03-22 06:50:00] [INFO ] Parsed PT model containing 22 places and 30 transitions and 90 arcs in 78 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Initial state reduction rules removed 3 formulas.
FORMULA MAPK-PT-02560-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPK-PT-02560-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA MAPK-PT-02560-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 21 out of 22 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 8 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
// Phase 1: matrix 30 rows 22 cols
[2023-03-22 06:50:00] [INFO ] Computed 7 place invariants in 8 ms
[2023-03-22 06:50:00] [INFO ] Implicit Places using invariants in 136 ms returned []
[2023-03-22 06:50:00] [INFO ] Invariant cache hit.
[2023-03-22 06:50:00] [INFO ] Implicit Places using invariants and state equation in 44 ms returned []
Implicit Place search using SMT with State Equation took 203 ms to find 0 implicit places.
[2023-03-22 06:50:00] [INFO ] Invariant cache hit.
[2023-03-22 06:50:00] [INFO ] Dead Transitions using invariants and state equation in 45 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 258 ms. Remains : 22/22 places, 30/30 transitions.
Support contains 21 out of 22 places after structural reductions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 16 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 5 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Incomplete random walk after 10260 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=320 ) properties (out of 30) seen :16
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 88 ms. (steps per millisecond=113 ) properties (out of 14) seen :9
Finished Best-First random walk after 2666 steps, including 0 resets, run visited all 5 properties in 7 ms. (steps per millisecond=380 )
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 3 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 3 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 22 transition count 29
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 20 transition count 29
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 20 transition count 28
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 5 place count 20 transition count 27
Reduce places removed 2 places and 0 transitions.
Graph (trivial) has 3 edges and 18 vertex of which 2 / 18 are part of one of the 1 SCC in 1 ms
Free SCC test removed 1 places
Iterating post reduction 1 with 3 rules applied. Total rules applied 8 place count 17 transition count 27
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 10 place count 17 transition count 25
Applied a total of 10 rules in 11 ms. Remains 17 /22 variables (removed 5) and now considering 25/30 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 17/22 places, 25/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 25 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 6 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 22 transition count 29
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 20 transition count 29
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 20 transition count 28
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 5 place count 20 transition count 27
Reduce places removed 2 places and 0 transitions.
Graph (trivial) has 3 edges and 18 vertex of which 2 / 18 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Iterating post reduction 1 with 3 rules applied. Total rules applied 8 place count 17 transition count 27
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 10 place count 17 transition count 25
Applied a total of 10 rules in 3 ms. Remains 17 /22 variables (removed 5) and now considering 25/30 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 17/22 places, 25/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 25 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Input system was already deterministic with 30 transitions.
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-22 06:50:01] [INFO ] Flatten gal took : 2 ms
[2023-03-22 06:50:01] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-22 06:50:01] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 22 places, 30 transitions and 90 arcs took 1 ms.
Total runtime 1130 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT MAPK-PT-02560
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA MAPK-PT-02560-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-02560-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA MAPK-PT-02560-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679468068070

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 9 (type EXCL) for 6 MAPK-PT-02560-CTLFireability-02
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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44 AGEF EXCL 5/688 7/32 MAPK-PT-02560-CTLFireability-08 1886747 m, 377349 m/sec, 8451473 t fired, .

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MAPK-PT-02560-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-08: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/3360 7/32 MAPK-PT-02560-CTLFireability-02 1513096 m, 302619 m/sec, 8193583 t fired, .

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MAPK-PT-02560-CTLFireability-05: CTL true CTL model checker
MAPK-PT-02560-CTLFireability-10: CTL false CTL model checker
MAPK-PT-02560-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-02560-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-02: DISJ 0 0 1 0 2 0 1 0
MAPK-PT-02560-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-08: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/3360 13/32 MAPK-PT-02560-CTLFireability-02 3170130 m, 331406 m/sec, 14652260 t fired, .

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MAPK-PT-02560-CTLFireability-10: CTL false CTL model checker
MAPK-PT-02560-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-02560-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-02: DISJ 0 0 1 0 2 0 1 0
MAPK-PT-02560-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-08: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/3360 20/32 MAPK-PT-02560-CTLFireability-02 4934976 m, 352969 m/sec, 20571349 t fired, .

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MAPK-PT-02560-CTLFireability-05: CTL true CTL model checker
MAPK-PT-02560-CTLFireability-10: CTL false CTL model checker
MAPK-PT-02560-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-02560-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-02: DISJ 0 0 1 0 2 0 1 0
MAPK-PT-02560-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-08: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 20/3360 27/32 MAPK-PT-02560-CTLFireability-02 6663487 m, 345702 m/sec, 26385371 t fired, .

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MAPK-PT-02560-CTLFireability-05: CTL true CTL model checker
MAPK-PT-02560-CTLFireability-10: CTL false CTL model checker
MAPK-PT-02560-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-02560-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-02: DISJ 0 0 0 0 2 0 2 0
MAPK-PT-02560-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-08: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
MAPK-PT-02560-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-02560-CTLFireability-00: EFAG unknown AGGR
MAPK-PT-02560-CTLFireability-01: CTL unknown AGGR
MAPK-PT-02560-CTLFireability-02: DISJ unknown DISJ
MAPK-PT-02560-CTLFireability-03: CTL unknown AGGR
MAPK-PT-02560-CTLFireability-04: CTL unknown AGGR
MAPK-PT-02560-CTLFireability-05: CTL true CTL model checker
MAPK-PT-02560-CTLFireability-06: CTL unknown AGGR
MAPK-PT-02560-CTLFireability-07: CTL unknown AGGR
MAPK-PT-02560-CTLFireability-08: EFAG unknown AGGR
MAPK-PT-02560-CTLFireability-09: CTL unknown AGGR
MAPK-PT-02560-CTLFireability-10: CTL false CTL model checker
MAPK-PT-02560-CTLFireability-13: CTL false CTL model checker
MAPK-PT-02560-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MAPK-PT-02560"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is MAPK-PT-02560, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416300610"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/MAPK-PT-02560.tgz
mv MAPK-PT-02560 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;