About the Execution of LoLa+red for LamportFastMutEx-PT-5
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1788.684 | 464889.00 | 1836952.00 | 299.70 | TFTTTFFFFFFFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416000422.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LamportFastMutEx-PT-5, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416000422
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 12K Feb 25 13:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 25 13:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 25K Feb 25 13:40 CTLFireability.txt
-rw-r--r-- 1 mcc users 145K Feb 25 13:40 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 7.2K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 35K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 36K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 38K Feb 25 13:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 249K Feb 25 13:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 42K Feb 25 13:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 224K Feb 25 13:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.2K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 157K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1679452808029
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-PT-5
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 02:40:09] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-22 02:40:09] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 02:40:09] [INFO ] Load time of PNML (sax parser for PT used): 58 ms
[2023-03-22 02:40:09] [INFO ] Transformed 174 places.
[2023-03-22 02:40:09] [INFO ] Transformed 318 transitions.
[2023-03-22 02:40:09] [INFO ] Found NUPN structural information;
[2023-03-22 02:40:09] [INFO ] Completing missing partition info from NUPN : creating a component with [P_start_1_0, P_start_1_1, P_start_1_2, P_start_1_3, P_start_1_4, P_start_1_5, P_b_0_false, P_b_0_true, P_b_1_false, P_b_1_true, P_b_2_false, P_b_2_true, P_b_3_false, P_b_3_true, P_b_4_false, P_b_4_true, P_b_5_false, P_b_5_true, P_setx_3_0, P_setx_3_1, P_setx_3_2, P_setx_3_3, P_setx_3_4, P_setx_3_5, P_setbi_5_0, P_setbi_5_1, P_setbi_5_2, P_setbi_5_3, P_setbi_5_4, P_setbi_5_5, P_ify0_4_0, P_ify0_4_1, P_ify0_4_2, P_ify0_4_3, P_ify0_4_4, P_ify0_4_5, P_sety_9_0, P_sety_9_1, P_sety_9_2, P_sety_9_3, P_sety_9_4, P_sety_9_5, P_ifxi_10_0, P_ifxi_10_1, P_ifxi_10_2, P_ifxi_10_3, P_ifxi_10_4, P_ifxi_10_5, P_setbi_11_0, P_setbi_11_1, P_setbi_11_2, P_setbi_11_3, P_setbi_11_4, P_setbi_11_5, P_fordo_12_0, P_fordo_12_1, P_fordo_12_2, P_fordo_12_3, P_fordo_12_4, P_fordo_12_5, P_wait_0_0, P_wait_0_1, P_wait_0_2, P_wait_0_3, P_wait_0_4, P_wait_0_5, P_wait_1_0, P_wait_1_1, P_wait_1_2, P_wait_1_3, P_wait_1_4, P_wait_1_5, P_wait_2_0, P_wait_2_1, P_wait_2_2, P_wait_2_3, P_wait_2_4, P_wait_2_5, P_wait_3_0, P_wait_3_1, P_wait_3_2, P_wait_3_3, P_wait_3_4, P_wait_3_5, P_wait_4_0, P_wait_4_1, P_wait_4_2, P_wait_4_3, P_wait_4_4, P_wait_4_5, P_wait_5_0, P_wait_5_1, P_wait_5_2, P_wait_5_3, P_wait_5_4, P_wait_5_5, P_await_13_0, P_await_13_1, P_await_13_2, P_await_13_3, P_await_13_4, P_await_13_5, P_done_0_0, P_done_0_1, P_done_0_2, P_done_0_3, P_done_0_4, P_done_0_5, P_done_1_0, P_done_1_1, P_done_1_2, P_done_1_3, P_done_1_4, P_done_1_5, P_done_2_0, P_done_2_1, P_done_2_2, P_done_2_3, P_done_2_4, P_done_2_5, P_done_3_0, P_done_3_1, P_done_3_2, P_done_3_3, P_done_3_4, P_done_3_5, P_done_4_0, P_done_4_1, P_done_4_2, P_done_4_3, P_done_4_4, P_done_4_5, P_done_5_0, P_done_5_1, P_done_5_2, P_done_5_3, P_done_5_4, P_done_5_5, P_ifyi_15_0, P_ifyi_15_1, P_ifyi_15_2, P_ifyi_15_3, P_ifyi_15_4, P_ifyi_15_5, P_awaity_0, P_awaity_1, P_awaity_2, P_awaity_3, P_awaity_4, P_awaity_5, P_CS_21_0, P_CS_21_1, P_CS_21_2, P_CS_21_3, P_CS_21_4, P_CS_21_5, P_setbi_24_0, P_setbi_24_1, P_setbi_24_2, P_setbi_24_3, P_setbi_24_4, P_setbi_24_5]
[2023-03-22 02:40:09] [INFO ] Parsed PT model containing 174 places and 318 transitions and 1380 arcs in 121 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 21 ms.
Working with output stream class java.io.PrintStream
Deduced a syphon composed of 37 places in 2 ms
Reduce places removed 37 places and 58 transitions.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 378 ms. (steps per millisecond=26 ) properties (out of 7) seen :1
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 93 ms. (steps per millisecond=107 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-22 02:40:10] [INFO ] Flow matrix only has 200 transitions (discarded 60 similar events)
// Phase 1: matrix 200 rows 137 cols
[2023-03-22 02:40:10] [INFO ] Computed 37 place invariants in 13 ms
[2023-03-22 02:40:10] [INFO ] After 201ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0 real:2
[2023-03-22 02:40:10] [INFO ] [Nat]Absence check using 37 positive place invariants in 26 ms returned sat
[2023-03-22 02:40:10] [INFO ] After 103ms SMT Verify possible using all constraints in natural domain returned unsat :6 sat :0
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-15 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-13 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-07 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-06 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-05 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-03 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 6 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
All properties solved without resorting to model-checking.
Total runtime 1390 ms.
starting LoLA
BK_INPUT LamportFastMutEx-PT-5
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679453272918
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type SKEL/FNDP) for 21 LamportFastMutEx-PT-5-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SKEL/EQUN) for 21 LamportFastMutEx-PT-5-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 57 (type SKEL/SRCH) for 21 LamportFastMutEx-PT-5-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SKEL/SRCH) for 21 LamportFastMutEx-PT-5-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 1.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 25 (type CNST) for 24 LamportFastMutEx-PT-5-ReachabilityCardinality-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 28 (type CNST) for 27 LamportFastMutEx-PT-5-ReachabilityCardinality-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 25 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-08
lola: result : false
lola: FINISHED task # 28 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-09
lola: result : false
lola: Rule S: 58 transitions removed,37 places removed
lola: LAUNCH INITIAL
lola: LAUNCH task # 43 (type CNST) for 42 LamportFastMutEx-PT-5-ReachabilityCardinality-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 13 (type CNST) for 12 LamportFastMutEx-PT-5-ReachabilityCardinality-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 13 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-04
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: LAUNCH task # 4 (type CNST) for 3 LamportFastMutEx-PT-5-ReachabilityCardinality-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-53.sara.
FINISHED task # 43 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-14
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 4 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-01
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 LamportFastMutEx-PT-5-ReachabilityCardinality-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
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lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
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lola: fired transitions : 725718
lola: tried executions : 5957
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sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-117.sara.
sara: place or transition ordering is non-deterministic
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
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119 EF SRCH 4/257 3/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 763224 m, 152644 m/sec, 942423 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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lola: result : true
lola: fired transitions : 9
lola: tried executions : 1
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
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LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 10 0 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 7 2 0 0 0 1 0
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114 EF EXCL 14/719 3/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 701077 m, 48702 m/sec, 1043758 t fired, .
116 EF FNDP 14/318 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 2983385 t fired, 3 attempts, .
117 EF STEQ 14/318 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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116 EF FNDP 19/313 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 3901350 t fired, 4 attempts, .
117 EF STEQ 19/313 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 10 0 0 0 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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117 EF STEQ 24/308 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
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117 EF STEQ 29/303 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
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97 EF FNDP 25/279 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-06 5175645 t fired, 6 attempts, .
114 EF EXCL 34/719 7/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 1667298 m, 48123 m/sec, 2617501 t fired, .
116 EF FNDP 34/298 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 6597907 t fired, 7 attempts, .
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97 EF FNDP 30/274 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-06 6211657 t fired, 7 attempts, .
114 EF EXCL 39/719 8/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 1908471 m, 48234 m/sec, 3017861 t fired, .
116 EF FNDP 39/293 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 7491664 t fired, 8 attempts, .
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97 EF FNDP 35/269 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-06 7243859 t fired, 8 attempts, .
114 EF EXCL 44/719 9/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 2148079 m, 47921 m/sec, 3421108 t fired, .
116 EF FNDP 44/288 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 8382170 t fired, 9 attempts, .
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97 EF FNDP 40/264 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-06 8274082 t fired, 9 attempts, .
114 EF EXCL 49/719 10/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 2387259 m, 47836 m/sec, 3823478 t fired, .
116 EF FNDP 49/283 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 9272080 t fired, 10 attempts, .
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114 EF EXCL 54/719 11/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 2628440 m, 48236 m/sec, 4226111 t fired, .
116 EF FNDP 54/278 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 10157630 t fired, 11 attempts, .
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114 EF EXCL 59/719 12/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 2867087 m, 47729 m/sec, 4633495 t fired, .
116 EF FNDP 59/273 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 11056657 t fired, 12 attempts, .
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114 EF EXCL 65/719 13/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 3105269 m, 47636 m/sec, 5045449 t fired, .
116 EF FNDP 65/268 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 11953712 t fired, 12 attempts, .
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97 EF FNDP 61/243 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-06 12372507 t fired, 13 attempts, .
114 EF EXCL 70/719 13/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 3344042 m, 47754 m/sec, 5457976 t fired, .
116 EF FNDP 70/262 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 12853750 t fired, 13 attempts, .
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97 EF FNDP 66/238 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-06 13398467 t fired, 14 attempts, .
114 EF EXCL 75/719 14/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 3583138 m, 47819 m/sec, 5871622 t fired, .
116 EF FNDP 75/257 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 13754283 t fired, 14 attempts, .
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116 EF FNDP 80/252 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 14646335 t fired, 15 attempts, .
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116 EF FNDP 85/247 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 15526007 t fired, 16 attempts, .
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114 EF EXCL 105/719 20/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 5009377 m, 47272 m/sec, 8410629 t fired, .
116 EF FNDP 105/227 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 19038103 t fired, 20 attempts, .
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114 EF EXCL 110/719 21/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 5246542 m, 47433 m/sec, 8838778 t fired, .
116 EF FNDP 110/222 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 19914083 t fired, 20 attempts, .
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114 EF EXCL 115/719 22/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 5484436 m, 47578 m/sec, 9268026 t fired, .
116 EF FNDP 115/217 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 20790044 t fired, 21 attempts, .
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114 EF EXCL 120/719 23/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 5721083 m, 47329 m/sec, 9697229 t fired, .
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114 EF EXCL 125/719 23/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 5957480 m, 47279 m/sec, 10128804 t fired, .
116 EF FNDP 125/207 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 22543233 t fired, 23 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 10 0 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF 0 9 1 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
97 EF FNDP 151/153 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-06 30553267 t fired, 31 attempts, .
114 EF EXCL 160/719 30/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7612245 m, 46990 m/sec, 13193330 t fired, .
116 EF FNDP 160/172 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 28722058 t fired, 29 attempts, .
117 EF STEQ 160/172 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF 0 9 0 0 0 1 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
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114 EF EXCL 165/719 31/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7847377 m, 47026 m/sec, 13634903 t fired, .
116 EF FNDP 165/167 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 29612279 t fired, 30 attempts, .
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104 EF FNDP 5/312 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 1122633 t fired, 2 attempts, .
114 EF EXCL 170/719 32/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 8082242 m, 46973 m/sec, 14077263 t fired, .
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sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-98.sara.
sara: place or transition ordering is non-deterministic
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
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78 EF FNDP 5/428 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 3400231 t fired, 39498 attempts, .
85 EF FNDP 5/489 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 817258 t fired, 1 attempts, .
104 EF FNDP 10/485 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 1941926 t fired, 2 attempts, .
114 EF EXCL 175/899 32/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 8304741 m, 44499 m/sec, 14496008 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 9 1 0 0 0 0 0
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78 EF FNDP 10/423 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 6676917 t fired, 77210 attempts, .
85 EF FNDP 10/484 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 1610041 t fired, 2 attempts, .
104 EF FNDP 15/480 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 2714780 t fired, 3 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
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78 EF FNDP 15/418 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 9839885 t fired, 113784 attempts, .
85 EF FNDP 15/479 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 2369013 t fired, 3 attempts, .
89 EF EXCL 5/1139 2/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 262987 m, 52597 m/sec, 371788 t fired, .
104 EF FNDP 20/475 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 3459591 t fired, 4 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
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78 EF FNDP 20/413 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 12927773 t fired, 149830 attempts, .
85 EF FNDP 20/474 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 3111198 t fired, 4 attempts, .
89 EF EXCL 10/1139 3/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 509863 m, 49375 m/sec, 745713 t fired, .
104 EF FNDP 25/470 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 4184202 t fired, 5 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 9 1 0 0 0 0 0
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
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78 EF FNDP 25/408 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 15950057 t fired, 184917 attempts, .
85 EF FNDP 25/469 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 3838518 t fired, 4 attempts, .
89 EF EXCL 15/1139 3/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 750319 m, 48091 m/sec, 1117084 t fired, .
104 EF FNDP 30/465 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 4894946 t fired, 5 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
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78 EF FNDP 30/403 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 18911513 t fired, 219333 attempts, .
85 EF FNDP 30/464 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 4549788 t fired, 5 attempts, .
89 EF EXCL 20/1139 4/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 987936 m, 47523 m/sec, 1490735 t fired, .
104 EF FNDP 35/460 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 5594870 t fired, 6 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
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78 EF FNDP 35/398 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 21829446 t fired, 253424 attempts, .
85 EF FNDP 35/459 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 5254438 t fired, 6 attempts, .
89 EF EXCL 25/1139 5/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 1223968 m, 47206 m/sec, 1864438 t fired, .
104 EF FNDP 40/455 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 6289585 t fired, 7 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
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LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 2 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 5 1 0 3 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
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78 EF FNDP 210/223 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 119405894 t fired, 1391308 attempts, .
85 EF FNDP 210/284 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 29625136 t fired, 30 attempts, .
104 EF FNDP 215/280 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 29044972 t fired, 30 attempts, .
108 EF EXCL 10/1614 4/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 811799 m, 78361 m/sec, 1278082 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 2 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 5 1 0 3 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
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78 EF FNDP 215/218 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 122209629 t fired, 1424271 attempts, .
85 EF FNDP 215/279 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 30310278 t fired, 31 attempts, .
104 EF FNDP 220/275 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 29698434 t fired, 30 attempts, .
108 EF EXCL 15/1614 5/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 1194074 m, 76455 m/sec, 1923316 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 2 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 5 0 0 3 1 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
85 EF FNDP 220/274 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 30996220 t fired, 31 attempts, .
104 EF FNDP 225/270 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 30352579 t fired, 31 attempts, .
108 EF EXCL 20/1614 7/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 1568602 m, 74905 m/sec, 2581520 t fired, .
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lola: LAUNCH task # 79 (type SKEL/EQUN) for 15 LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 78 (type SKEL/FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: result : unknown
lola: fired transitions : 125010227
lola: tried executions : 1457018
lola: time used : 220.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-79.sara.
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 2 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
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79 EF STEQ 5/458 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 225/269 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 31951337 t fired, 32 attempts, .
104 EF FNDP 230/265 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 31256359 t fired, 32 attempts, .
108 EF EXCL 25/1614 8/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 1919397 m, 70159 m/sec, 3204679 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 2 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 EF STEQ 10/453 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 230/264 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 32918810 t fired, 33 attempts, .
104 EF FNDP 235/260 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 32171087 t fired, 33 attempts, .
108 EF EXCL 30/1614 9/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 2280988 m, 72318 m/sec, 3855503 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 2 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 EF STEQ 15/448 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 235/259 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 33886961 t fired, 34 attempts, .
104 EF FNDP 240/255 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 33087429 t fired, 34 attempts, .
108 EF EXCL 35/1614 11/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 2637685 m, 71339 m/sec, 4506751 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 2 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 EF STEQ 20/443 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 240/254 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 34853930 t fired, 35 attempts, .
104 EF FNDP 245/250 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-03 34001832 t fired, 35 attempts, .
108 EF EXCL 40/1614 12/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 2997080 m, 71879 m/sec, 5158961 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 0 1 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
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79 EF STEQ 25/438 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 245/249 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 35822474 t fired, 36 attempts, .
108 EF EXCL 45/1614 13/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 3354254 m, 71434 m/sec, 5810131 t fired, .
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lola: time limit : 32000000 sec
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lola: FINISHED task # 104 (type FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 34914899
lola: tried executions : 36
lola: time used : 250.000000
lola: memory pages used : 0
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
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79 EF STEQ 30/433 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 250/326 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 36828796 t fired, 37 attempts, .
108 EF EXCL 50/1614 15/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 3708840 m, 70917 m/sec, 6461147 t fired, .
110 EF FNDP 5/454 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 1029009 t fired, 2 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 1 0 0 0
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
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79 EF STEQ 35/428 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 255/321 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 37823925 t fired, 38 attempts, .
108 EF EXCL 55/1614 16/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 4060490 m, 70330 m/sec, 7116517 t fired, .
110 EF FNDP 10/449 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 2036248 t fired, 3 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 1 0 0 0
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
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79 EF STEQ 40/423 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 260/316 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 38811381 t fired, 39 attempts, .
108 EF EXCL 60/1614 17/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 4410092 m, 69920 m/sec, 7766595 t fired, .
110 EF FNDP 15/444 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 3038507 t fired, 4 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 EF STEQ 45/418 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 265/311 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 39793695 t fired, 40 attempts, .
108 EF EXCL 65/1614 19/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 4760641 m, 70109 m/sec, 8427150 t fired, .
110 EF FNDP 20/439 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 4035202 t fired, 5 attempts, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 EF STEQ 50/413 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 270/306 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 40772623 t fired, 41 attempts, .
108 EF EXCL 70/1614 20/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 5106080 m, 69087 m/sec, 9087404 t fired, .
110 EF FNDP 25/434 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 5028875 t fired, 6 attempts, .
Time elapsed: 441 secs. Pages in use: 33
# running tasks: 4 of 4 Visible: 16
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 EF STEQ 55/408 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 275/301 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 41750532 t fired, 42 attempts, .
108 EF EXCL 75/1614 21/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 5451839 m, 69151 m/sec, 9748693 t fired, .
110 EF FNDP 30/429 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 6018374 t fired, 7 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 EF STEQ 60/403 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 280/296 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 42727103 t fired, 43 attempts, .
108 EF EXCL 80/1614 23/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 5795733 m, 68778 m/sec, 10414700 t fired, .
110 EF FNDP 35/424 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7004166 t fired, 8 attempts, .
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# running tasks: 4 of 4 Visible: 16
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 EF STEQ 65/398 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
85 EF FNDP 285/291 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 43703385 t fired, 44 attempts, .
108 EF EXCL 85/1614 24/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 6139877 m, 68828 m/sec, 11081612 t fired, .
110 EF FNDP 40/419 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7990339 t fired, 8 attempts, .
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# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 85 (type FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-15 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 0 0 1 1 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
79 EF STEQ 70/393 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
108 EF EXCL 90/1614 25/32 LamportFastMutEx-PT-5-ReachabilityCardinality-03 6483119 m, 68648 m/sec, 11744848 t fired, .
110 EF FNDP 45/414 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 8976150 t fired, 9 attempts, .
Time elapsed: 461 secs. Pages in use: 33
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 86 (type EQUN) for 45 LamportFastMutEx-PT-5-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-15
lola: result : unknown
lola: fired transitions : 44679479
lola: tried executions : 46
lola: time used : 290.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-86.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 86 (type EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-15
lola: result : false
lola: LAUNCH task # 105 (type EQUN) for 9 LamportFastMutEx-PT-5-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-105.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 105 (type EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 108 (type EXCL) for LamportFastMutEx-PT-5-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 120 (type EXCL) for 15 LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: time limit : 3139 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 82 (type SKEL/SRCH) for 15 LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 82 (type SKEL/SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: result : false
lola: markings : 153589
lola: fired transitions : 499267
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 79 (type EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 120 (type EXCL) for LamportFastMutEx-PT-5-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 111 (type EQUN) for 39 LamportFastMutEx-PT-5-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type SRCH) for 39 LamportFastMutEx-PT-5-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 115 (type SRCH) for 39 LamportFastMutEx-PT-5-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 79 (type SKEL/EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: result : unknown
lola: FINISHED task # 115 (type SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-111.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 111 (type EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-13
lola: result : false
lola: CANCELED task # 110 (type FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 113 (type SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-13 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG true state equation
Time elapsed: 461 secs. Pages in use: 33
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-5"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LamportFastMutEx-PT-5, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416000422"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-5.tgz
mv LamportFastMutEx-PT-5 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;