Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-tall-167856415900354.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LamportFastMutEx-COL-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856415900354
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 536K
-rw-r--r-- 1 mcc users 8.8K Feb 25 13:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 25 13:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Feb 25 13:39 CTLFireability.txt
-rw-r--r-- 1 mcc users 36K Feb 25 13:39 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 25 13:44 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 174K Feb 25 13:44 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.0K Feb 25 13:43 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 13:43 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 40K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-00
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-01
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-02
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-03
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-04
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-05
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-06
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-07
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-08
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-09
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-10
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-11
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-12
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-13
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-14
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679445375882

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-COL-4
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 00:36:17] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 00:36:17] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 00:36:17] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-22 00:36:17] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-22 00:36:17] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 436 ms
[2023-03-22 00:36:17] [INFO ] Imported 18 HL places and 17 HL transitions for a total of 135 PT places and 285.0 transition bindings in 163 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
[2023-03-22 00:36:17] [INFO ] Built PT skeleton of HLPN with 18 places and 17 transitions 68 arcs in 4 ms.
[2023-03-22 00:36:17] [INFO ] Skeletonized 9 HLPN properties in 2 ms. Removed 7 properties that had guard overlaps.
Computed a total of 3 stabilizing places and 0 stable transitions
Remains 6 properties that can be checked using skeleton over-approximation.
Reduce places removed 3 places and 0 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 938 steps, including 0 resets, run visited all 9 properties in 29 ms. (steps per millisecond=32 )
[2023-03-22 00:36:18] [INFO ] Flatten gal took : 14 ms
[2023-03-22 00:36:18] [INFO ] Flatten gal took : 2 ms
Domain [pid(5), pid(5)] of place P_wait breaks symmetries in sort pid
Symmetric sort wr.t. initial and guards and successors and join/free detected :P_bool
Arc [3:1*[$i, 1]] contains constants of sort P_bool
Transition T_setbi_2 : constants on arcs in [[3:1*[$i, 1]]] introduces in P_bool(2) partition with 1 elements that refines current partition to 2 subsets.
[2023-03-22 00:36:18] [INFO ] Unfolded HLPN to a Petri net with 135 places and 230 transitions 990 arcs in 15 ms.
[2023-03-22 00:36:18] [INFO ] Unfolded 16 HLPN properties in 1 ms.
Deduced a syphon composed of 33 places in 1 ms
Reduce places removed 33 places and 50 transitions.
Support contains 102 out of 102 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 6 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
[2023-03-22 00:36:18] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
// Phase 1: matrix 144 rows 102 cols
[2023-03-22 00:36:18] [INFO ] Computed 26 place invariants in 14 ms
[2023-03-22 00:36:18] [INFO ] Implicit Places using invariants in 171 ms returned []
[2023-03-22 00:36:18] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 00:36:18] [INFO ] Invariant cache hit.
[2023-03-22 00:36:18] [INFO ] State equation strengthened by 40 read => feed constraints.
[2023-03-22 00:36:18] [INFO ] Implicit Places using invariants and state equation in 120 ms returned []
Implicit Place search using SMT with State Equation took 314 ms to find 0 implicit places.
[2023-03-22 00:36:18] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 00:36:18] [INFO ] Invariant cache hit.
[2023-03-22 00:36:18] [INFO ] Dead Transitions using invariants and state equation in 109 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 432 ms. Remains : 102/102 places, 180/180 transitions.
Support contains 102 out of 102 places after structural reductions.
[2023-03-22 00:36:18] [INFO ] Flatten gal took : 24 ms
[2023-03-22 00:36:18] [INFO ] Flatten gal took : 28 ms
[2023-03-22 00:36:18] [INFO ] Input system was already deterministic with 180 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 149 ms. (steps per millisecond=67 ) properties (out of 36) seen :35
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-22 00:36:19] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 00:36:19] [INFO ] Invariant cache hit.
[2023-03-22 00:36:19] [INFO ] [Real]Absence check using 26 positive place invariants in 8 ms returned sat
[2023-03-22 00:36:19] [INFO ] After 127ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-22 00:36:19] [INFO ] [Nat]Absence check using 26 positive place invariants in 5 ms returned sat
[2023-03-22 00:36:19] [INFO ] After 50ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-22 00:36:19] [INFO ] State equation strengthened by 40 read => feed constraints.
[2023-03-22 00:36:19] [INFO ] After 30ms SMT Verify possible using 40 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-22 00:36:19] [INFO ] After 64ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 27 ms.
[2023-03-22 00:36:19] [INFO ] After 188ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 3 ms.
Support contains 33 out of 102 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 12 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 12 ms. Remains : 102/102 places, 180/180 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 1689636 steps, run timeout after 3001 ms. (steps per millisecond=563 ) properties seen :{}
Probabilistic random walk after 1689636 steps, saw 394039 distinct states, run finished after 3002 ms. (steps per millisecond=562 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-22 00:36:22] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 00:36:22] [INFO ] Invariant cache hit.
[2023-03-22 00:36:22] [INFO ] [Real]Absence check using 26 positive place invariants in 5 ms returned sat
[2023-03-22 00:36:22] [INFO ] After 166ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-22 00:36:22] [INFO ] [Nat]Absence check using 26 positive place invariants in 7 ms returned sat
[2023-03-22 00:36:22] [INFO ] After 49ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-22 00:36:22] [INFO ] State equation strengthened by 40 read => feed constraints.
[2023-03-22 00:36:22] [INFO ] After 29ms SMT Verify possible using 40 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-22 00:36:22] [INFO ] After 65ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 31 ms.
[2023-03-22 00:36:22] [INFO ] After 193ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 33 out of 102 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 9 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10 ms. Remains : 102/102 places, 180/180 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 7 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
[2023-03-22 00:36:23] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 00:36:23] [INFO ] Invariant cache hit.
[2023-03-22 00:36:23] [INFO ] Implicit Places using invariants in 74 ms returned []
[2023-03-22 00:36:23] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 00:36:23] [INFO ] Invariant cache hit.
[2023-03-22 00:36:23] [INFO ] State equation strengthened by 40 read => feed constraints.
[2023-03-22 00:36:23] [INFO ] Implicit Places using invariants and state equation in 140 ms returned []
Implicit Place search using SMT with State Equation took 217 ms to find 0 implicit places.
[2023-03-22 00:36:23] [INFO ] Redundant transitions in 6 ms returned []
[2023-03-22 00:36:23] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 00:36:23] [INFO ] Invariant cache hit.
[2023-03-22 00:36:23] [INFO ] Dead Transitions using invariants and state equation in 108 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 349 ms. Remains : 102/102 places, 180/180 transitions.
Ensure Unique test removed 36 transitions
Reduce isomorphic transitions removed 36 transitions.
Iterating post reduction 0 with 36 rules applied. Total rules applied 36 place count 102 transition count 144
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 1 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 1 with 16 rules applied. Total rules applied 52 place count 94 transition count 136
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 56 place count 90 transition count 128
Iterating global reduction 1 with 4 rules applied. Total rules applied 60 place count 90 transition count 128
Partial Free-agglomeration rule applied 4 times.
Drop transitions removed 4 transitions
Iterating global reduction 1 with 4 rules applied. Total rules applied 64 place count 90 transition count 128
Applied a total of 64 rules in 23 ms. Remains 90 /102 variables (removed 12) and now considering 128/180 (removed 52) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 128 rows 90 cols
[2023-03-22 00:36:23] [INFO ] Computed 26 place invariants in 2 ms
[2023-03-22 00:36:23] [INFO ] [Real]Absence check using 26 positive place invariants in 4 ms returned sat
[2023-03-22 00:36:23] [INFO ] After 88ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-22 00:36:23] [INFO ] [Nat]Absence check using 26 positive place invariants in 4 ms returned sat
[2023-03-22 00:36:23] [INFO ] After 43ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-22 00:36:23] [INFO ] After 69ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 19 ms.
[2023-03-22 00:36:23] [INFO ] After 117ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
[2023-03-22 00:36:23] [INFO ] Flatten gal took : 14 ms
[2023-03-22 00:36:23] [INFO ] Flatten gal took : 24 ms
[2023-03-22 00:36:23] [INFO ] Input system was already deterministic with 180 transitions.
Computed a total of 1 stabilizing places and 4 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 3 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:23] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:36:23] [INFO ] Flatten gal took : 13 ms
[2023-03-22 00:36:23] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 6 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:23] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:36:23] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:36:23] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 1 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:23] [INFO ] Flatten gal took : 13 ms
[2023-03-22 00:36:23] [INFO ] Flatten gal took : 10 ms
[2023-03-22 00:36:23] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 2 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 18 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 5 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 7 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 1 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 1 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 7 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 98 transition count 176
Applied a total of 8 rules in 9 ms. Remains 98 /102 variables (removed 4) and now considering 176/180 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 98/102 places, 176/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 98 transition count 176
Applied a total of 8 rules in 17 ms. Remains 98 /102 variables (removed 4) and now considering 176/180 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 98/102 places, 176/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 7 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 12 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 7 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 5 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 98 transition count 176
Applied a total of 8 rules in 8 ms. Remains 98 /102 variables (removed 4) and now considering 176/180 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 98/102 places, 176/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 7 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 7 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 98 transition count 176
Applied a total of 8 rules in 7 ms. Remains 98 /102 variables (removed 4) and now considering 176/180 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 98/102 places, 176/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 1 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 5 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 0 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 98 transition count 176
Applied a total of 8 rules in 6 ms. Remains 98 /102 variables (removed 4) and now considering 176/180 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 98/102 places, 176/180 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 6 ms
[2023-03-22 00:36:24] [INFO ] Input system was already deterministic with 176 transitions.
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 13 ms
[2023-03-22 00:36:24] [INFO ] Flatten gal took : 12 ms
[2023-03-22 00:36:24] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 11 ms.
[2023-03-22 00:36:24] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 102 places, 180 transitions and 768 arcs took 1 ms.
Total runtime 7427 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT LamportFastMutEx-COL-4
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA LamportFastMutEx-COL-4-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-4-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679445457853

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 14 (type EXCL) for 13 LamportFastMutEx-COL-4-CTLFireability-03
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: LAUNCH task # 74 (type FNDP) for 53 LamportFastMutEx-COL-4-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 53 LamportFastMutEx-COL-4-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SRCH) for 53 LamportFastMutEx-COL-4-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 77 (type SRCH) for LamportFastMutEx-COL-4-CTLFireability-15
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 72 (type FNDP) for 53 LamportFastMutEx-COL-4-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:742
lola: FINISHED task # 74 (type FNDP) for LamportFastMutEx-COL-4-CTLFireability-15
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 72 (type FNDP) for LamportFastMutEx-COL-4-CTLFireability-15
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: CANCELED task # 75 (type EQUN) for LamportFastMutEx-COL-4-CTLFireability-15 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: try reading problem file /home/mcc/execution/373/CTLFireability-75.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 95 (type SRCH) for 0 LamportFastMutEx-COL-4-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type FNDP) for 0 LamportFastMutEx-COL-4-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 91 (type EQUN) for 0 LamportFastMutEx-COL-4-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 95 (type SRCH) for LamportFastMutEx-COL-4-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 85 (type FNDP) for LamportFastMutEx-COL-4-CTLFireability-00
lola: result : true
lola: fired transitions : 2972
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 91 (type EQUN) for LamportFastMutEx-COL-4-CTLFireability-00 (obsolete)
sara: try reading problem file /home/mcc/execution/373/CTLFireability-91.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 75 (type EQUN) for LamportFastMutEx-COL-4-CTLFireability-15
lola: result : true
lola: FINISHED task # 14 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-03
lola: result : false
lola: markings : 316120
lola: fired transitions : 1156844
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 51 (type EXCL) for 50 LamportFastMutEx-COL-4-CTLFireability-14
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-14
lola: result : true
lola: markings : 12
lola: fired transitions : 49
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 LamportFastMutEx-COL-4-CTLFireability-13
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-13
lola: result : true
lola: markings : 626
lola: fired transitions : 1482
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 LamportFastMutEx-COL-4-CTLFireability-06
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-06
lola: result : false
lola: markings : 3234
lola: fired transitions : 11984
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 LamportFastMutEx-COL-4-CTLFireability-05
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-05
lola: result : true
lola: markings : 3302
lola: fired transitions : 15317
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 LamportFastMutEx-COL-4-CTLFireability-04
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-04
lola: result : false
lola: markings : 432
lola: fired transitions : 782
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 LamportFastMutEx-COL-4-CTLFireability-02
lola: time limit : 399 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 4/399 3/32 LamportFastMutEx-COL-4-CTLFireability-02 471323 m, 94264 m/sec, 3249718 t fired, .

Time elapsed: 6 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 9/399 4/32 LamportFastMutEx-COL-4-CTLFireability-02 860763 m, 77888 m/sec, 7861013 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 14/399 6/32 LamportFastMutEx-COL-4-CTLFireability-02 1231997 m, 74246 m/sec, 12564252 t fired, .

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LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 19/399 7/32 LamportFastMutEx-COL-4-CTLFireability-02 1621820 m, 77964 m/sec, 17304061 t fired, .

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lola: FINISHED task # 11 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-02
lola: result : true
lola: markings : 1914784
lola: fired transitions : 20384715
lola: time used : 22.000000
lola: memory pages used : 9
lola: LAUNCH task # 93 (type EXCL) for 31 LamportFastMutEx-COL-4-CTLFireability-09
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 93 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-09
lola: result : true
lola: markings : 63
lola: fired transitions : 63
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 LamportFastMutEx-COL-4-CTLFireability-12
lola: time limit : 595 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 EFAGEF EXCL 1/595 2/32 LamportFastMutEx-COL-4-CTLFireability-12 416364 m, 83272 m/sec, 1289278 t fired, .

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LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 EFAGEF EXCL 6/595 6/32 LamportFastMutEx-COL-4-CTLFireability-12 1480183 m, 212763 m/sec, 6180851 t fired, .

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lola: FINISHED task # 45 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-12
lola: result : true
lola: markings : 1672714
lola: fired transitions : 7309146
lola: time used : 7.000000
lola: memory pages used : 7
lola: LAUNCH task # 29 (type EXCL) for 28 LamportFastMutEx-COL-4-CTLFireability-08
lola: time limit : 713 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-08: AGEF 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 AGEF EXCL 4/713 4/32 LamportFastMutEx-COL-4-CTLFireability-08 828944 m, 165788 m/sec, 2087215 t fired, .

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lola: FINISHED task # 29 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-08
lola: result : true
lola: markings : 1037424
lola: fired transitions : 2996747
lola: time used : 5.000000
lola: memory pages used : 5
lola: LAUNCH task # 26 (type EXCL) for 25 LamportFastMutEx-COL-4-CTLFireability-07
lola: time limit : 890 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-08: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-07: AGEF 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 AGEF EXCL 4/890 3/32 LamportFastMutEx-COL-4-CTLFireability-07 736735 m, 147347 m/sec, 1748643 t fired, .

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lola: FINISHED task # 26 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-07
lola: result : true
lola: markings : 1125026
lola: fired transitions : 3229719
lola: time used : 7.000000
lola: memory pages used : 5
lola: LAUNCH task # 42 (type EXCL) for 41 LamportFastMutEx-COL-4-CTLFireability-11
lola: time limit : 1185 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-11
lola: result : true
lola: markings : 183
lola: fired transitions : 1080
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 LamportFastMutEx-COL-4-CTLFireability-10
lola: time limit : 1778 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-07: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-08: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 2/1778 2/32 LamportFastMutEx-COL-4-CTLFireability-10 396413 m, 79282 m/sec, 2194758 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-07: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-08: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 7/1778 5/32 LamportFastMutEx-COL-4-CTLFireability-10 1055832 m, 131883 m/sec, 6899721 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-07: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-08: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-4-CTLFireability-10: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 12/1778 8/32 LamportFastMutEx-COL-4-CTLFireability-10 1679352 m, 124704 m/sec, 11548297 t fired, .

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lola: FINISHED task # 39 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-10
lola: result : true
lola: markings : 1914784
lola: fired transitions : 13419849
lola: time used : 14.000000
lola: memory pages used : 9
lola: LAUNCH task # 8 (type EXCL) for 7 LamportFastMutEx-COL-4-CTLFireability-01
lola: time limit : 3542 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-07: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-08: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 3/3542 2/32 LamportFastMutEx-COL-4-CTLFireability-01 433971 m, 86794 m/sec, 2488198 t fired, .

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sara: warning, failure of lp_solve (at job 39283)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-07: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-08: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 8/3542 5/32 LamportFastMutEx-COL-4-CTLFireability-01 1103749 m, 133955 m/sec, 7138403 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-07: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-08: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-4-CTLFireability-01: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 13/3542 8/32 LamportFastMutEx-COL-4-CTLFireability-01 1785623 m, 136374 m/sec, 11750279 t fired, .

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lola: FINISHED task # 8 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-01
lola: result : false
lola: markings : 1914784
lola: fired transitions : 12796716
lola: time used : 14.000000
lola: memory pages used : 9
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-COL-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-COL-4-CTLFireability-07: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-08: AGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-09: CONJ false state space / EG
LamportFastMutEx-COL-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-12: EFAGEF true tscc_search
LamportFastMutEx-COL-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-4-CTLFireability-15: DISJ true findpath


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LamportFastMutEx-COL-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856415900354"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-4.tgz
mv LamportFastMutEx-COL-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;