Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-tall-167856415800226.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is JoinFreeModules-PT-5000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856415800226
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 17M
-rw-r--r-- 1 mcc users 7.0K Feb 25 12:18 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K Feb 25 12:18 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 25 12:07 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 25 12:07 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 16:18 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 16:18 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:18 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:18 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 12:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 106K Feb 25 12:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 12:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 93K Feb 25 12:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:18 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:18 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 16M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-00
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-01
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-02
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-03
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-04
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-05
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-06
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-07
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-08
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-09
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-10
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-11
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-12
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-13
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-14
FORMULA_NAME JoinFreeModules-PT-5000-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679440894196

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=JoinFreeModules-PT-5000
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-21 23:21:35] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-21 23:21:35] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-21 23:21:36] [INFO ] Load time of PNML (sax parser for PT used): 992 ms
[2023-03-21 23:21:36] [INFO ] Transformed 25001 places.
[2023-03-21 23:21:36] [INFO ] Transformed 40001 transitions.
[2023-03-21 23:21:36] [INFO ] Parsed PT model containing 25001 places and 40001 transitions and 115002 arcs in 1194 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 28 ms.
Initial state reduction rules removed 4 formulas.
Reduce places removed 1 places and 0 transitions.
FORMULA JoinFreeModules-PT-5000-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA JoinFreeModules-PT-5000-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA JoinFreeModules-PT-5000-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA JoinFreeModules-PT-5000-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 117 out of 25000 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 7488 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
// Phase 1: matrix 40001 rows 25000 cols
[2023-03-21 23:21:44] [INFO ] Computed 5000 place invariants in 208 ms
[2023-03-21 23:21:47] [INFO ] Dead Transitions using invariants and state equation in 2654 ms found 0 transitions.
[2023-03-21 23:21:47] [INFO ] Invariant cache hit.
[2023-03-21 23:21:53] [INFO ] Implicit Places using invariants in 6299 ms returned []
Implicit Place search using SMT only with invariants took 6303 ms to find 0 implicit places.
[2023-03-21 23:21:53] [INFO ] Invariant cache hit.
[2023-03-21 23:21:55] [INFO ] Dead Transitions using invariants and state equation in 2064 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18549 ms. Remains : 25000/25000 places, 40001/40001 transitions.
Support contains 117 out of 25000 places after structural reductions.
[2023-03-21 23:21:57] [INFO ] Flatten gal took : 1233 ms
[2023-03-21 23:21:58] [INFO ] Flatten gal took : 912 ms
[2023-03-21 23:22:00] [INFO ] Input system was already deterministic with 40001 transitions.
Incomplete random walk after 10003 steps, including 1 resets, run finished after 2163 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 208 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 204 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 314 ms. (steps per millisecond=3 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 256 ms. (steps per millisecond=3 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 255 ms. (steps per millisecond=3 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 293 ms. (steps per millisecond=3 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 201 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 228 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 260 ms. (steps per millisecond=3 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 249 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 252 ms. (steps per millisecond=3 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 248 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 246 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 200 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 215 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 199 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 208 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 199 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 199 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 200 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 201 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 220 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 203 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 204 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 199 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 198 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 200 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 199 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 198 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 216 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 203 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 204 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 203 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 203 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 201 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 221 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 201 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 202 ms. (steps per millisecond=4 ) properties (out of 87) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 200 ms. (steps per millisecond=5 ) properties (out of 87) seen :0
Probabilistic random walk after 80018 steps, saw 79966 distinct states, run finished after 58223 ms. (steps per millisecond=1 ) properties seen :15
Running SMT prover for 72 properties.
[2023-03-21 23:23:12] [INFO ] Invariant cache hit.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.assertInvariants(DeadlockTester.java:2340)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:618)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-21 23:23:38] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-21 23:23:38] [INFO ] After 26122ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 72 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 2 ms.
Support contains 94 out of 25000 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Graph (complete) has 60000 edges and 25000 vertex of which 465 are kept as prefixes of interest. Removing 24535 places using SCC suffix rule.102 ms
Discarding 24535 places :
Also discarding 39256 output transitions
Drop transitions removed 39256 transitions
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 465 transition count 744
Applied a total of 2 rules in 1883 ms. Remains 465 /25000 variables (removed 24535) and now considering 744/40001 (removed 39257) transitions.
// Phase 1: matrix 744 rows 465 cols
[2023-03-21 23:23:40] [INFO ] Computed 93 place invariants in 3 ms
[2023-03-21 23:23:41] [INFO ] Dead Transitions using invariants and state equation in 769 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2655 ms. Remains : 465/25000 places, 744/40001 transitions.
[2023-03-21 23:23:42] [INFO ] Flatten gal took : 1109 ms
[2023-03-21 23:23:43] [INFO ] Flatten gal took : 745 ms
[2023-03-21 23:23:45] [INFO ] Input system was already deterministic with 40001 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 7159 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
// Phase 1: matrix 40001 rows 25000 cols
[2023-03-21 23:24:01] [INFO ] Computed 5000 place invariants in 136 ms
[2023-03-21 23:24:03] [INFO ] Dead Transitions using invariants and state equation in 2249 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9410 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:24:04] [INFO ] Flatten gal took : 694 ms
[2023-03-21 23:24:05] [INFO ] Flatten gal took : 775 ms
[2023-03-21 23:24:07] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 6926 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:24:14] [INFO ] Invariant cache hit.
[2023-03-21 23:24:16] [INFO ] Dead Transitions using invariants and state equation in 2037 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8977 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:24:17] [INFO ] Flatten gal took : 748 ms
[2023-03-21 23:24:17] [INFO ] Flatten gal took : 840 ms
[2023-03-21 23:24:19] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 7318 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:24:27] [INFO ] Invariant cache hit.
[2023-03-21 23:24:29] [INFO ] Dead Transitions using invariants and state equation in 2060 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9388 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:24:29] [INFO ] Flatten gal took : 691 ms
[2023-03-21 23:24:30] [INFO ] Flatten gal took : 778 ms
[2023-03-21 23:24:32] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 3453 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:24:35] [INFO ] Invariant cache hit.
[2023-03-21 23:24:37] [INFO ] Dead Transitions using invariants and state equation in 1931 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5387 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:24:38] [INFO ] Flatten gal took : 780 ms
[2023-03-21 23:24:39] [INFO ] Flatten gal took : 800 ms
[2023-03-21 23:24:40] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 6197 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:24:47] [INFO ] Invariant cache hit.
[2023-03-21 23:24:49] [INFO ] Dead Transitions using invariants and state equation in 2038 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8241 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:24:50] [INFO ] Flatten gal took : 728 ms
[2023-03-21 23:24:50] [INFO ] Flatten gal took : 749 ms
[2023-03-21 23:24:52] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 5828 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:24:58] [INFO ] Invariant cache hit.
[2023-03-21 23:25:00] [INFO ] Dead Transitions using invariants and state equation in 1945 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7787 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:25:00] [INFO ] Flatten gal took : 722 ms
[2023-03-21 23:25:01] [INFO ] Flatten gal took : 816 ms
[2023-03-21 23:25:03] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 6472 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:25:09] [INFO ] Invariant cache hit.
[2023-03-21 23:25:11] [INFO ] Dead Transitions using invariants and state equation in 1993 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8473 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:25:12] [INFO ] Flatten gal took : 684 ms
[2023-03-21 23:25:13] [INFO ] Flatten gal took : 729 ms
[2023-03-21 23:25:14] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 7205 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:25:22] [INFO ] Invariant cache hit.
[2023-03-21 23:25:24] [INFO ] Dead Transitions using invariants and state equation in 1976 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9200 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:25:24] [INFO ] Flatten gal took : 696 ms
[2023-03-21 23:25:25] [INFO ] Flatten gal took : 748 ms
[2023-03-21 23:25:27] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 5869 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:25:33] [INFO ] Invariant cache hit.
[2023-03-21 23:25:35] [INFO ] Dead Transitions using invariants and state equation in 1940 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7826 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:25:35] [INFO ] Flatten gal took : 681 ms
[2023-03-21 23:25:36] [INFO ] Flatten gal took : 723 ms
[2023-03-21 23:25:38] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 6172 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:25:44] [INFO ] Invariant cache hit.
[2023-03-21 23:25:46] [INFO ] Dead Transitions using invariants and state equation in 1974 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8158 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:25:47] [INFO ] Flatten gal took : 697 ms
[2023-03-21 23:25:47] [INFO ] Flatten gal took : 736 ms
[2023-03-21 23:25:49] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 3619 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:25:52] [INFO ] Invariant cache hit.
[2023-03-21 23:25:54] [INFO ] Dead Transitions using invariants and state equation in 1936 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5556 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:25:55] [INFO ] Flatten gal took : 689 ms
[2023-03-21 23:25:56] [INFO ] Flatten gal took : 733 ms
[2023-03-21 23:25:57] [INFO ] Input system was already deterministic with 40001 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25000/25000 places, 40001/40001 transitions.
Applied a total of 0 rules in 5558 ms. Remains 25000 /25000 variables (removed 0) and now considering 40001/40001 (removed 0) transitions.
[2023-03-21 23:26:03] [INFO ] Invariant cache hit.
[2023-03-21 23:26:05] [INFO ] Dead Transitions using invariants and state equation in 1889 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7466 ms. Remains : 25000/25000 places, 40001/40001 transitions.
[2023-03-21 23:26:06] [INFO ] Flatten gal took : 674 ms
[2023-03-21 23:26:06] [INFO ] Flatten gal took : 722 ms
[2023-03-21 23:26:08] [INFO ] Input system was already deterministic with 40001 transitions.
[2023-03-21 23:26:08] [INFO ] Flatten gal took : 705 ms
[2023-03-21 23:26:09] [INFO ] Flatten gal took : 734 ms
[2023-03-21 23:26:09] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-21 23:26:09] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 25000 places, 40001 transitions and 115000 arcs took 185 ms.
Total runtime 274250 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT JoinFreeModules-PT-5000
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

BK_STOP 1679442308341

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 2/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 381227 m, 76245 m/sec, 381573 t fired, .

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lola: memory limit: 5 pages
lola: RELEASE
lola: FINISHED task # 54 (type SKEL/SRCH) for JoinFreeModules-PT-5000-CTLFireability-09
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 7/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 1314185 m, 186591 m/sec, 1315386 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 12/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 2294546 m, 196072 m/sec, 2296638 t fired, .

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lola: RELEASE
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 17/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 3218317 m, 184754 m/sec, 3221250 t fired, .

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lola: LAUNCH task # 57 (type SKEL/FNDP) for 22 JoinFreeModules-PT-5000-CTLFireability-09
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lola: FINISHED task # 59 (type SKEL/SRCH) for JoinFreeModules-PT-5000-CTLFireability-09
lola: result : true
lola: markings : 9
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 57 (type FNDP) for JoinFreeModules-PT-5000-CTLFireability-09 (obsolete)
lola: CANCELED task # 58 (type EQUN) for JoinFreeModules-PT-5000-CTLFireability-09 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 2 0 0 3
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 22/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 4167956 m, 189927 m/sec, 4171757 t fired, .

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lola: tried executions : 1
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lola: memory pages used : 0
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JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 4 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 27/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 4200700 m, 6548 m/sec, 4204528 t fired, .

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JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 4 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 32/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 5194583 m, 198776 m/sec, 5199319 t fired, .

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JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 4 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 38/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 6260140 m, 213111 m/sec, 6265852 t fired, .

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lola: result : false
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lola: memory pages used : 1
lola: Created skeleton in 3.000000 secs.
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 5 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 43/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 7199226 m, 187817 m/sec, 7205796 t fired, .

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JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 5 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 48/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 7948810 m, 149916 m/sec, 7956058 t fired, .

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JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 5 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 53/2766 1/5 JoinFreeModules-PT-5000-CTLFireability-09 9154970 m, 241232 m/sec, 9163319 t fired, .

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JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 5 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 58/2766 2/5 JoinFreeModules-PT-5000-CTLFireability-09 10349975 m, 239001 m/sec, 10359419 t fired, .

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JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 5 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 63/2766 2/5 JoinFreeModules-PT-5000-CTLFireability-09 11534013 m, 236807 m/sec, 11544536 t fired, .

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JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 5 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL SRCH 68/2766 2/5 JoinFreeModules-PT-5000-CTLFireability-09 12687614 m, 230720 m/sec, 12699187 t fired, .

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JoinFreeModules-PT-5000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
JoinFreeModules-PT-5000-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-09: DISJ 0 0 1 0 5 0 0 1
JoinFreeModules-PT-5000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
JoinFreeModules-PT-5000-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
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52 CTL SRCH 73/2766 2/5 JoinFreeModules-PT-5000-CTLFireability-09 13871104 m, 236698 m/sec, 13883757 t fired, .

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52 CTL SRCH 78/2766 2/5 JoinFreeModules-PT-5000-CTLFireability-09 15047023 m, 235183 m/sec, 15060747 t fired, .

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52 CTL SRCH 83/2766 2/5 JoinFreeModules-PT-5000-CTLFireability-09 16208286 m, 232252 m/sec, 16223072 t fired, .

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52 CTL SRCH 88/2766 2/5 JoinFreeModules-PT-5000-CTLFireability-09 17376206 m, 233584 m/sec, 17392058 t fired, .

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52 CTL SRCH 93/2766 2/5 JoinFreeModules-PT-5000-CTLFireability-09 18542245 m, 233207 m/sec, 18559159 t fired, .

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52 CTL SRCH 98/2766 2/5 JoinFreeModules-PT-5000-CTLFireability-09 19714136 m, 234378 m/sec, 19732120 t fired, .

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52 CTL SRCH 103/2766 3/5 JoinFreeModules-PT-5000-CTLFireability-09 20862823 m, 229737 m/sec, 20881858 t fired, .

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52 CTL SRCH 108/2766 3/5 JoinFreeModules-PT-5000-CTLFireability-09 22032120 m, 233859 m/sec, 22052221 t fired, .

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52 CTL SRCH 113/2766 3/5 JoinFreeModules-PT-5000-CTLFireability-09 23176576 m, 228891 m/sec, 23197722 t fired, .

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52 CTL SRCH 118/2766 3/5 JoinFreeModules-PT-5000-CTLFireability-09 24327035 m, 230091 m/sec, 24349228 t fired, .

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52 CTL SRCH 123/2766 3/5 JoinFreeModules-PT-5000-CTLFireability-09 25439727 m, 222538 m/sec, 25462934 t fired, .

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52 CTL SRCH 128/2766 3/5 JoinFreeModules-PT-5000-CTLFireability-09 26592331 m, 230520 m/sec, 26616591 t fired, .

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52 CTL SRCH 133/2766 3/5 JoinFreeModules-PT-5000-CTLFireability-09 27730527 m, 227639 m/sec, 27755825 t fired, .

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52 CTL SRCH 138/2766 3/5 JoinFreeModules-PT-5000-CTLFireability-09 28858677 m, 225630 m/sec, 28885001 t fired, .

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52 CTL SRCH 143/2766 3/5 JoinFreeModules-PT-5000-CTLFireability-09 29980889 m, 224442 m/sec, 30008239 t fired, .

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52 CTL SRCH 148/2766 4/5 JoinFreeModules-PT-5000-CTLFireability-09 31092933 m, 222408 m/sec, 31121300 t fired, .

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52 CTL SRCH 153/2766 4/5 JoinFreeModules-PT-5000-CTLFireability-09 32211271 m, 223667 m/sec, 32240653 t fired, .

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52 CTL SRCH 158/2766 4/5 JoinFreeModules-PT-5000-CTLFireability-09 33325327 m, 222811 m/sec, 33355724 t fired, .

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52 CTL SRCH 163/2766 4/5 JoinFreeModules-PT-5000-CTLFireability-09 34469630 m, 228860 m/sec, 34501075 t fired, .

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52 CTL SRCH 168/2766 4/5 JoinFreeModules-PT-5000-CTLFireability-09 35631052 m, 232284 m/sec, 35663556 t fired, .

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52 CTL SRCH 173/2766 4/5 JoinFreeModules-PT-5000-CTLFireability-09 36743030 m, 222395 m/sec, 36776548 t fired, .

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52 CTL SRCH 178/2766 4/5 JoinFreeModules-PT-5000-CTLFireability-09 37868310 m, 225056 m/sec, 37902854 t fired, .

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52 CTL SRCH 183/2766 4/5 JoinFreeModules-PT-5000-CTLFireability-09 39022315 m, 230801 m/sec, 39057913 t fired, .

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52 CTL SRCH 188/2766 4/5 JoinFreeModules-PT-5000-CTLFireability-09 40176376 m, 230812 m/sec, 40213026 t fired, .

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52 CTL SRCH 193/2766 5/5 JoinFreeModules-PT-5000-CTLFireability-09 41320645 m, 228853 m/sec, 41358344 t fired, .

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52 CTL SRCH 198/2766 5/5 JoinFreeModules-PT-5000-CTLFireability-09 42396679 m, 215206 m/sec, 42435504 t fired, .

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52 CTL SRCH 203/2766 5/5 JoinFreeModules-PT-5000-CTLFireability-09 43654087 m, 251481 m/sec, 43694132 t fired, .

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52 CTL SRCH 208/2766 5/5 JoinFreeModules-PT-5000-CTLFireability-09 44956137 m, 260410 m/sec, 44997514 t fired, .

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52 CTL SRCH 213/2766 5/5 JoinFreeModules-PT-5000-CTLFireability-09 46205801 m, 249932 m/sec, 46248723 t fired, .

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52 CTL SRCH 218/2766 5/5 JoinFreeModules-PT-5000-CTLFireability-09 47508808 m, 260601 m/sec, 47553062 t fired, .

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52 CTL SRCH 223/2766 5/5 JoinFreeModules-PT-5000-CTLFireability-09 48764398 m, 251118 m/sec, 48810238 t fired, .

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52 CTL SRCH 228/2766 5/5 JoinFreeModules-PT-5000-CTLFireability-09 50075265 m, 262173 m/sec, 50122347 t fired, .

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52 CTL SRCH 233/2766 5/5 JoinFreeModules-PT-5000-CTLFireability-09 51393210 m, 263589 m/sec, 51441617 t fired, .

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/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 535 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="JoinFreeModules-PT-5000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is JoinFreeModules-PT-5000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856415800226"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/JoinFreeModules-PT-5000.tgz
mv JoinFreeModules-PT-5000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;