Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-tall-167856415500034.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HypertorusGrid-PT-d2k2p1b00, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856415500034
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 548K
-rw-r--r-- 1 mcc users 10K Feb 26 10:46 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K Feb 26 10:46 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Feb 26 10:45 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 10:45 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 16:16 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:16 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 25 16:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:17 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 26 10:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 144K Feb 26 10:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 10:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 70K Feb 26 10:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:17 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:17 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rwxr-xr-x 1 mcc users 35K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-00
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-01
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-02
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-03
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-04
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-05
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-06
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-07
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-08
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-09
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-10
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-11
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-12
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-13
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-14
FORMULA_NAME HypertorusGrid-PT-d2k2p1b00-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679428535841

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HypertorusGrid-PT-d2k2p1b00
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-21 19:55:37] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-21 19:55:37] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-21 19:55:37] [INFO ] Load time of PNML (sax parser for PT used): 28 ms
[2023-03-21 19:55:37] [INFO ] Transformed 52 places.
[2023-03-21 19:55:37] [INFO ] Transformed 64 transitions.
[2023-03-21 19:55:37] [INFO ] Parsed PT model containing 52 places and 64 transitions and 256 arcs in 84 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 50 out of 52 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 9 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
// Phase 1: matrix 64 rows 52 cols
[2023-03-21 19:55:37] [INFO ] Computed 21 place invariants in 17 ms
[2023-03-21 19:55:37] [INFO ] Implicit Places using invariants in 168 ms returned []
[2023-03-21 19:55:37] [INFO ] Invariant cache hit.
[2023-03-21 19:55:37] [INFO ] Implicit Places using invariants and state equation in 56 ms returned []
Implicit Place search using SMT with State Equation took 247 ms to find 0 implicit places.
[2023-03-21 19:55:37] [INFO ] Invariant cache hit.
[2023-03-21 19:55:37] [INFO ] Dead Transitions using invariants and state equation in 65 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 323 ms. Remains : 52/52 places, 64/64 transitions.
Support contains 50 out of 52 places after structural reductions.
[2023-03-21 19:55:37] [INFO ] Flatten gal took : 85 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 10 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Finished random walk after 142 steps, including 0 resets, run visited all 49 properties in 27 ms. (steps per millisecond=5 )
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 6 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 7 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 6 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 5 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 3 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 3 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 5 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 5 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 2 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 5 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 3 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 64/64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 3 ms
[2023-03-21 19:55:38] [INFO ] Input system was already deterministic with 64 transitions.
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Flatten gal took : 4 ms
[2023-03-21 19:55:38] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-21 19:55:38] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 52 places, 64 transitions and 256 arcs took 1 ms.
Total runtime 1345 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HypertorusGrid-PT-d2k2p1b00
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/371
CTLFireability

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HypertorusGrid-PT-d2k2p1b00-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679428704876

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/371/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/371/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/371/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 13 (type EXCL) for 12 HypertorusGrid-PT-d2k2p1b00-CTLFireability-04
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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37 CTL EXCL 5/257 7/32 HypertorusGrid-PT-d2k2p1b00-CTLFireability-12 1582933 m, 316586 m/sec, 6003714 t fired, .

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HypertorusGrid-PT-d2k2p1b00-CTLFireability-14: EFAG 0 1 0 0 1 0 0 0
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37 CTL EXCL 10/257 12/32 HypertorusGrid-PT-d2k2p1b00-CTLFireability-12 2881646 m, 259742 m/sec, 10993327 t fired, .

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37 CTL EXCL 15/257 17/32 HypertorusGrid-PT-d2k2p1b00-CTLFireability-12 4055014 m, 234673 m/sec, 15629363 t fired, .

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37 CTL EXCL 20/257 22/32 HypertorusGrid-PT-d2k2p1b00-CTLFireability-12 5182064 m, 225410 m/sec, 20049192 t fired, .

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37 CTL EXCL 25/257 27/32 HypertorusGrid-PT-d2k2p1b00-CTLFireability-12 6267484 m, 217084 m/sec, 24325536 t fired, .

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37 CTL EXCL 30/257 31/32 HypertorusGrid-PT-d2k2p1b00-CTLFireability-12 7324960 m, 211495 m/sec, 28487869 t fired, .

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HypertorusGrid-PT-d2k2p1b00-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 AGEF EXCL 20/693 24/32 HypertorusGrid-PT-d2k2p1b00-CTLFireability-14 6187250 m, 261747 m/sec, 16362548 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HypertorusGrid-PT-d2k2p1b00-CTLFireability-01: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-04: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-05: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-06: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-07: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-11: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HypertorusGrid-PT-d2k2p1b00-CTLFireability-00: F 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-14: EFAG 0 0 1 0 1 0 0 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 AGEF EXCL 25/693 29/32 HypertorusGrid-PT-d2k2p1b00-CTLFireability-14 7424781 m, 247506 m/sec, 19796019 t fired, .

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lola: CANCELED task # 49 (type EXCL) for HypertorusGrid-PT-d2k2p1b00-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HypertorusGrid-PT-d2k2p1b00-CTLFireability-01: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-04: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-05: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-06: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-07: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-11: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HypertorusGrid-PT-d2k2p1b00-CTLFireability-00: F 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-14: EFAG 0 0 0 0 1 0 1 0
HypertorusGrid-PT-d2k2p1b00-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 48 (type EXCL) for 0 HypertorusGrid-PT-d2k2p1b00-CTLFireability-00
lola: time limit : 858 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for HypertorusGrid-PT-d2k2p1b00-CTLFireability-00
lola: result : true
lola: markings : 20
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 HypertorusGrid-PT-d2k2p1b00-CTLFireability-03
lola: time limit : 1145 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for HypertorusGrid-PT-d2k2p1b00-CTLFireability-03
lola: result : false
lola: markings : 31
lola: fired transitions : 62
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 HypertorusGrid-PT-d2k2p1b00-CTLFireability-10
lola: time limit : 1717 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for HypertorusGrid-PT-d2k2p1b00-CTLFireability-10
lola: result : true
lola: markings : 10293
lola: fired transitions : 63708
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 HypertorusGrid-PT-d2k2p1b00-CTLFireability-02
lola: time limit : 3435 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for HypertorusGrid-PT-d2k2p1b00-CTLFireability-02
lola: result : false
lola: markings : 231
lola: fired transitions : 748
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HypertorusGrid-PT-d2k2p1b00-CTLFireability-00: F false state space / EG
HypertorusGrid-PT-d2k2p1b00-CTLFireability-01: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-02: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-03: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-04: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-05: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-06: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-07: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-08: CTL unknown AGGR
HypertorusGrid-PT-d2k2p1b00-CTLFireability-09: CTL unknown AGGR
HypertorusGrid-PT-d2k2p1b00-CTLFireability-10: CTL true CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-11: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-12: CTL unknown AGGR
HypertorusGrid-PT-d2k2p1b00-CTLFireability-13: CTL false CTL model checker
HypertorusGrid-PT-d2k2p1b00-CTLFireability-14: EFAG unknown AGGR
HypertorusGrid-PT-d2k2p1b00-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HypertorusGrid-PT-d2k2p1b00"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HypertorusGrid-PT-d2k2p1b00, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856415500034"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/HypertorusGrid-PT-d2k2p1b00.tgz
mv HypertorusGrid-PT-d2k2p1b00 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;