About the Execution of LoLA for LamportFastMutEx-PT-5
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1778.292 | 471082.00 | 1866214.00 | 17.60 | TFTTTFFFFFFFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r230-tall-167856414600422.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is LamportFastMutEx-PT-5, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r230-tall-167856414600422
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 12K Feb 25 13:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 25 13:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 25K Feb 25 13:40 CTLFireability.txt
-rw-r--r-- 1 mcc users 145K Feb 25 13:40 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 7.2K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 35K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 36K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 38K Feb 25 13:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 249K Feb 25 13:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 42K Feb 25 13:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 224K Feb 25 13:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.2K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 157K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1679463841865
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-PT-5
Not applying reductions.
Model is PT
ReachabilityCardinality PT
starting LoLA
BK_INPUT LamportFastMutEx-PT-5
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679464312947
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 49 (type SKEL/FNDP) for 6 LamportFastMutEx-PT-5-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SKEL/EQUN) for 6 LamportFastMutEx-PT-5-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SKEL/SRCH) for 6 LamportFastMutEx-PT-5-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type SKEL/SRCH) for 6 LamportFastMutEx-PT-5-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type SKEL/SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-02
lola: result : true
lola: markings : 12
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 49 (type FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 50 (type EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 52 (type SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 57 (type SKEL/FNDP) for 9 LamportFastMutEx-PT-5-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SKEL/EQUN) for 9 LamportFastMutEx-PT-5-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SKEL/SRCH) for 9 LamportFastMutEx-PT-5-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 61 (type SKEL/SRCH) for 9 LamportFastMutEx-PT-5-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 49 (type SKEL/FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-02
lola: result : true
lola: fired transitions : 9
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 31 (type CNST) for 30 LamportFastMutEx-PT-5-ReachabilityCardinality-10
lola: time limit : 0 sec
lola: memory limit: 0 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-58.sara.
lola: LAUNCH INITIAL
lola: LAUNCH task # 28 (type CNST) for 27 LamportFastMutEx-PT-5-ReachabilityCardinality-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 31 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-10
lola: result : false
lola: Rule S: 58 transitions removed,37 places removed
lola: LAUNCH INITIAL
lola: LAUNCH task # 25 (type CNST) for 24 LamportFastMutEx-PT-5-ReachabilityCardinality-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 28 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-09
lola: result : false
lola: LAUNCH INITIAL
lola: LAUNCH task # 34 (type CNST) for 33 LamportFastMutEx-PT-5-ReachabilityCardinality-11
lola: time limit : 0 sec
lola: memory limit: 0 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-50.sara.
lola: FINISHED task # 34 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-11
lola: result : false
lola: FINISHED task # 25 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-08
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 LamportFastMutEx-PT-5-ReachabilityCardinality-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 4 (type CNST) for 3 LamportFastMutEx-PT-5-ReachabilityCardinality-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: LAUNCH task # 13 (type CNST) for 12 LamportFastMutEx-PT-5-ReachabilityCardinality-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 37 (type CNST) for 36 LamportFastMutEx-PT-5-ReachabilityCardinality-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 43 (type CNST) for 42 LamportFastMutEx-PT-5-ReachabilityCardinality-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 37 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-12
lola: result : false
lola: FINISHED task # 1 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-00
lola: result : true
lola: FINISHED task # 43 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-14
lola: result : false
lola: FINISHED task # 13 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-04
lola: result : true
lola: FINISHED task # 4 (type CNST) for LamportFastMutEx-PT-5-ReachabilityCardinality-01
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 58 (type SKEL/EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 57 (type FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 60 (type SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 61 (type SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 107 (type EXCL) for 39 LamportFastMutEx-PT-5-ReachabilityCardinality-13
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 97 (type FNDP) for 15 LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 98 (type EQUN) for 15 LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 100 (type SRCH) for 15 LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 57 (type SKEL/FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 65291
lola: tried executions : 841
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 50 (type SKEL/EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-02
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-98.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF 0 5 0 0 3 0 0 2
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 7 3 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF 0 10 0 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF 0 10 0 0 0 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
97 EF FNDP 5/276 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 1117038 t fired, 2 attempts, .
98 EF STEQ 5/276 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
100 EF SRCH 5/276 4/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 916961 m, 183392 m/sec, 1139459 t fired, .
107 EF EXCL 5/599 1/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 242476 m, 48495 m/sec, 340559 t fired, .
Time elapsed: 6 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 100 (type SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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97 EF FNDP 10/271 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 2230516 t fired, 3 attempts, .
98 EF STEQ 10/271 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
107 EF EXCL 10/599 2/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 487998 m, 49104 m/sec, 712683 t fired, .
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85 EF FNDP 5/276 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 985022 t fired, 1 attempts, .
97 EF FNDP 15/266 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 3204248 t fired, 4 attempts, .
98 EF STEQ 15/289 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
107 EF EXCL 15/599 3/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 732069 m, 48814 m/sec, 1092057 t fired, .
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85 EF FNDP 10/271 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 1952582 t fired, 2 attempts, .
97 EF FNDP 20/261 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 4171599 t fired, 5 attempts, .
98 EF STEQ 20/284 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
107 EF EXCL 20/599 4/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 975754 m, 48737 m/sec, 1482584 t fired, .
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85 EF FNDP 15/266 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 2910418 t fired, 3 attempts, .
97 EF FNDP 25/256 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 5134646 t fired, 6 attempts, .
98 EF STEQ 25/279 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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85 EF FNDP 20/261 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 3859135 t fired, 4 attempts, .
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98 EF STEQ 30/274 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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85 EF FNDP 25/256 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 4804696 t fired, 5 attempts, .
97 EF FNDP 35/246 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 7046810 t fired, 8 attempts, .
98 EF STEQ 35/269 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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85 EF FNDP 30/251 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 5748414 t fired, 6 attempts, .
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98 EF STEQ 40/264 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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85 EF FNDP 35/246 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 6690907 t fired, 7 attempts, .
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85 EF FNDP 40/241 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 7631465 t fired, 8 attempts, .
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85 EF FNDP 45/236 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 8570837 t fired, 9 attempts, .
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85 EF FNDP 50/231 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 9507208 t fired, 10 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
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85 EF FNDP 115/166 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 21630828 t fired, 22 attempts, .
97 EF FNDP 125/156 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 24049864 t fired, 25 attempts, .
98 EF STEQ 125/179 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
107 EF EXCL 125/599 24/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 6004044 m, 47406 m/sec, 10215269 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
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85 EF FNDP 120/161 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 22561599 t fired, 23 attempts, .
97 EF FNDP 130/151 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 24991540 t fired, 25 attempts, .
98 EF STEQ 130/174 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
107 EF EXCL 130/599 24/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 6241385 m, 47468 m/sec, 10646693 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
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85 EF FNDP 125/156 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 23492047 t fired, 24 attempts, .
97 EF FNDP 135/146 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 25933604 t fired, 26 attempts, .
98 EF STEQ 135/169 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
107 EF EXCL 135/599 25/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 6479045 m, 47532 m/sec, 11082477 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
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85 EF FNDP 130/151 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 24422863 t fired, 25 attempts, .
97 EF FNDP 140/141 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 26875153 t fired, 27 attempts, .
98 EF STEQ 140/164 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
107 EF EXCL 140/599 26/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 6717001 m, 47591 m/sec, 11524369 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
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85 EF FNDP 135/146 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 25352105 t fired, 26 attempts, .
98 EF STEQ 145/159 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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85 EF FNDP 140/164 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 26306325 t fired, 27 attempts, .
98 EF STEQ 150/154 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
107 EF EXCL 150/599 28/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7191410 m, 47261 m/sec, 12403878 t fired, .
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85 EF FNDP 145/159 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 27249075 t fired, 28 attempts, .
107 EF EXCL 155/599 29/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7428661 m, 47450 m/sec, 12846815 t fired, .
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64 EF FNDP 5/287 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 3369368 t fired, 39185 attempts, .
85 EF FNDP 150/181 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 27936882 t fired, 28 attempts, .
107 EF EXCL 160/599 30/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7665050 m, 47277 m/sec, 13293094 t fired, .
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64 EF FNDP 10/282 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 6597787 t fired, 76870 attempts, .
85 EF FNDP 155/176 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 28616198 t fired, 29 attempts, .
107 EF EXCL 165/599 31/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7900543 m, 47098 m/sec, 13735355 t fired, .
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64 EF FNDP 15/277 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 9785342 t fired, 113870 attempts, .
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107 EF EXCL 170/599 32/32 LamportFastMutEx-PT-5-ReachabilityCardinality-13 8138869 m, 47665 m/sec, 14183461 t fired, .
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64 EF FNDP 20/272 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 12959085 t fired, 150989 attempts, .
85 EF FNDP 165/166 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-07 29970037 t fired, 30 attempts, .
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64 EF FNDP 25/267 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 16102374 t fired, 187542 attempts, .
90 EF EXCL 5/684 2/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 266291 m, 53258 m/sec, 376736 t fired, .
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90 EF EXCL 10/1141 3/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 509977 m, 48737 m/sec, 745882 t fired, .
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64 EF FNDP 35/400 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 21775370 t fired, 253865 attempts, .
90 EF EXCL 15/1141 3/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 749841 m, 47972 m/sec, 1116356 t fired, .
103 EF FNDP 10/483 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 1586278 t fired, 2 attempts, .
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64 EF FNDP 40/395 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 24450392 t fired, 285324 attempts, .
90 EF EXCL 20/1141 4/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 988053 m, 47642 m/sec, 1491018 t fired, .
103 EF FNDP 15/478 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 2332041 t fired, 3 attempts, .
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64 EF FNDP 45/390 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 27067378 t fired, 315561 attempts, .
90 EF EXCL 25/1141 5/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 1225103 m, 47410 m/sec, 1866459 t fired, .
103 EF FNDP 20/473 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 3056812 t fired, 4 attempts, .
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64 EF FNDP 50/385 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 29648533 t fired, 345971 attempts, .
90 EF EXCL 30/1141 6/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 1457501 m, 46479 m/sec, 2237538 t fired, .
103 EF FNDP 25/468 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 3769015 t fired, 4 attempts, .
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64 EF FNDP 60/375 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 34740354 t fired, 405286 attempts, .
90 EF EXCL 40/1141 8/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 1921745 m, 46340 m/sec, 2995310 t fired, .
103 EF FNDP 35/458 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 5162686 t fired, 6 attempts, .
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64 EF FNDP 75/360 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 42443810 t fired, 495403 attempts, .
90 EF EXCL 55/1141 11/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 2604242 m, 44954 m/sec, 4132080 t fired, .
103 EF FNDP 50/443 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7202155 t fired, 8 attempts, .
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64 EF FNDP 80/355 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 45049578 t fired, 525656 attempts, .
90 EF EXCL 60/1141 12/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 2830626 m, 45276 m/sec, 4514520 t fired, .
103 EF FNDP 55/438 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 7872090 t fired, 8 attempts, .
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64 EF FNDP 85/350 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 47685691 t fired, 556715 attempts, .
90 EF EXCL 65/1141 12/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 3058160 m, 45506 m/sec, 4900419 t fired, .
103 EF FNDP 60/433 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 8539019 t fired, 9 attempts, .
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64 EF FNDP 90/345 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 50295618 t fired, 587311 attempts, .
90 EF EXCL 70/1141 13/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 3283303 m, 45028 m/sec, 5281604 t fired, .
103 EF FNDP 65/428 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 9206304 t fired, 10 attempts, .
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64 EF FNDP 95/340 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 52865787 t fired, 617263 attempts, .
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103 EF FNDP 70/423 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 9878032 t fired, 10 attempts, .
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64 EF FNDP 100/335 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 55424308 t fired, 646924 attempts, .
90 EF EXCL 80/1141 15/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 3728463 m, 44539 m/sec, 6046288 t fired, .
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64 EF FNDP 105/330 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 58000449 t fired, 676868 attempts, .
90 EF EXCL 85/1141 16/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 3952951 m, 44897 m/sec, 6435388 t fired, .
103 EF FNDP 80/413 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 11223917 t fired, 12 attempts, .
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64 EF FNDP 110/325 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 60570258 t fired, 706631 attempts, .
90 EF EXCL 90/1141 17/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 4172094 m, 43828 m/sec, 6818850 t fired, .
103 EF FNDP 85/408 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 11895626 t fired, 12 attempts, .
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64 EF FNDP 115/320 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 63137593 t fired, 736140 attempts, .
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103 EF FNDP 90/403 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 12568653 t fired, 13 attempts, .
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64 EF FNDP 120/315 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 65693595 t fired, 765745 attempts, .
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64 EF FNDP 125/310 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 68253261 t fired, 795663 attempts, .
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64 EF FNDP 130/305 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 70848170 t fired, 825755 attempts, .
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64 EF FNDP 135/300 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 73434819 t fired, 856082 attempts, .
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64 EF FNDP 140/295 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 76015764 t fired, 886045 attempts, .
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64 EF FNDP 150/285 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 81403055 t fired, 949315 attempts, .
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64 EF FNDP 155/280 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 84115442 t fired, 980935 attempts, .
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64 EF FNDP 160/275 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 86818868 t fired, 1012567 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
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64 EF FNDP 190/245 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 103156179 t fired, 1203099 attempts, .
90 EF EXCL 170/1141 30/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 7627040 m, 42755 m/sec, 13057284 t fired, .
103 EF FNDP 165/328 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 22539129 t fired, 23 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
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64 EF FNDP 195/240 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 105883260 t fired, 1234637 attempts, .
90 EF EXCL 175/1141 31/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 7840830 m, 42758 m/sec, 13455664 t fired, .
103 EF FNDP 170/323 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 23197973 t fired, 24 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
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64 EF FNDP 200/235 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 108611006 t fired, 1266582 attempts, .
90 EF EXCL 180/1141 32/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 8053187 m, 42471 m/sec, 13847528 t fired, .
103 EF FNDP 175/318 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 23858131 t fired, 24 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
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64 EF FNDP 205/230 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 111312029 t fired, 1298091 attempts, .
90 EF EXCL 185/1141 32/32 LamportFastMutEx-PT-5-ReachabilityCardinality-15 8263613 m, 42085 m/sec, 14242875 t fired, .
103 EF FNDP 180/313 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 24515133 t fired, 25 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
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64 EF FNDP 210/225 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 114009229 t fired, 1329591 attempts, .
103 EF FNDP 185/308 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 25172735 t fired, 26 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
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64 EF FNDP 215/220 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 116721191 t fired, 1361062 attempts, .
103 EF FNDP 190/303 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 25834658 t fired, 26 attempts, .
122 EF FNDP 225/273 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-06 31738175 t fired, 32 attempts, .
126 EF EXCL 5/1617 2/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 428998 m, 85799 m/sec, 634298 t fired, .
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103 EF FNDP 195/298 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 26492762 t fired, 27 attempts, .
122 EF FNDP 230/268 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-06 32456892 t fired, 33 attempts, .
126 EF EXCL 10/1617 4/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 833364 m, 80873 m/sec, 1289902 t fired, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
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65 EF STEQ 5/460 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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65 EF STEQ 10/455 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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65 EF STEQ 15/450 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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65 EF STEQ 20/445 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
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lola: result : unknown
lola: fired transitions : 36442062
lola: tried executions : 38
lola: time used : 250.000000
lola: memory pages used : 0
lola: LAUNCH task # 86 (type FNDP) for 45 LamportFastMutEx-PT-5-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
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LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
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65 EF STEQ 25/440 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 5/457 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 1047805 t fired, 2 attempts, .
103 EF FNDP 220/354 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 31224021 t fired, 32 attempts, .
126 EF EXCL 35/1617 11/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 2719318 m, 74926 m/sec, 4535915 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
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65 EF STEQ 30/435 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 10/452 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 2058100 t fired, 3 attempts, .
103 EF FNDP 225/349 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 32193332 t fired, 33 attempts, .
126 EF EXCL 40/1617 12/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 3094107 m, 74957 m/sec, 5209652 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
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65 EF STEQ 35/430 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 15/447 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 3050454 t fired, 4 attempts, .
103 EF FNDP 230/344 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 33156487 t fired, 34 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
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65 EF STEQ 40/425 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 20/442 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 4034181 t fired, 5 attempts, .
103 EF FNDP 235/339 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 34115132 t fired, 35 attempts, .
126 EF EXCL 50/1617 15/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 3837828 m, 74174 m/sec, 6555976 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
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65 EF STEQ 45/420 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 25/437 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 5010032 t fired, 6 attempts, .
103 EF FNDP 240/334 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 35068869 t fired, 36 attempts, .
126 EF EXCL 55/1617 17/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 4208981 m, 74230 m/sec, 7239216 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
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65 EF STEQ 50/415 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 30/432 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 5983067 t fired, 6 attempts, .
103 EF FNDP 245/329 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 36022078 t fired, 37 attempts, .
126 EF EXCL 60/1617 18/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 4578422 m, 73888 m/sec, 7922223 t fired, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
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65 EF STEQ 55/410 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 35/427 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 6951595 t fired, 7 attempts, .
103 EF FNDP 250/324 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 36973810 t fired, 37 attempts, .
126 EF EXCL 65/1617 20/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 4945158 m, 73347 m/sec, 8606676 t fired, .
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65 EF STEQ 60/405 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 40/422 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 7918197 t fired, 8 attempts, .
103 EF FNDP 255/319 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 37925250 t fired, 38 attempts, .
126 EF EXCL 70/1617 21/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 5312022 m, 73372 m/sec, 9294415 t fired, .
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65 EF STEQ 65/400 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 45/417 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 8883063 t fired, 9 attempts, .
103 EF FNDP 260/314 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 38874086 t fired, 39 attempts, .
126 EF EXCL 75/1617 22/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 5676749 m, 72945 m/sec, 9992325 t fired, .
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65 EF STEQ 70/395 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 50/412 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 9848205 t fired, 10 attempts, .
103 EF FNDP 265/309 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 39821965 t fired, 40 attempts, .
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65 EF STEQ 75/390 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 55/407 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 10810561 t fired, 11 attempts, .
103 EF FNDP 270/304 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 40766342 t fired, 41 attempts, .
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LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF STEQ 80/385 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 60/402 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 11771624 t fired, 12 attempts, .
103 EF FNDP 275/299 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 41711592 t fired, 42 attempts, .
126 EF EXCL 90/1617 26/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 6767609 m, 72451 m/sec, 12085675 t fired, .
Time elapsed: 456 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF STEQ 85/380 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 65/397 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 12731428 t fired, 13 attempts, .
103 EF FNDP 280/294 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 42657273 t fired, 43 attempts, .
126 EF EXCL 95/1617 28/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 7130574 m, 72593 m/sec, 12787741 t fired, .
Time elapsed: 461 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 1 0 1 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF STEQ 90/375 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 70/392 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 13691928 t fired, 14 attempts, .
103 EF FNDP 285/289 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-13 43600487 t fired, 44 attempts, .
126 EF EXCL 100/1617 29/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 7492573 m, 72399 m/sec, 13486064 t fired, .
Time elapsed: 466 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 103 (type FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-13 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF 0 4 1 0 4 0 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF 0 8 1 0 1 0 0 0
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF 0 3 0 0 1 1 1 0
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG 0 3 1 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF STEQ 95/370 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-05 sara is running.
86 EF FNDP 75/387 0/5 LamportFastMutEx-PT-5-ReachabilityCardinality-15 14649869 t fired, 15 attempts, .
126 EF EXCL 105/1617 31/32 LamportFastMutEx-PT-5-ReachabilityCardinality-06 7849475 m, 71380 m/sec, 14195002 t fired, .
Time elapsed: 471 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 104 (type EQUN) for 39 LamportFastMutEx-PT-5-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 103 (type FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-13
lola: result : unknown
lola: fired transitions : 44545157
lola: tried executions : 46
lola: time used : 290.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-104.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 104 (type EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-13
lola: result : false
lola: LAUNCH task # 123 (type EQUN) for 18 LamportFastMutEx-PT-5-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-123.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 123 (type EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-06
lola: result : false
lola: CANCELED task # 126 (type EXCL) for LamportFastMutEx-PT-5-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 101 (type EXCL) for 15 LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: time limit : 3129 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 67 (type SKEL/SRCH) for 15 LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 67 (type SKEL/SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: result : false
lola: markings : 153589
lola: fired transitions : 499267
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 65 (type EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 101 (type EXCL) for LamportFastMutEx-PT-5-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 87 (type EQUN) for 45 LamportFastMutEx-PT-5-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 89 (type SRCH) for 45 LamportFastMutEx-PT-5-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 91 (type SRCH) for 45 LamportFastMutEx-PT-5-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 65 (type SKEL/EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-05
lola: result : unknown
lola: FINISHED task # 91 (type SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-15
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-87.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 87 (type EQUN) for LamportFastMutEx-PT-5-ReachabilityCardinality-15
lola: result : false
lola: CANCELED task # 86 (type FNDP) for LamportFastMutEx-PT-5-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 89 (type SRCH) for LamportFastMutEx-PT-5-ReachabilityCardinality-15 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-ReachabilityCardinality-00: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-01: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-02: EF true findpath
LamportFastMutEx-PT-5-ReachabilityCardinality-03: AG true skeleton: state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-04: INITIAL true preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-05: EF false skeleton: tandem / insertion
LamportFastMutEx-PT-5-ReachabilityCardinality-06: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-07: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-08: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-10: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-11: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-12: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-13: EF false state equation
LamportFastMutEx-PT-5-ReachabilityCardinality-14: INITIAL false preprocessing
LamportFastMutEx-PT-5-ReachabilityCardinality-15: AG true state equation
Time elapsed: 471 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-5"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is LamportFastMutEx-PT-5, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r230-tall-167856414600422"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-5.tgz
mv LamportFastMutEx-PT-5 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;