About the Execution of LoLa+red for HirschbergSinclair-PT-30
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3216.720 | 1127863.00 | 1141742.00 | 4028.40 | ?TT???F??FTF?TT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r199-smll-167840346000466.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HirschbergSinclair-PT-30, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840346000466
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 780K
-rw-r--r-- 1 mcc users 9.2K Feb 26 02:12 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 26 02:12 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 26 02:11 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 26 02:11 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.0K Feb 25 16:15 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:15 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Feb 26 02:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 130K Feb 26 02:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 26 02:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 29K Feb 26 02:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 357K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-00
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-01
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-02
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-03
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-04
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-05
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-06
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-07
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-08
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-09
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-10
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-11
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-12
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-13
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-14
FORMULA_NAME HirschbergSinclair-PT-30-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678547521095
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-30
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 15:12:04] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 15:12:04] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 15:12:04] [INFO ] Load time of PNML (sax parser for PT used): 164 ms
[2023-03-11 15:12:04] [INFO ] Transformed 670 places.
[2023-03-11 15:12:04] [INFO ] Transformed 605 transitions.
[2023-03-11 15:12:04] [INFO ] Parsed PT model containing 670 places and 605 transitions and 1849 arcs in 410 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 22 ms.
Support contains 124 out of 670 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 670/670 places, 605/605 transitions.
Reduce places removed 30 places and 0 transitions.
Iterating post reduction 0 with 30 rules applied. Total rules applied 30 place count 640 transition count 605
Discarding 22 places :
Symmetric choice reduction at 1 with 22 rule applications. Total rules 52 place count 618 transition count 583
Iterating global reduction 1 with 22 rules applied. Total rules applied 74 place count 618 transition count 583
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 88 place count 604 transition count 569
Iterating global reduction 1 with 14 rules applied. Total rules applied 102 place count 604 transition count 569
Applied a total of 102 rules in 203 ms. Remains 604 /670 variables (removed 66) and now considering 569/605 (removed 36) transitions.
// Phase 1: matrix 569 rows 604 cols
[2023-03-11 15:12:05] [INFO ] Computed 35 place invariants in 48 ms
[2023-03-11 15:12:05] [INFO ] Implicit Places using invariants in 820 ms returned []
[2023-03-11 15:12:05] [INFO ] Invariant cache hit.
[2023-03-11 15:12:07] [INFO ] Implicit Places using invariants and state equation in 1461 ms returned []
Implicit Place search using SMT with State Equation took 2345 ms to find 0 implicit places.
[2023-03-11 15:12:07] [INFO ] Invariant cache hit.
[2023-03-11 15:12:07] [INFO ] Dead Transitions using invariants and state equation in 488 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 604/670 places, 569/605 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3039 ms. Remains : 604/670 places, 569/605 transitions.
Support contains 124 out of 604 places after structural reductions.
[2023-03-11 15:12:08] [INFO ] Flatten gal took : 125 ms
[2023-03-11 15:12:08] [INFO ] Flatten gal took : 56 ms
[2023-03-11 15:12:08] [INFO ] Input system was already deterministic with 569 transitions.
Support contains 122 out of 604 places (down from 124) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 16 resets, run finished after 666 ms. (steps per millisecond=15 ) properties (out of 78) seen :68
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 10) seen :0
Running SMT prover for 10 properties.
[2023-03-11 15:12:09] [INFO ] Invariant cache hit.
[2023-03-11 15:12:09] [INFO ] [Real]Absence check using 0 positive and 35 generalized place invariants in 155 ms returned sat
[2023-03-11 15:12:10] [INFO ] After 579ms SMT Verify possible using state equation in real domain returned unsat :2 sat :2 real:6
[2023-03-11 15:12:10] [INFO ] After 799ms SMT Verify possible using trap constraints in real domain returned unsat :2 sat :2 real:6
Attempting to minimize the solution found.
Minimization took 105 ms.
[2023-03-11 15:12:11] [INFO ] After 1600ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :2 real:6
[2023-03-11 15:12:11] [INFO ] [Nat]Absence check using 0 positive and 35 generalized place invariants in 146 ms returned sat
[2023-03-11 15:12:12] [INFO ] After 1091ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :7
[2023-03-11 15:12:13] [INFO ] After 2073ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :7
Attempting to minimize the solution found.
Minimization took 747 ms.
[2023-03-11 15:12:14] [INFO ] After 3446ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :7
Fused 10 Parikh solutions to 7 different solutions.
Parikh walk visited 1 properties in 101 ms.
Support contains 25 out of 604 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 604/604 places, 569/569 transitions.
Drop transitions removed 164 transitions
Trivial Post-agglo rules discarded 164 transitions
Performed 164 trivial Post agglomeration. Transition count delta: 164
Iterating post reduction 0 with 164 rules applied. Total rules applied 164 place count 604 transition count 405
Reduce places removed 164 places and 0 transitions.
Graph (complete) has 779 edges and 440 vertex of which 402 are kept as prefixes of interest. Removing 38 places using SCC suffix rule.2 ms
Discarding 38 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 165 rules applied. Total rules applied 329 place count 402 transition count 405
Drop transitions removed 38 transitions
Reduce isomorphic transitions removed 38 transitions.
Iterating post reduction 2 with 38 rules applied. Total rules applied 367 place count 402 transition count 367
Discarding 8 places :
Symmetric choice reduction at 3 with 8 rule applications. Total rules 375 place count 394 transition count 359
Iterating global reduction 3 with 8 rules applied. Total rules applied 383 place count 394 transition count 359
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 3 with 3 rules applied. Total rules applied 386 place count 394 transition count 356
Reduce places removed 3 places and 0 transitions.
Graph (complete) has 694 edges and 391 vertex of which 386 are kept as prefixes of interest. Removing 5 places using SCC suffix rule.1 ms
Discarding 5 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 4 rules applied. Total rules applied 390 place count 386 transition count 356
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 5 with 5 rules applied. Total rules applied 395 place count 386 transition count 351
Discarding 5 places :
Symmetric choice reduction at 6 with 5 rule applications. Total rules 400 place count 381 transition count 346
Iterating global reduction 6 with 5 rules applied. Total rules applied 405 place count 381 transition count 346
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 406 place count 380 transition count 345
Iterating global reduction 6 with 1 rules applied. Total rules applied 407 place count 380 transition count 345
Free-agglomeration rule (complex) applied 23 times.
Iterating global reduction 6 with 23 rules applied. Total rules applied 430 place count 380 transition count 322
Reduce places removed 23 places and 0 transitions.
Iterating post reduction 6 with 23 rules applied. Total rules applied 453 place count 357 transition count 322
Reduce places removed 20 places and 20 transitions.
Iterating global reduction 7 with 20 rules applied. Total rules applied 473 place count 337 transition count 302
Applied a total of 473 rules in 312 ms. Remains 337 /604 variables (removed 267) and now considering 302/569 (removed 267) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 313 ms. Remains : 337/604 places, 302/569 transitions.
Incomplete random walk after 10000 steps, including 31 resets, run finished after 209 ms. (steps per millisecond=47 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 5 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 6 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 5 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 6 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10000 steps, including 6 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 6 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
// Phase 1: matrix 302 rows 337 cols
[2023-03-11 15:12:15] [INFO ] Computed 35 place invariants in 5 ms
[2023-03-11 15:12:15] [INFO ] [Real]Absence check using 0 positive and 35 generalized place invariants in 103 ms returned sat
[2023-03-11 15:12:16] [INFO ] After 656ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-11 15:12:16] [INFO ] [Nat]Absence check using 0 positive and 35 generalized place invariants in 92 ms returned sat
[2023-03-11 15:12:16] [INFO ] After 421ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-11 15:12:16] [INFO ] State equation strengthened by 14 read => feed constraints.
[2023-03-11 15:12:17] [INFO ] After 175ms SMT Verify possible using 14 Read/Feed constraints in natural domain returned unsat :0 sat :3
[2023-03-11 15:12:17] [INFO ] After 390ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 131 ms.
[2023-03-11 15:12:17] [INFO ] After 1205ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Parikh walk visited 0 properties in 38 ms.
Support contains 18 out of 337 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 337/337 places, 302/302 transitions.
Drop transitions removed 11 transitions
Trivial Post-agglo rules discarded 11 transitions
Performed 11 trivial Post agglomeration. Transition count delta: 11
Iterating post reduction 0 with 11 rules applied. Total rules applied 11 place count 337 transition count 291
Reduce places removed 11 places and 0 transitions.
Graph (complete) has 598 edges and 326 vertex of which 321 are kept as prefixes of interest. Removing 5 places using SCC suffix rule.1 ms
Discarding 5 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 12 rules applied. Total rules applied 23 place count 321 transition count 291
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 28 place count 321 transition count 286
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 3 with 1 rules applied. Total rules applied 29 place count 321 transition count 285
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 30 place count 320 transition count 285
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 4 with 1 rules applied. Total rules applied 31 place count 319 transition count 284
Applied a total of 31 rules in 78 ms. Remains 319 /337 variables (removed 18) and now considering 284/302 (removed 18) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 78 ms. Remains : 319/337 places, 284/302 transitions.
Incomplete random walk after 10000 steps, including 33 resets, run finished after 230 ms. (steps per millisecond=43 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10000 steps, including 6 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 8 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 3) seen :0
Interrupted probabilistic random walk after 499923 steps, run timeout after 3001 ms. (steps per millisecond=166 ) properties seen :{2=1}
Probabilistic random walk after 499923 steps, saw 109055 distinct states, run finished after 3002 ms. (steps per millisecond=166 ) properties seen :1
Running SMT prover for 2 properties.
// Phase 1: matrix 284 rows 319 cols
[2023-03-11 15:12:20] [INFO ] Computed 35 place invariants in 3 ms
[2023-03-11 15:12:21] [INFO ] [Real]Absence check using 0 positive and 35 generalized place invariants in 67 ms returned sat
[2023-03-11 15:12:21] [INFO ] After 400ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-11 15:12:21] [INFO ] [Nat]Absence check using 0 positive and 35 generalized place invariants in 77 ms returned sat
[2023-03-11 15:12:21] [INFO ] After 324ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-11 15:12:21] [INFO ] State equation strengthened by 15 read => feed constraints.
[2023-03-11 15:12:21] [INFO ] After 123ms SMT Verify possible using 15 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-11 15:12:22] [INFO ] After 288ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 86 ms.
[2023-03-11 15:12:22] [INFO ] After 876ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 21 ms.
Support contains 13 out of 319 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 319/319 places, 284/284 transitions.
Graph (complete) has 590 edges and 319 vertex of which 318 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.1 ms
Discarding 1 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 20 transitions
Trivial Post-agglo rules discarded 20 transitions
Performed 20 trivial Post agglomeration. Transition count delta: 20
Iterating post reduction 0 with 21 rules applied. Total rules applied 22 place count 318 transition count 263
Reduce places removed 20 places and 0 transitions.
Graph (complete) has 546 edges and 298 vertex of which 297 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 21 rules applied. Total rules applied 43 place count 297 transition count 263
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 44 place count 297 transition count 262
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 46 place count 295 transition count 260
Iterating global reduction 3 with 2 rules applied. Total rules applied 48 place count 295 transition count 260
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 3 with 1 rules applied. Total rules applied 49 place count 295 transition count 259
Reduce places removed 1 places and 0 transitions.
Graph (complete) has 540 edges and 294 vertex of which 292 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.1 ms
Discarding 2 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 2 rules applied. Total rules applied 51 place count 292 transition count 259
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 53 place count 292 transition count 257
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 6 with 1 rules applied. Total rules applied 54 place count 292 transition count 256
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 55 place count 291 transition count 256
Reduce places removed 3 places and 3 transitions.
Iterating global reduction 7 with 3 rules applied. Total rules applied 58 place count 288 transition count 253
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 59 place count 287 transition count 253
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 8 with 11 Pre rules applied. Total rules applied 59 place count 287 transition count 242
Deduced a syphon composed of 11 places in 3 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 8 with 22 rules applied. Total rules applied 81 place count 276 transition count 242
Applied a total of 81 rules in 149 ms. Remains 276 /319 variables (removed 43) and now considering 242/284 (removed 42) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 149 ms. Remains : 276/319 places, 242/284 transitions.
Incomplete random walk after 10000 steps, including 40 resets, run finished after 147 ms. (steps per millisecond=68 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 9 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 8 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 242 rows 276 cols
[2023-03-11 15:12:22] [INFO ] Computed 34 place invariants in 2 ms
[2023-03-11 15:12:22] [INFO ] [Real]Absence check using 0 positive and 34 generalized place invariants in 55 ms returned sat
[2023-03-11 15:12:22] [INFO ] After 298ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-11 15:12:23] [INFO ] [Nat]Absence check using 0 positive and 34 generalized place invariants in 84 ms returned sat
[2023-03-11 15:12:23] [INFO ] After 155ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-11 15:12:23] [INFO ] State equation strengthened by 5 read => feed constraints.
[2023-03-11 15:12:23] [INFO ] After 40ms SMT Verify possible using 5 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-11 15:12:23] [INFO ] After 144ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 41 ms.
[2023-03-11 15:12:23] [INFO ] After 513ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 9 out of 276 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 276/276 places, 242/242 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 276 transition count 235
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 14 place count 269 transition count 235
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 15 place count 268 transition count 234
Iterating global reduction 2 with 1 rules applied. Total rules applied 16 place count 268 transition count 234
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 1 rules applied. Total rules applied 17 place count 268 transition count 233
Reduce places removed 1 places and 0 transitions.
Graph (complete) has 486 edges and 267 vertex of which 265 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.0 ms
Discarding 2 places :
Also discarding 0 output transitions
Iterating post reduction 3 with 2 rules applied. Total rules applied 19 place count 265 transition count 233
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 21 place count 265 transition count 231
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 5 with 1 rules applied. Total rules applied 22 place count 265 transition count 230
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 23 place count 264 transition count 230
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 25 place count 262 transition count 228
Applied a total of 25 rules in 52 ms. Remains 262 /276 variables (removed 14) and now considering 228/242 (removed 14) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 53 ms. Remains : 262/276 places, 228/242 transitions.
Incomplete random walk after 10000 steps, including 42 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 10 resets, run finished after 13 ms. (steps per millisecond=769 ) properties (out of 1) seen :0
Finished probabilistic random walk after 90138 steps, run visited all 1 properties in 539 ms. (steps per millisecond=167 )
Probabilistic random walk after 90138 steps, saw 23917 distinct states, run finished after 539 ms. (steps per millisecond=167 ) properties seen :1
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-11 15:12:24] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 55 ms
FORMULA HirschbergSinclair-PT-30-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 38 ms
[2023-03-11 15:12:24] [INFO ] Input system was already deterministic with 569 transitions.
Support contains 107 out of 604 places (down from 118) after GAL structural reductions.
Computed a total of 604 stabilizing places and 569 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 604 transition count 569
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
FORMULA HirschbergSinclair-PT-30-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 588 transition count 553
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 588 transition count 553
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 40 place count 580 transition count 545
Iterating global reduction 0 with 8 rules applied. Total rules applied 48 place count 580 transition count 545
Applied a total of 48 rules in 59 ms. Remains 580 /604 variables (removed 24) and now considering 545/569 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 61 ms. Remains : 580/604 places, 545/569 transitions.
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 30 ms
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 32 ms
[2023-03-11 15:12:24] [INFO ] Input system was already deterministic with 545 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Reduce places removed 28 places and 28 transitions.
Drop transitions removed 225 transitions
Trivial Post-agglo rules discarded 225 transitions
Performed 225 trivial Post agglomeration. Transition count delta: 225
Iterating post reduction 0 with 225 rules applied. Total rules applied 225 place count 576 transition count 316
Reduce places removed 225 places and 0 transitions.
Iterating post reduction 1 with 225 rules applied. Total rules applied 450 place count 351 transition count 316
Discarding 16 places :
Symmetric choice reduction at 2 with 16 rule applications. Total rules 466 place count 335 transition count 300
Iterating global reduction 2 with 16 rules applied. Total rules applied 482 place count 335 transition count 300
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 2 with 7 rules applied. Total rules applied 489 place count 335 transition count 293
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 3 with 7 rules applied. Total rules applied 496 place count 328 transition count 293
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 497 place count 327 transition count 292
Iterating global reduction 4 with 1 rules applied. Total rules applied 498 place count 327 transition count 292
Applied a total of 498 rules in 61 ms. Remains 327 /604 variables (removed 277) and now considering 292/569 (removed 277) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 61 ms. Remains : 327/604 places, 292/569 transitions.
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 13 ms
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 14 ms
[2023-03-11 15:12:24] [INFO ] Input system was already deterministic with 292 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Reduce places removed 30 places and 30 transitions.
Drop transitions removed 239 transitions
Trivial Post-agglo rules discarded 239 transitions
Performed 239 trivial Post agglomeration. Transition count delta: 239
Iterating post reduction 0 with 239 rules applied. Total rules applied 239 place count 574 transition count 300
Reduce places removed 239 places and 0 transitions.
Iterating post reduction 1 with 239 rules applied. Total rules applied 478 place count 335 transition count 300
Discarding 15 places :
Symmetric choice reduction at 2 with 15 rule applications. Total rules 493 place count 320 transition count 285
Iterating global reduction 2 with 15 rules applied. Total rules applied 508 place count 320 transition count 285
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 516 place count 320 transition count 277
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 524 place count 312 transition count 277
Applied a total of 524 rules in 37 ms. Remains 312 /604 variables (removed 292) and now considering 277/569 (removed 292) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 38 ms. Remains : 312/604 places, 277/569 transitions.
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 11 ms
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 13 ms
[2023-03-11 15:12:24] [INFO ] Input system was already deterministic with 277 transitions.
Finished random walk after 36 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=18 )
FORMULA HirschbergSinclair-PT-30-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Reduce places removed 29 places and 29 transitions.
Drop transitions removed 228 transitions
Trivial Post-agglo rules discarded 228 transitions
Performed 228 trivial Post agglomeration. Transition count delta: 228
Iterating post reduction 0 with 228 rules applied. Total rules applied 228 place count 575 transition count 312
Reduce places removed 228 places and 0 transitions.
Iterating post reduction 1 with 228 rules applied. Total rules applied 456 place count 347 transition count 312
Discarding 15 places :
Symmetric choice reduction at 2 with 15 rule applications. Total rules 471 place count 332 transition count 297
Iterating global reduction 2 with 15 rules applied. Total rules applied 486 place count 332 transition count 297
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 494 place count 332 transition count 289
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 502 place count 324 transition count 289
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 503 place count 323 transition count 288
Iterating global reduction 4 with 1 rules applied. Total rules applied 504 place count 323 transition count 288
Applied a total of 504 rules in 46 ms. Remains 323 /604 variables (removed 281) and now considering 288/569 (removed 281) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 47 ms. Remains : 323/604 places, 288/569 transitions.
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 12 ms
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 12 ms
[2023-03-11 15:12:24] [INFO ] Input system was already deterministic with 288 transitions.
Starting structural reductions in LTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 590 transition count 555
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 590 transition count 555
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 34 place count 584 transition count 549
Iterating global reduction 0 with 6 rules applied. Total rules applied 40 place count 584 transition count 549
Applied a total of 40 rules in 57 ms. Remains 584 /604 variables (removed 20) and now considering 549/569 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 57 ms. Remains : 584/604 places, 549/569 transitions.
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 27 ms
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 27 ms
[2023-03-11 15:12:24] [INFO ] Input system was already deterministic with 549 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Reduce places removed 25 places and 25 transitions.
Drop transitions removed 202 transitions
Trivial Post-agglo rules discarded 202 transitions
Performed 202 trivial Post agglomeration. Transition count delta: 202
Iterating post reduction 0 with 202 rules applied. Total rules applied 202 place count 579 transition count 342
Reduce places removed 202 places and 0 transitions.
Iterating post reduction 1 with 202 rules applied. Total rules applied 404 place count 377 transition count 342
Discarding 15 places :
Symmetric choice reduction at 2 with 15 rule applications. Total rules 419 place count 362 transition count 327
Iterating global reduction 2 with 15 rules applied. Total rules applied 434 place count 362 transition count 327
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 2 with 7 rules applied. Total rules applied 441 place count 362 transition count 320
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 3 with 7 rules applied. Total rules applied 448 place count 355 transition count 320
Applied a total of 448 rules in 38 ms. Remains 355 /604 variables (removed 249) and now considering 320/569 (removed 249) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 39 ms. Remains : 355/604 places, 320/569 transitions.
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 12 ms
[2023-03-11 15:12:24] [INFO ] Flatten gal took : 13 ms
[2023-03-11 15:12:25] [INFO ] Input system was already deterministic with 320 transitions.
Starting structural reductions in LTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 590 transition count 555
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 590 transition count 555
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 35 place count 583 transition count 548
Iterating global reduction 0 with 7 rules applied. Total rules applied 42 place count 583 transition count 548
Applied a total of 42 rules in 56 ms. Remains 583 /604 variables (removed 21) and now considering 548/569 (removed 21) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 583/604 places, 548/569 transitions.
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 21 ms
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 21 ms
[2023-03-11 15:12:25] [INFO ] Input system was already deterministic with 548 transitions.
Starting structural reductions in LTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 589 transition count 554
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 589 transition count 554
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 37 place count 582 transition count 547
Iterating global reduction 0 with 7 rules applied. Total rules applied 44 place count 582 transition count 547
Applied a total of 44 rules in 55 ms. Remains 582 /604 variables (removed 22) and now considering 547/569 (removed 22) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 582/604 places, 547/569 transitions.
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 20 ms
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 18 ms
[2023-03-11 15:12:25] [INFO ] Input system was already deterministic with 547 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Reduce places removed 26 places and 26 transitions.
Drop transitions removed 204 transitions
Trivial Post-agglo rules discarded 204 transitions
Performed 204 trivial Post agglomeration. Transition count delta: 204
Iterating post reduction 0 with 204 rules applied. Total rules applied 204 place count 578 transition count 339
Reduce places removed 204 places and 0 transitions.
Iterating post reduction 1 with 204 rules applied. Total rules applied 408 place count 374 transition count 339
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 422 place count 360 transition count 325
Iterating global reduction 2 with 14 rules applied. Total rules applied 436 place count 360 transition count 325
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 2 with 6 rules applied. Total rules applied 442 place count 360 transition count 319
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 3 with 6 rules applied. Total rules applied 448 place count 354 transition count 319
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 449 place count 353 transition count 318
Iterating global reduction 4 with 1 rules applied. Total rules applied 450 place count 353 transition count 318
Applied a total of 450 rules in 41 ms. Remains 353 /604 variables (removed 251) and now considering 318/569 (removed 251) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 42 ms. Remains : 353/604 places, 318/569 transitions.
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 10 ms
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 10 ms
[2023-03-11 15:12:25] [INFO ] Input system was already deterministic with 318 transitions.
Starting structural reductions in LTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 589 transition count 554
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 589 transition count 554
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 38 place count 581 transition count 546
Iterating global reduction 0 with 8 rules applied. Total rules applied 46 place count 581 transition count 546
Applied a total of 46 rules in 65 ms. Remains 581 /604 variables (removed 23) and now considering 546/569 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 65 ms. Remains : 581/604 places, 546/569 transitions.
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 19 ms
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 19 ms
[2023-03-11 15:12:25] [INFO ] Input system was already deterministic with 546 transitions.
Starting structural reductions in LTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 590 transition count 555
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 590 transition count 555
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 35 place count 583 transition count 548
Iterating global reduction 0 with 7 rules applied. Total rules applied 42 place count 583 transition count 548
Applied a total of 42 rules in 58 ms. Remains 583 /604 variables (removed 21) and now considering 548/569 (removed 21) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 58 ms. Remains : 583/604 places, 548/569 transitions.
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 16 ms
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 17 ms
[2023-03-11 15:12:25] [INFO ] Input system was already deterministic with 548 transitions.
Starting structural reductions in LTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 589 transition count 554
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 589 transition count 554
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 37 place count 582 transition count 547
Iterating global reduction 0 with 7 rules applied. Total rules applied 44 place count 582 transition count 547
Applied a total of 44 rules in 53 ms. Remains 582 /604 variables (removed 22) and now considering 547/569 (removed 22) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 53 ms. Remains : 582/604 places, 547/569 transitions.
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 15 ms
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 16 ms
[2023-03-11 15:12:25] [INFO ] Input system was already deterministic with 547 transitions.
Starting structural reductions in LTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 588 transition count 553
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 588 transition count 553
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 40 place count 580 transition count 545
Iterating global reduction 0 with 8 rules applied. Total rules applied 48 place count 580 transition count 545
Applied a total of 48 rules in 52 ms. Remains 580 /604 variables (removed 24) and now considering 545/569 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 52 ms. Remains : 580/604 places, 545/569 transitions.
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 15 ms
[2023-03-11 15:12:25] [INFO ] Flatten gal took : 16 ms
[2023-03-11 15:12:25] [INFO ] Input system was already deterministic with 545 transitions.
Starting structural reductions in LTL mode, iteration 0 : 604/604 places, 569/569 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 589 transition count 554
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 589 transition count 554
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 37 place count 582 transition count 547
Iterating global reduction 0 with 7 rules applied. Total rules applied 44 place count 582 transition count 547
Applied a total of 44 rules in 52 ms. Remains 582 /604 variables (removed 22) and now considering 547/569 (removed 22) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 52 ms. Remains : 582/604 places, 547/569 transitions.
[2023-03-11 15:12:26] [INFO ] Flatten gal took : 15 ms
[2023-03-11 15:12:26] [INFO ] Flatten gal took : 16 ms
[2023-03-11 15:12:26] [INFO ] Input system was already deterministic with 547 transitions.
[2023-03-11 15:12:26] [INFO ] Flatten gal took : 20 ms
[2023-03-11 15:12:26] [INFO ] Flatten gal took : 19 ms
[2023-03-11 15:12:26] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-11 15:12:26] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 604 places, 569 transitions and 1704 arcs took 4 ms.
Total runtime 22049 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HirschbergSinclair-PT-30
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA HirschbergSinclair-PT-30-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-30-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-30-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-30-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-30-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678548648958
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
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lola: Rule S: 0 transitions removed,0 places removed
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lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 50 (type EXCL) for 49 HirschbergSinclair-PT-30-CTLFireability-14
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 50 (type EXCL) for HirschbergSinclair-PT-30-CTLFireability-14
lola: result : true
lola: markings : 534
lola: fired transitions : 1600
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 HirschbergSinclair-PT-30-CTLFireability-01
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 4 (type EXCL) for HirschbergSinclair-PT-30-CTLFireability-01
lola: result : true
lola: markings : 284
lola: fired transitions : 853
lola: time used : 0.000000
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lola: LAUNCH task # 45 (type EXCL) for 34 HirschbergSinclair-PT-30-CTLFireability-13
lola: time limit : 239 sec
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lola: FINISHED task # 45 (type EXCL) for HirschbergSinclair-PT-30-CTLFireability-13
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 41 (type EXCL) for 34 HirschbergSinclair-PT-30-CTLFireability-13
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: FINISHED task # 41 (type EXCL) for HirschbergSinclair-PT-30-CTLFireability-13
lola: result : true
lola: markings : 567
lola: fired transitions : 595
lola: time used : 0.000000
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lola: LAUNCH task # 25 (type EXCL) for 24 HirschbergSinclair-PT-30-CTLFireability-10
lola: time limit : 327 sec
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lola: FINISHED task # 25 (type EXCL) for HirschbergSinclair-PT-30-CTLFireability-10
lola: result : true
lola: markings : 615
lola: fired transitions : 615
lola: time used : 0.000000
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lola: LAUNCH task # 10 (type EXCL) for 9 HirschbergSinclair-PT-30-CTLFireability-04
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
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10 CTL EXCL 5/359 2/32 HirschbergSinclair-PT-30-CTLFireability-04 187897 m, 37579 m/sec, 989097 t fired, .
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10 CTL EXCL 10/359 3/32 HirschbergSinclair-PT-30-CTLFireability-04 366894 m, 35799 m/sec, 2063770 t fired, .
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10 CTL EXCL 15/359 4/32 HirschbergSinclair-PT-30-CTLFireability-04 545259 m, 35673 m/sec, 3137258 t fired, .
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10 CTL EXCL 20/359 5/32 HirschbergSinclair-PT-30-CTLFireability-04 722591 m, 35466 m/sec, 4209872 t fired, .
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HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
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10 CTL EXCL 40/359 9/32 HirschbergSinclair-PT-30-CTLFireability-04 1286483 m, 27983 m/sec, 8029051 t fired, .
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HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
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HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
HirschbergSinclair-PT-30-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-30-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-30-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-05: SP ECTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-30-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 105/2639 25/32 HirschbergSinclair-PT-30-CTLFireability-03 5845109 m, 49586 m/sec, 36709663 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
HirschbergSinclair-PT-30-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-30-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-30-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-05: SP ECTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-30-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 110/2639 26/32 HirschbergSinclair-PT-30-CTLFireability-03 6061898 m, 43357 m/sec, 38485200 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
HirschbergSinclair-PT-30-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-30-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-30-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-05: SP ECTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-30-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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7 CTL EXCL 115/2639 27/32 HirschbergSinclair-PT-30-CTLFireability-03 6308772 m, 49374 m/sec, 40253186 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
HirschbergSinclair-PT-30-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-30-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-30-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-05: SP ECTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-30-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 120/2639 29/32 HirschbergSinclair-PT-30-CTLFireability-03 6605240 m, 59293 m/sec, 42015073 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
HirschbergSinclair-PT-30-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-30-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-30-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-05: SP ECTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-30-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 125/2639 30/32 HirschbergSinclair-PT-30-CTLFireability-03 6890920 m, 57136 m/sec, 43767072 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
HirschbergSinclair-PT-30-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-30-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-30-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-05: SP ECTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-30-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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7 CTL EXCL 130/2639 31/32 HirschbergSinclair-PT-30-CTLFireability-03 7156324 m, 53080 m/sec, 45518538 t fired, .
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HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
HirschbergSinclair-PT-30-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-30-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-30-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-05: SP ECTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-30-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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7 CTL EXCL 135/2639 32/32 HirschbergSinclair-PT-30-CTLFireability-03 7400314 m, 48798 m/sec, 47288683 t fired, .
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lola: CANCELED task # 7 (type EXCL) for HirschbergSinclair-PT-30-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
HirschbergSinclair-PT-30-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-30-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-05: SP ECTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-30-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-30-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-30-CTLFireability-00: CTL unknown AGGR
HirschbergSinclair-PT-30-CTLFireability-01: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-03: CTL unknown AGGR
HirschbergSinclair-PT-30-CTLFireability-04: CTL unknown AGGR
HirschbergSinclair-PT-30-CTLFireability-05: SP ECTL unknown AGGR
HirschbergSinclair-PT-30-CTLFireability-07: CTL unknown AGGR
HirschbergSinclair-PT-30-CTLFireability-08: CTL unknown AGGR
HirschbergSinclair-PT-30-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-30-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-12: DISJ unknown DISJ
HirschbergSinclair-PT-30-CTLFireability-13: DISJ true DISJ
HirschbergSinclair-PT-30-CTLFireability-14: CTL true CTL model checker
HirschbergSinclair-PT-30-CTLFireability-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-30"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HirschbergSinclair-PT-30, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840346000466"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-30.tgz
mv HirschbergSinclair-PT-30 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;