MCC'2023- Execution of r199-smll-167840346000442

About the Execution of LoLa+red for HirschbergSinclair-PT-15

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
2502.943	3600000.00	511113.00	10759.60	FTFFF?F?FT?FT???	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r199-smll
Waiting for the VM to be ready (probing
...........................................
.....................
===========================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HirschbergSinclair-PT-15,
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-16784034600
===========================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 616K
-rw-r--r-- 1 mcc users 9.1K Feb 26
-rw-r--r-- 1 mcc users 78K Feb 26
-rw-r--r-- 1 mcc users 10K Feb 26
-rw-r--r-- 1 mcc users 68K Feb 26
-rw-r--r-- 1 mcc users 5.6K Feb 25
-rw-r--r-- 1 mcc users 30K Feb 25
-rw-r--r-- 1 mcc users 3.5K Feb 25
-rw-r--r-- 1 mcc users 19K Feb 25
-rw-r--r-- 1 mcc users 14K Feb 26
-rw-r--r-- 1 mcc users 103K Feb 26
-rw-r--r-- 1 mcc users 8.8K Feb 26
-rw-r--r-- 1 mcc users 46K Feb 26
-rw-r--r-- 1 mcc users 2.0K Feb 25
-rw-r--r-- 1 mcc users 4.1K Feb 25
-rw-r--r-- 1 mcc users 6 Mar 5
-rw-r--r-- 1 mcc users 3 Mar 5
-rw-r--r-- 1 mcc users 6 Mar 5
-rw-r--r-- 1 mcc users 173K Mar 5

--------------------
content from stdout:

=== Data for post analysis generated

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi
FORMULA_NAME HirschbergSinclair-PT-15-CTLFi

=== Now, execution of the tool begins

BK_START 1678540643730

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-15
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 13:17:27] [INFO ] Running
[2023-03-11 13:17:27] [INFO ] Parsing
[2023-03-11 13:17:27] [INFO ] Load
[2023-03-11 13:17:27] [INFO ] Transformed
[2023-03-11 13:17:27] [INFO ] Transformed
[2023-03-11 13:17:27] [INFO ] Parsed
Parsed 16 properties from file /home/mcc/ex
Support contains 138 out of 330 places.
Starting structural reductions in
Reduce places removed 15 places and
Iterating post reduction 0 with 15
Discarding 3 places :
Symmetric choice reduction at 1 with
Iterating global reduction 1 with
Applied a total of 21 rules in 111
// Phase 1: matrix 293 rows 312 cols
[2023-03-11 13:17:27] [INFO ] Computed
[2023-03-11 13:17:28] [INFO ] Implicit
[2023-03-11 13:17:28] [INFO ] Invariant
[2023-03-11 13:17:29] [INFO ] Implicit
Implicit Place search using SMT with
[2023-03-11 13:17:29] [INFO ] Invariant
[2023-03-11 13:17:29] [INFO ] Dead
Starting structural reductions in
Finished structural reductions in
Support contains 138 out of 312 places
[2023-03-11 13:17:30] [INFO ] Flatten
[2023-03-11 13:17:30] [INFO ] Flatten
[2023-03-11 13:17:30] [INFO ] Input
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Running SMT prover for 7 properties.
[2023-03-11 13:17:32] [INFO ] Invariant
[2023-03-11 13:17:32] [INFO ] [Real]Absence
[2023-03-11 13:17:32] [INFO ] After
[2023-03-11 13:17:33] [INFO ] [Nat]Absence
[2023-03-11 13:17:33] [INFO ] After
[2023-03-11 13:17:33] [INFO ] After
Attempting to minimize the solution found.
Minimization took 48 ms.
[2023-03-11 13:17:33] [INFO ] After
Fused 7 Parikh solutions to 1 different
Parikh walk visited 0 properties in 6 ms.
Support contains 12 out of 312 places.
Starting structural reductions in
Graph (complete) has 579 edges and
Discarding 2 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed
Drop transitions removed 78 transitions
Trivial Post-agglo rules discarded
Performed 78 trivial Post agglomeration.
Iterating post reduction 0 with 80
Reduce places removed 78 places and
Graph (complete) has 406 edges and
Discarding 14 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 79
Drop transitions removed 14 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with 14
Discarding 12 places :
Symmetric choice reduction at 3 with
Iterating global reduction 3 with
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded
Performed 3 trivial Post agglomeration.
Iterating post reduction 3 with 3
Reduce places removed 3 places and
Graph (complete) has 361 edges and
Discarding 4 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 4
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed
Iterating post reduction 5 with 4
Discarding 9 places :
Symmetric choice reduction at 6 with
Iterating global reduction 6 with
Discarding 2 places :
Symmetric choice reduction at 6 with
Iterating global reduction 6 with
Free-agglomeration rule (complex)
Iterating global reduction 6 with
Reduce places removed 12 places and
Iterating post reduction 6 with 12
Reduce places removed 10 places and
Iterating global reduction 7 with
Reduce places removed 1 places and
Iterating post reduction 7 with 1
Performed 9 Pre agglomeration using
Pre-agglomeration after 8 with 9 Pre
Deduced a syphon composed of 9 places
Reduce places removed 9 places and
Iterating global reduction 8 with
Applied a total of 284 rules in 147
Finished structural reductions in
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Interrupted probabilistic random walk after 1345742
Probabilistic random walk after 1345742
Running SMT prover for 1 properties.
// Phase 1: matrix 138 rows 156 cols
[2023-03-11 13:17:36] [INFO ] Computed
[2023-03-11 13:17:36] [INFO ] [Real]Absence
[2023-03-11 13:17:36] [INFO ] [Real]Absence
[2023-03-11 13:17:36] [INFO ] After
[2023-03-11 13:17:36] [INFO ] [Nat]Absence
[2023-03-11 13:17:36] [INFO ] [Nat]Absence
[2023-03-11 13:17:37] [INFO ] After
[2023-03-11 13:17:37] [INFO ] After
Attempting to minimize the solution found.
Minimization took 29 ms.
[2023-03-11 13:17:37] [INFO ] After
Parikh walk visited 0 properties in 1 ms.
Support contains 12 out of 156 places.
Starting structural reductions in
Applied a total of 0 rules in 8 ms.
Finished structural reductions in
Starting structural reductions in
Applied a total of 0 rules in 7 ms.
[2023-03-11 13:17:37] [INFO ] Invariant
[2023-03-11 13:17:37] [INFO ] Implicit
[2023-03-11 13:17:37] [INFO ] Invariant
[2023-03-11 13:17:37] [INFO ] Implicit
Implicit Place search using SMT with
[2023-03-11 13:17:37] [INFO ] Redundant
[2023-03-11 13:17:37] [INFO ] Invariant
[2023-03-11 13:17:37] [INFO ] Dead
Finished structural reductions in
Ensure Unique test removed 3 places
Drop transitions removed 17 transitions
Trivial Post-agglo rules discarded
Performed 17 trivial Post agglomeration.
Iterating post reduction 0 with 20
Reduce places removed 17 places and
Iterating post reduction 1 with 17
Performed 31 Pre agglomeration using
Pre-agglomeration after 2 with 31
Deduced a syphon composed of 31 places
Ensure Unique test removed 1 places
Reduce places removed 32 places and
Iterating global reduction 2 with
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 2 with 1
Performed 1 Pre agglomeration using
Pre-agglomeration after 3 with 1 Pre
Deduced a syphon composed of 1 places
Reduce places removed 1 places and
Iterating global reduction 3 with
Discarding 1 places :
Symmetric choice reduction at 3 with
Iterating global reduction 3 with
Performed 5 Post agglomeration using
Deduced a syphon composed of 5 places
Reduce places removed 5 places and
Iterating global reduction 3 with
Applied a total of 115 rules in 39
Running SMT prover for 1 properties.
// Phase 1: matrix 83 rows 96 cols
[2023-03-11 13:17:38] [INFO ] Computed
[2023-03-11 13:17:38] [INFO ] [Real]Absence
[2023-03-11 13:17:38] [INFO ] [Real]Absence
[2023-03-11 13:17:38] [INFO ] After
[2023-03-11 13:17:38] [INFO ] [Nat]Absence
[2023-03-11 13:17:38] [INFO ] [Nat]Absence
[2023-03-11 13:17:38] [INFO ] After
[2023-03-11 13:17:38] [INFO ] After
Attempting to minimize the solution found.
Minimization took 27 ms.
[2023-03-11 13:17:38] [INFO ] After
Successfully simplified 6 atomic propositions
[2023-03-11 13:17:38] [INFO ] Flatten
[2023-03-11 13:17:38] [INFO ] Flatten
[2023-03-11 13:17:38] [INFO ] Input
Support contains 117 out of 312 places
FORMULA HirschbergSinclair-PT-15-CTLFireability-12
Computed a total of 312 stabilizing
Complete graph has no SCC; deadlocks
Detected that all paths lead to deadlock.
AF dead knowledge conclusive for 1
Starting structural reductions in
Reduce places removed 13 places and
Drop transitions removed 118 transitions
Trivial Post-agglo rules discarded
Performed 118 trivial Post agglomeration.
Iterating post reduction 0 with 118
Reduce places removed 118 places and
Iterating post reduction 1 with 118
Discarding 13 places :
Symmetric choice reduction at 2 with
Iterating global reduction 2 with
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded
Performed 2 trivial Post agglomeration.
Iterating post reduction 2 with 2
Reduce places removed 2 places and
Iterating post reduction 3 with 2
Applied a total of 266 rules in 46
Finished structural reductions in
[2023-03-11 13:17:38] [INFO ] Flatten
[2023-03-11 13:17:38] [INFO ] Flatten
[2023-03-11 13:17:38] [INFO ] Input
Starting structural reductions in
Discarding 15 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 52 rules in 49
Finished structural reductions in
[2023-03-11 13:17:38] [INFO ] Flatten
[2023-03-11 13:17:38] [INFO ] Flatten
[2023-03-11 13:17:38] [INFO ] Input
Starting structural reductions in
Discarding 14 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 50 rules in 32
Finished structural reductions in
[2023-03-11 13:17:38] [INFO ] Flatten
[2023-03-11 13:17:38] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Discarding 13 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 10 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 46 rules in 25
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Reduce places removed 15 places and
Drop transitions removed 124 transitions
Trivial Post-agglo rules discarded
Performed 124 trivial Post agglomeration.
Iterating post reduction 0 with 124
Reduce places removed 124 places and
Iterating post reduction 1 with 124
Discarding 15 places :
Symmetric choice reduction at 2 with
Iterating global reduction 2 with
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded
Performed 3 trivial Post agglomeration.
Iterating post reduction 2 with 3
Reduce places removed 3 places and
Iterating post reduction 3 with 3
Applied a total of 284 rules in 33
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Finished random walk after 142 steps,
FORMULA HirschbergSinclair-PT-15-CTLFireability-04
Starting structural reductions
Reduce places removed 12 places and
Drop transitions removed 101 transitions
Trivial Post-agglo rules discarded
Performed 101 trivial Post agglomeration.
Iterating post reduction 0 with 101
Reduce places removed 101 places and
Iterating post reduction 1 with 101
Discarding 14 places :
Symmetric choice reduction at 2 with
Iterating global reduction 2 with
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded
Performed 3 trivial Post agglomeration.
Iterating post reduction 2 with 3
Reduce places removed 3 places and
Iterating post reduction 3 with 3
Discarding 1 places :
Symmetric choice reduction at 4 with
Iterating global reduction 4 with
Applied a total of 238 rules in 35
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Discarding 13 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 10 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 46 rules in 29
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Discarding 15 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 52 rules in 27
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Discarding 15 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 52 rules in 28
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Discarding 13 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 9 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 44 rules in 26
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Discarding 14 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 50 rules in 25
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Discarding 15 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 12 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 54 rules in 26
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Discarding 14 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 11 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 50 rules in 34
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Discarding 15 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Discarding 12 places :
Symmetric choice reduction at 0 with
Iterating global reduction 0 with
Applied a total of 54 rules in 19
Finished structural reductions in
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Flatten
[2023-03-11 13:17:39] [INFO ] Input
Starting structural reductions in
Reduce places removed 14 places and
Drop transitions removed 114 transitions
Trivial Post-agglo rules discarded
Performed 114 trivial Post agglomeration.
Iterating post reduction 0 with 114
Reduce places removed 114 places and
Iterating post reduction 1 with 114
Discarding 14 places :
Symmetric choice reduction at 2 with
Iterating global reduction 2 with
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded
Performed 3 trivial Post agglomeration.
Iterating post reduction 2 with 3
Reduce places removed 3 places and
Iterating post reduction 3 with 3
Discarding 1 places :
Symmetric choice reduction at 4 with
Iterating global reduction 4 with
Applied a total of 264 rules in 30
Finished structural reductions in
[2023-03-11 13:17:40] [INFO ] Flatten
[2023-03-11 13:17:40] [INFO ] Flatten
[2023-03-11 13:17:40] [INFO ] Input
[2023-03-11 13:17:40] [INFO ] Flatten
[2023-03-11 13:17:40] [INFO ] Flatten
[2023-03-11 13:17:40] [INFO ] Export
[2023-03-11 13:17:40] [INFO ] Export
Total runtime 12992 ms.
There are residual formulas that ITS
starting LoLA
BK_INPUT HirschbergSinclair-PT-15
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../r
current directory: /home/mcc/execution/376
CTLFireability

FORMULA HirschbergSinclair-PT-15-CTLFireability-00

FORMULA HirschbergSinclair-PT-15-CTLFireability-03

FORMULA HirschbergSinclair-PT-15-CTLFireability-01

FORMULA HirschbergSinclair-PT-15-CTLFireability-11

FORMULA HirschbergSinclair-PT-15-CTLFireability-09

FORMULA HirschbergSinclair-PT-15-CTLFireability-08

FORMULA HirschbergSinclair-PT-15-CTLFireability-06

FORMULA HirschbergSinclair-PT-15-CTLFireability-02
TIME LIMIT: Killed by timeout
MemTotal: 16393216 kB
MemFree: 13648592 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16103256 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itst
+ PYTHONPATH=/home/mcc/BenchKit/itstools/py
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstoo
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bi
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//.
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/executio
lola: reading pnml
lola: PNML file contains place/transition
lola: finished parsing
lola: closed net file /home/mcc/execution
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/exec
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
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lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
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lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
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lola: rewrite Frontend/Parser/formula_rew
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lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
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lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: rewrite Frontend/Parser/formula_rew
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rew
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 37 (type CNST)
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 37 (type CNST)
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0
lola: Created skeleton in 0.000000 secs.
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========================== examination is CTLFireability 0442 ========================== 02:14 CTLCardinality.txt 02:14 CTLCardinality.xml 02:13 CTLFireability.txt 02:13 CTLFireability.xml 16:15 LTLCardinality.txt 16:15 LTLCardinality.xml 16:15 LTLFireability.txt 16:15 LTLFireability.xml 02:15 ReachabilityCardinality.txt 02:15 ReachabilityCardinality.xml 02:14 ReachabilityFireability.txt 02:14 ReachabilityFireability.xml 16:15 UpperBounds.txt 16:15 UpperBounds.xml 18:22 equiv_col 18:22 instance 18:22 iscolored 18:22 model.pnml by BenchKit (invocation template) result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML] pnml file : /home/mcc/execution/model.pnml time of PNML (sax parser for PT used): 116 ms 330 places. 296 transitions. PT model containing 330 places and 296 transitions and 906 arcs in 249 ms. ecution/CTLFireability.xml in 24 ms. Attempting structural reductions. LTL mode, iteration 0 : 330/330 places, 296/296 transitions. 0 transitions. rules applied. Total rules applied 15 place count 315 transition count 296 3 rule applications. Total rules 18 place count 312 transition count 293 3 rules applied. Total rules applied 21 place count 312 transition count 293 ms. Remains 312 /330 variables (removed 18) and now considering 293/296 (removed 3) transitions. 19 place invariants in 24 ms Places using invariants in 573 ms returned [] cache hit. Places using invariants and state equation in 946 ms returned [] State Equation took 1610 ms to find 0 implicit places. cache hit. Transitions using invariants and state equation in 383 ms found 0 transitions. LTL mode, iteration 1 : 312/330 places, 293/296 transitions. LTL mode , in 1 iterations and 2110 ms. Remains : 312/330 places, 293/296 transitions. after structural reductions. gal took : 145 ms gal took : 49 ms system was already deterministic with 293 transitions. steps, including 33 resets, run finished after 994 ms. (steps per millisecond=10 ) properties (out of 104) seen :96 steps, including 4 resets, run finished after 74 ms. (steps per millisecond=135 ) properties (out of 8) seen :1 steps, including 4 resets, run finished after 71 ms. (steps per millisecond=140 ) properties (out of 7) seen :0 steps, including 4 resets, run finished after 68 ms. (steps per millisecond=147 ) properties (out of 7) seen :0 steps, including 5 resets, run finished after 110 ms. (steps per millisecond=90 ) properties (out of 7) seen :0 steps, including 4 resets, run finished after 84 ms. (steps per millisecond=119 ) properties (out of 7) seen :0 steps, including 5 resets, run finished after 78 ms. (steps per millisecond=128 ) properties (out of 7) seen :0 steps, including 4 resets, run finished after 73 ms. (steps per millisecond=137 ) properties (out of 7) seen :0 steps, including 5 resets, run finished after 76 ms. (steps per millisecond=131 ) properties (out of 7) seen :0 cache hit. check using 0 positive and 19 generalized place invariants in 41 ms returned sat 726ms SMT Verify possible using all constraints in real domain returned unsat :6 sat :0 real:1 check using 0 positive and 19 generalized place invariants in 42 ms returned sat 238ms SMT Verify possible using state equation in natural domain returned unsat :6 sat :1 320ms SMT Verify possible using trap constraints in natural domain returned unsat :6 sat :1 558ms SMT Verify possible using all constraints in natural domain returned unsat :6 sat :1 solutions. Attempting structural reductions. REACHABILITY mode, iteration 0 : 312/312 places, 293/293 transitions. 312 vertex of which 310 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.4 ms 2 transitions. 78 transitions Transition count delta: 78 rules applied. Total rules applied 81 place count 310 transition count 213 0 transitions. 232 vertex of which 218 are kept as prefixes of interest. Removing 14 places using SCC suffix rule.1 ms rules applied. Total rules applied 160 place count 218 transition count 213 14 transitions. rules applied. Total rules applied 174 place count 218 transition count 199 12 rule applications. Total rules 186 place count 206 transition count 187 12 rules applied. Total rules applied 198 place count 206 transition count 187 3 transitions Transition count delta: 3 rules applied. Total rules applied 201 place count 206 transition count 184 0 transitions. 203 vertex of which 199 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.1 ms rules applied. Total rules applied 205 place count 199 transition count 184 4 transitions. rules applied. Total rules applied 209 place count 199 transition count 180 9 rule applications. Total rules 218 place count 190 transition count 171 9 rules applied. Total rules applied 227 place count 190 transition count 171 2 rule applications. Total rules 229 place count 188 transition count 169 2 rules applied. Total rules applied 231 place count 188 transition count 169 applied 12 times. 12 rules applied. Total rules applied 243 place count 188 transition count 157 0 transitions. rules applied. Total rules applied 255 place count 176 transition count 157 10 transitions. 10 rules applied. Total rules applied 265 place count 166 transition count 147 0 transitions. rules applied. Total rules applied 266 place count 165 transition count 147 Quasi-Persistent + Divergent Free condition.. rules applied. Total rules applied 266 place count 165 transition count 138 in 1 ms 0 transitions. 18 rules applied. Total rules applied 284 place count 156 transition count 138 ms. Remains 156 /312 variables (removed 156) and now considering 138/293 (removed 155) transitions. REACHABILITY mode , in 1 iterations and 147 ms. Remains : 156/312 places, 138/293 transitions. steps, including 64 resets, run finished after 58 ms. (steps per millisecond=172 ) properties (out of 1) seen :0 steps, including 14 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 1) seen :0 steps, run timeout after 3001 ms. (steps per millisecond=448 ) properties seen :{} steps, saw 259046 distinct states, run finished after 3002 ms. (steps per millisecond=448 ) properties seen :0 18 place invariants in 5 ms check using 1 positive place invariants in 2 ms returned sat check using 1 positive and 17 generalized place invariants in 23 ms returned sat 200ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1 check using 1 positive place invariants in 8 ms returned sat check using 1 positive and 17 generalized place invariants in 22 ms returned sat 88ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1 129ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1 240ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1 Attempting structural reductions. REACHABILITY mode, iteration 0 : 156/156 places, 138/138 transitions. Remains 156 /156 variables (removed 0) and now considering 138/138 (removed 0) transitions. REACHABILITY mode , in 1 iterations and 8 ms. Remains : 156/156 places, 138/138 transitions. REACHABILITY mode, iteration 0 : 156/156 places, 138/138 transitions. Remains 156 /156 variables (removed 0) and now considering 138/138 (removed 0) transitions. cache hit. Places using invariants in 175 ms returned [] cache hit. Places using invariants and state equation in 416 ms returned [] State Equation took 601 ms to find 0 implicit places. transitions in 7 ms returned [] cache hit. Transitions using invariants and state equation in 187 ms found 0 transitions. REACHABILITY mode , in 1 iterations and 814 ms. Remains : 156/156 places, 138/138 transitions. 17 transitions Transition count delta: 17 rules applied. Total rules applied 20 place count 153 transition count 121 0 transitions. rules applied. Total rules applied 37 place count 136 transition count 121 Quasi-Persistent + Divergent Free condition.. Pre rules applied. Total rules applied 37 place count 136 transition count 90 in 0 ms 0 transitions. 63 rules applied. Total rules applied 100 place count 104 transition count 90 rules applied. Total rules applied 101 place count 103 transition count 90 Quasi-Persistent + Divergent Free condition.. rules applied. Total rules applied 101 place count 103 transition count 89 in 1 ms 0 transitions. 2 rules applied. Total rules applied 103 place count 102 transition count 89 1 rule applications. Total rules 104 place count 101 transition count 88 1 rules applied. Total rules applied 105 place count 101 transition count 88 F-continuation condition.Transition count delta: 5 in 0 ms 0 transitions. 10 rules applied. Total rules applied 115 place count 96 transition count 83 ms. Remains 96 /156 variables (removed 60) and now considering 83/138 (removed 55) transitions. 13 place invariants in 2 ms check using 1 positive place invariants in 2 ms returned sat check using 1 positive and 12 generalized place invariants in 18 ms returned sat 70ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1 check using 1 positive place invariants in 1 ms returned sat check using 1 positive and 12 generalized place invariants in 17 ms returned sat 87ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1 121ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1 219ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1 for a total of 16 simplifications. gal took : 38 ms gal took : 42 ms system was already deterministic with 293 transitions. (down from 128) after GAL structural reductions. TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE places and 293 stable transitions are unavoidable. place count 312 transition count 293 Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false). formulas. SI_CTL mode, iteration 0 : 312/312 places, 293/293 transitions. 13 transitions. 118 transitions Transition count delta: 118 rules applied. Total rules applied 118 place count 299 transition count 162 0 transitions. rules applied. Total rules applied 236 place count 181 transition count 162 13 rule applications. Total rules 249 place count 168 transition count 149 13 rules applied. Total rules applied 262 place count 168 transition count 149 2 transitions Transition count delta: 2 rules applied. Total rules applied 264 place count 168 transition count 147 0 transitions. rules applied. Total rules applied 266 place count 166 transition count 147 ms. Remains 166 /312 variables (removed 146) and now considering 147/293 (removed 146) transitions. SI_CTL mode , in 1 iterations and 47 ms. Remains : 166/312 places, 147/293 transitions. gal took : 17 ms gal took : 19 ms system was already deterministic with 147 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 15 rule applications. Total rules 15 place count 297 transition count 278 15 rules applied. Total rules applied 30 place count 297 transition count 278 11 rule applications. Total rules 41 place count 286 transition count 267 11 rules applied. Total rules applied 52 place count 286 transition count 267 ms. Remains 286 /312 variables (removed 26) and now considering 267/293 (removed 26) transitions. LTL mode , in 1 iterations and 49 ms. Remains : 286/312 places, 267/293 transitions. gal took : 31 ms gal took : 31 ms system was already deterministic with 267 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 14 rule applications. Total rules 14 place count 298 transition count 279 14 rules applied. Total rules applied 28 place count 298 transition count 279 11 rule applications. Total rules 39 place count 287 transition count 268 11 rules applied. Total rules applied 50 place count 287 transition count 268 ms. Remains 287 /312 variables (removed 25) and now considering 268/293 (removed 25) transitions. LTL mode , in 1 iterations and 32 ms. Remains : 287/312 places, 268/293 transitions. gal took : 27 ms gal took : 31 ms system was already deterministic with 268 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 13 rule applications. Total rules 13 place count 299 transition count 280 13 rules applied. Total rules applied 26 place count 299 transition count 280 10 rule applications. Total rules 36 place count 289 transition count 270 10 rules applied. Total rules applied 46 place count 289 transition count 270 ms. Remains 289 /312 variables (removed 23) and now considering 270/293 (removed 23) transitions. LTL mode , in 1 iterations and 26 ms. Remains : 289/312 places, 270/293 transitions. gal took : 28 ms gal took : 29 ms system was already deterministic with 270 transitions. SI_CTL mode, iteration 0 : 312/312 places, 293/293 transitions. 15 transitions. 124 transitions Transition count delta: 124 rules applied. Total rules applied 124 place count 297 transition count 154 0 transitions. rules applied. Total rules applied 248 place count 173 transition count 154 15 rule applications. Total rules 263 place count 158 transition count 139 15 rules applied. Total rules applied 278 place count 158 transition count 139 3 transitions Transition count delta: 3 rules applied. Total rules applied 281 place count 158 transition count 136 0 transitions. rules applied. Total rules applied 284 place count 155 transition count 136 ms. Remains 155 /312 variables (removed 157) and now considering 136/293 (removed 157) transitions. SI_CTL mode , in 1 iterations and 33 ms. Remains : 155/312 places, 136/293 transitions. gal took : 8 ms gal took : 8 ms system was already deterministic with 136 transitions. including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=142 ) FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK in SI_CTL mode, iteration 0 : 312/312 places, 293/293 transitions. 12 transitions. 101 transitions Transition count delta: 101 rules applied. Total rules applied 101 place count 300 transition count 180 0 transitions. rules applied. Total rules applied 202 place count 199 transition count 180 14 rule applications. Total rules 216 place count 185 transition count 166 14 rules applied. Total rules applied 230 place count 185 transition count 166 3 transitions Transition count delta: 3 rules applied. Total rules applied 233 place count 185 transition count 163 0 transitions. rules applied. Total rules applied 236 place count 182 transition count 163 1 rule applications. Total rules 237 place count 181 transition count 162 1 rules applied. Total rules applied 238 place count 181 transition count 162 ms. Remains 181 /312 variables (removed 131) and now considering 162/293 (removed 131) transitions. SI_CTL mode , in 1 iterations and 35 ms. Remains : 181/312 places, 162/293 transitions. gal took : 8 ms gal took : 8 ms system was already deterministic with 162 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 13 rule applications. Total rules 13 place count 299 transition count 280 13 rules applied. Total rules applied 26 place count 299 transition count 280 10 rule applications. Total rules 36 place count 289 transition count 270 10 rules applied. Total rules applied 46 place count 289 transition count 270 ms. Remains 289 /312 variables (removed 23) and now considering 270/293 (removed 23) transitions. LTL mode , in 1 iterations and 29 ms. Remains : 289/312 places, 270/293 transitions. gal took : 14 ms gal took : 14 ms system was already deterministic with 270 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 15 rule applications. Total rules 15 place count 297 transition count 278 15 rules applied. Total rules applied 30 place count 297 transition count 278 11 rule applications. Total rules 41 place count 286 transition count 267 11 rules applied. Total rules applied 52 place count 286 transition count 267 ms. Remains 286 /312 variables (removed 26) and now considering 267/293 (removed 26) transitions. LTL mode , in 1 iterations and 27 ms. Remains : 286/312 places, 267/293 transitions. gal took : 14 ms gal took : 14 ms system was already deterministic with 267 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 15 rule applications. Total rules 15 place count 297 transition count 278 15 rules applied. Total rules applied 30 place count 297 transition count 278 11 rule applications. Total rules 41 place count 286 transition count 267 11 rules applied. Total rules applied 52 place count 286 transition count 267 ms. Remains 286 /312 variables (removed 26) and now considering 267/293 (removed 26) transitions. LTL mode , in 1 iterations and 28 ms. Remains : 286/312 places, 267/293 transitions. gal took : 12 ms gal took : 13 ms system was already deterministic with 267 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 13 rule applications. Total rules 13 place count 299 transition count 280 13 rules applied. Total rules applied 26 place count 299 transition count 280 9 rule applications. Total rules 35 place count 290 transition count 271 9 rules applied. Total rules applied 44 place count 290 transition count 271 ms. Remains 290 /312 variables (removed 22) and now considering 271/293 (removed 22) transitions. LTL mode , in 1 iterations and 26 ms. Remains : 290/312 places, 271/293 transitions. gal took : 13 ms gal took : 14 ms system was already deterministic with 271 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 14 rule applications. Total rules 14 place count 298 transition count 279 14 rules applied. Total rules applied 28 place count 298 transition count 279 11 rule applications. Total rules 39 place count 287 transition count 268 11 rules applied. Total rules applied 50 place count 287 transition count 268 ms. Remains 287 /312 variables (removed 25) and now considering 268/293 (removed 25) transitions. LTL mode , in 1 iterations and 25 ms. Remains : 287/312 places, 268/293 transitions. gal took : 13 ms gal took : 13 ms system was already deterministic with 268 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 15 rule applications. Total rules 15 place count 297 transition count 278 15 rules applied. Total rules applied 30 place count 297 transition count 278 12 rule applications. Total rules 42 place count 285 transition count 266 12 rules applied. Total rules applied 54 place count 285 transition count 266 ms. Remains 285 /312 variables (removed 27) and now considering 266/293 (removed 27) transitions. LTL mode , in 1 iterations and 27 ms. Remains : 285/312 places, 266/293 transitions. gal took : 13 ms gal took : 12 ms system was already deterministic with 266 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 14 rule applications. Total rules 14 place count 298 transition count 279 14 rules applied. Total rules applied 28 place count 298 transition count 279 11 rule applications. Total rules 39 place count 287 transition count 268 11 rules applied. Total rules applied 50 place count 287 transition count 268 ms. Remains 287 /312 variables (removed 25) and now considering 268/293 (removed 25) transitions. LTL mode , in 1 iterations and 34 ms. Remains : 287/312 places, 268/293 transitions. gal took : 12 ms gal took : 13 ms system was already deterministic with 268 transitions. LTL mode, iteration 0 : 312/312 places, 293/293 transitions. 15 rule applications. Total rules 15 place count 297 transition count 278 15 rules applied. Total rules applied 30 place count 297 transition count 278 12 rule applications. Total rules 42 place count 285 transition count 266 12 rules applied. Total rules applied 54 place count 285 transition count 266 ms. Remains 285 /312 variables (removed 27) and now considering 266/293 (removed 27) transitions. LTL mode , in 1 iterations and 19 ms. Remains : 285/312 places, 266/293 transitions. gal took : 12 ms gal took : 13 ms system was already deterministic with 266 transitions. SI_CTL mode, iteration 0 : 312/312 places, 293/293 transitions. 14 transitions. 114 transitions Transition count delta: 114 rules applied. Total rules applied 114 place count 298 transition count 165 0 transitions. rules applied. Total rules applied 228 place count 184 transition count 165 14 rule applications. Total rules 242 place count 170 transition count 151 14 rules applied. Total rules applied 256 place count 170 transition count 151 3 transitions Transition count delta: 3 rules applied. Total rules applied 259 place count 170 transition count 148 0 transitions. rules applied. Total rules applied 262 place count 167 transition count 148 1 rule applications. Total rules 263 place count 166 transition count 147 1 rules applied. Total rules applied 264 place count 166 transition count 147 ms. Remains 166 /312 variables (removed 146) and now considering 147/293 (removed 146) transitions. SI_CTL mode , in 1 iterations and 30 ms. Remains : 166/312 places, 147/293 transitions. gal took : 6 ms gal took : 7 ms system was already deterministic with 147 transitions. gal took : 13 ms gal took : 13 ms to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms. to PNML in file /home/mcc/execution/model.sr.pnml of net with 312 places, 293 transitions and 872 arcs took 3 ms. could not solve within timeout educer/bin//../../lola/bin/ FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT after 3600 seconds ools/pylibs libs /itstools/pylibs: ls/pylibs: n//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar ./../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML n/376/model.pnml net /376/model.pnml ution/376/CTLFireability.xml rite.k:550 rite.k:550 rite.k:317 rite.k:296 rite.k:322 rite.k:331 rite.k:322 rite.k:328 rite.k:296 rite.k:250 rite.k:250 rite.k:550 rite.k:322 rite.k:328 rite.k:296 rite.k:472 rite.k:325 rite.k:331 rite.k:299 rite.k:253 rite.k:325 rite.k:337 rite.k:325 rite.k:334 rite.k:296 rite.k:325 rite.k:337 rite.k:296 rite.k:296 rite.k:325 rite.k:337 rite.k:322 rite.k:337 rite.k:296 rite.k:296 rite.k:314 rite.k:325 rite.k:331 rite.k:296 rite.k:296 rite.k:544 rite.k:472 rite.k:325 rite.k:337 rite.k:325 rite.k:331 rite.k:296 rite.k:322 rite.k:334 rite.k:296 rite.k:253 rite.k:553 rite.k:553 rite.k:553 rite.k:325 rite.k:328 rite.k:296 rite.k:250 rite.k:250 rite.k:250 rite.k:98 rite.k:129 rite.k:196 rite.k:150 rite.k:322 rite.k:337 rite.k:296 rite.k:296 rite.k:544 rite.k:469 rite.k:322 rite.k:331 rite.k:296 rite.k:322 rite.k:331 rite.k:296 rite.k:317 rite.k:325 rite.k:337 rite.k:296 rite.k:296 rite.k:325 rite.k:328 rite.k:296 rite.k:469 for 34 HirschbergSinclair-PT-15-CTLFireability-11 for HirschbergSinclair-PT-15-CTLFireability-11 places removed rite.k:811 rite.k:809 for 0 HirschbergSinclair-PT-15-CTLFireability-00 rite.k:721 rite.k:787 rite.k:721 rite.k:787 rite.k:721 rite.k:787 for 9 HirschbergSinclair-PT-15-CTLFireability-03 for 9 HirschbergSinclair-PT-15-CTLFireability-03 for 9 HirschbergSinclair-PT-15-CTLFireability-03 rite.k:812 rite.k:812 rite.k:812 rite.k:812 rite.k:812 rite.k:808 rite.k:808 rite.k:807 rite.k:806 rite.k:808 rite.k:809 for HirschbergSinclair-PT-15-CTLFireability-00 101 101 0.000000 1 for 9 HirschbergSinclair-PT-15-CTLFireability-03 for HirschbergSinclair-PT-15-CTLFireability-03 99 99 0.000000 1 for HirschbergSinclair-PT-15-CTLFireability-03 (obsolete) for HirschbergSinclair-PT-15-CTLFireability-03 (obsolete) for HirschbergSinclair-PT-15-CTLFireability-03 (obsolete) for HirschbergSinclair-PT-15-CTLFireability-03 149 2 0.000000 0 for HirschbergSinclair-PT-15-CTLFireability-03 0.000000 1 for 3 HirschbergSinclair-PT-15-CTLFireability-01 rite.k:721 rite.k:787 for HirschbergSinclair-PT-15-CTLFireability-01 185 371 0.000000 1 rite.k:811 rite.k:813 rite.k:808 rite.k:813 rite.k:808 ecution/376/CTLFireability-52.sara. is non-deterministic for 12 HirschbergSinclair-PT-15-CTLFireability-05 rite.k:812 rite.k:807 rite.k:811 rite.k:812 rite.k:815 rite.k:815 rite.k:813 rite.k:810 rite.k:813 rite.k:815 rite.k:813 rite.k:808 rite.k:808 rite.k:808 rite.k:814 rite.k:814 rite.k:813 rite.k:807 rite.k:815 rite.k:807 rite.k:807 rite.k:807 rite.k:807 rite.k:807 rite.k:806 rite.k:807 rite.k:806 rite.k:808 rite.k:812 rite.k:809 rite.k:815 rite.k:811 rite.k:814 rite.k:811 rite.k:814 rite.k:808 rite.k:807 for HirschbergSinclair-PT-15-CTLFireability-03 rite.k:807 rite.k:813 rite.k:810 rite.k:806 rite.k:813 rite.k:811 rite.k:807 rite.k:806 rite.k:814 rite.k:812 rite.k:806 rite.k:809 rite.k:814 rite.k:814 rite.k:807 rite.k:811 rite.k:806 rite.k:811 rite.k:806 rite.k:811 rite.k:806 rite.k:812 rite.k:811 rite.k:813 rite.k:809 rite.k:806 rite.k:814 rite.k:811 rite.k:809 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 HirschbergSinclair-PT-15-CTLFireability-05 834053 m, 166810 m/sec, 2343732 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 HirschbergSinclair-PT-15-CTLFireability-05 1734208 m, 180031 m/sec, 4876978 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 HirschbergSinclair-PT-15-CTLFireability-05 2575906 m, 168339 m/sec, 7327544 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 HirschbergSinclair-PT-15-CTLFireability-05 3415456 m, 167910 m/sec, 9737396 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 HirschbergSinclair-PT-15-CTLFireability-05 4171819 m, 151272 m/sec, 12112579 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 HirschbergSinclair-PT-15-CTLFireability-05 4982211 m, 162078 m/sec, 14459356 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 HirschbergSinclair-PT-15-CTLFireability-05 5649856 m, 133529 m/sec, 16858375 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 HirschbergSinclair-PT-15-CTLFireability-05 6244666 m, 118962 m/sec, 19254800 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 HirschbergSinclair-PT-15-CTLFireability-05 6996875 m, 150441 m/sec, 21630124 t fired, . for HirschbergSinclair-PT-15-CTLFireability-05 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS for 44 HirschbergSinclair-PT-15-CTLFireability-14 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 HirschbergSinclair-PT-15-CTLFireability-14 434765 m, 86953 m/sec, 1838097 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 HirschbergSinclair-PT-15-CTLFireability-14 898356 m, 92718 m/sec, 3798266 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 HirschbergSinclair-PT-15-CTLFireability-14 1358503 m, 92029 m/sec, 5722955 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 HirschbergSinclair-PT-15-CTLFireability-14 1805340 m, 89367 m/sec, 7635649 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 HirschbergSinclair-PT-15-CTLFireability-14 2270111 m, 92954 m/sec, 9555521 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 HirschbergSinclair-PT-15-CTLFireability-14 2725770 m, 91131 m/sec, 11446745 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 HirschbergSinclair-PT-15-CTLFireability-14 3165915 m, 88029 m/sec, 13336057 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 HirschbergSinclair-PT-15-CTLFireability-14 3628711 m, 92559 m/sec, 15239005 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 HirschbergSinclair-PT-15-CTLFireability-14 4090758 m, 92409 m/sec, 17150444 t fired, . VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 HirschbergSinclair-PT-15-CTLFireability-14 4545190 m, 90886 m/sec, 19058412 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 HirschbergSinclair-PT-15-CTLFireability-14 5009372 m, 92836 m/sec, 20976100 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 HirschbergSinclair-PT-15-CTLFireability-14 5461729 m, 90471 m/sec, 22890861 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 HirschbergSinclair-PT-15-CTLFireability-14 5888977 m, 85449 m/sec, 24766848 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 HirschbergSinclair-PT-15-CTLFireability-14 6311118 m, 84428 m/sec, 26648818 t fired, . in use: 32 for HirschbergSinclair-PT-15-CTLFireability-14 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CONJ 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 for 34 HirschbergSinclair-PT-15-CTLFireability-11 for HirschbergSinclair-PT-15-CTLFireability-11 255 763 0.000000 1 for 27 HirschbergSinclair-PT-15-CTLFireability-10 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 1 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 HirschbergSinclair-PT-15-CTLFireability-10 969919 m, 193983 m/sec, 1700335 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 1 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 HirschbergSinclair-PT-15-CTLFireability-10 1952686 m, 196553 m/sec, 3449279 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 1 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 HirschbergSinclair-PT-15-CTLFireability-10 2865816 m, 182626 m/sec, 5161502 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 1 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 HirschbergSinclair-PT-15-CTLFireability-10 3808070 m, 188450 m/sec, 6878364 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 1 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 HirschbergSinclair-PT-15-CTLFireability-10 4765466 m, 191479 m/sec, 8594202 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 1 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 HirschbergSinclair-PT-15-CTLFireability-10 5717511 m, 190409 m/sec, 10299885 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 1 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 HirschbergSinclair-PT-15-CTLFireability-10 6650694 m, 186636 m/sec, 11991313 t fired, . in use: 32 for HirschbergSinclair-PT-15-CTLFireability-10 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 for 27 HirschbergSinclair-PT-15-CTLFireability-10 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 HirschbergSinclair-PT-15-CTLFireability-10 534836 m, 106967 m/sec, 1789015 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 HirschbergSinclair-PT-15-CTLFireability-10 1011614 m, 95355 m/sec, 3721995 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 HirschbergSinclair-PT-15-CTLFireability-10 1420950 m, 81867 m/sec, 5664011 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 HirschbergSinclair-PT-15-CTLFireability-10 1892171 m, 94244 m/sec, 7589232 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 HirschbergSinclair-PT-15-CTLFireability-10 2372540 m, 96073 m/sec, 9521404 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 HirschbergSinclair-PT-15-CTLFireability-10 2849033 m, 95298 m/sec, 11441720 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 HirschbergSinclair-PT-15-CTLFireability-10 3334860 m, 97165 m/sec, 13375155 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 HirschbergSinclair-PT-15-CTLFireability-10 3827688 m, 98565 m/sec, 15294544 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 HirschbergSinclair-PT-15-CTLFireability-10 4358091 m, 106080 m/sec, 17194736 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 HirschbergSinclair-PT-15-CTLFireability-10 4893819 m, 107145 m/sec, 19111561 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 HirschbergSinclair-PT-15-CTLFireability-10 5417671 m, 104770 m/sec, 21139970 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 2 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 HirschbergSinclair-PT-15-CTLFireability-10 5970750 m, 110615 m/sec, 23177577 t fired, . in use: 32 for HirschbergSinclair-PT-15-CTLFireability-10 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 for 24 HirschbergSinclair-PT-15-CTLFireability-09 for HirschbergSinclair-PT-15-CTLFireability-09 2634 2694 0.000000 1 for 21 HirschbergSinclair-PT-15-CTLFireability-08 for HirschbergSinclair-PT-15-CTLFireability-08 0.000000 1 for 18 HirschbergSinclair-PT-15-CTLFireability-07 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 HirschbergSinclair-PT-15-CTLFireability-07 478636 m, 95727 m/sec, 1771510 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 HirschbergSinclair-PT-15-CTLFireability-07 965759 m, 97424 m/sec, 3744496 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 HirschbergSinclair-PT-15-CTLFireability-07 1315676 m, 69983 m/sec, 5486573 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 HirschbergSinclair-PT-15-CTLFireability-07 1741076 m, 85080 m/sec, 7322183 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 HirschbergSinclair-PT-15-CTLFireability-07 2072696 m, 66324 m/sec, 8914824 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 HirschbergSinclair-PT-15-CTLFireability-07 2468476 m, 79156 m/sec, 10669869 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 HirschbergSinclair-PT-15-CTLFireability-07 2798585 m, 66021 m/sec, 12400962 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 HirschbergSinclair-PT-15-CTLFireability-07 3215558 m, 83394 m/sec, 14021402 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 HirschbergSinclair-PT-15-CTLFireability-07 3567125 m, 70313 m/sec, 15603919 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 HirschbergSinclair-PT-15-CTLFireability-07 3895136 m, 65602 m/sec, 17199807 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 HirschbergSinclair-PT-15-CTLFireability-07 4318834 m, 84739 m/sec, 18941262 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 HirschbergSinclair-PT-15-CTLFireability-07 4608698 m, 57972 m/sec, 20607478 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 HirschbergSinclair-PT-15-CTLFireability-07 5047997 m, 87859 m/sec, 22391595 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 HirschbergSinclair-PT-15-CTLFireability-07 5356955 m, 61791 m/sec, 24033486 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 HirschbergSinclair-PT-15-CTLFireability-07 5669684 m, 62545 m/sec, 25694024 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 HirschbergSinclair-PT-15-CTLFireability-07 6058087 m, 77680 m/sec, 27508267 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 HirschbergSinclair-PT-15-CTLFireability-07 6386196 m, 65621 m/sec, 29255801 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 HirschbergSinclair-PT-15-CTLFireability-07 6681608 m, 59082 m/sec, 30957492 t fired, . in use: 32 for HirschbergSinclair-PT-15-CTLFireability-07 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker AG false state space false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 for 15 HirschbergSinclair-PT-15-CTLFireability-06 for HirschbergSinclair-PT-15-CTLFireability-06 96 287 0.000000 1 for 6 HirschbergSinclair-PT-15-CTLFireability-02 for HirschbergSinclair-PT-15-CTLFireability-02 255 254 0.000000 1 for 47 HirschbergSinclair-PT-15-CTLFireability-15 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 HirschbergSinclair-PT-15-CTLFireability-15 565624 m, 113124 m/sec, 2541492 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 HirschbergSinclair-PT-15-CTLFireability-15 1305224 m, 147920 m/sec, 5770642 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 HirschbergSinclair-PT-15-CTLFireability-15 1935637 m, 126082 m/sec, 9115796 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 HirschbergSinclair-PT-15-CTLFireability-15 2494381 m, 111748 m/sec, 12374687 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 HirschbergSinclair-PT-15-CTLFireability-15 2935716 m, 88267 m/sec, 14600126 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 HirschbergSinclair-PT-15-CTLFireability-15 3234814 m, 59819 m/sec, 16588172 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 HirschbergSinclair-PT-15-CTLFireability-15 3566237 m, 66284 m/sec, 18616507 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 HirschbergSinclair-PT-15-CTLFireability-15 3933684 m, 73489 m/sec, 20728958 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 HirschbergSinclair-PT-15-CTLFireability-15 4195494 m, 52362 m/sec, 22655917 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 HirschbergSinclair-PT-15-CTLFireability-15 4872872 m, 135475 m/sec, 25637528 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 HirschbergSinclair-PT-15-CTLFireability-15 5520041 m, 129433 m/sec, 28911840 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 HirschbergSinclair-PT-15-CTLFireability-15 6134790 m, 122949 m/sec, 32205427 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 HirschbergSinclair-PT-15-CTLFireability-15 6815216 m, 136085 m/sec, 35469412 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 HirschbergSinclair-PT-15-CTLFireability-15 7400230 m, 117002 m/sec, 38739062 t fired, . in use: 32 for HirschbergSinclair-PT-15-CTLFireability-15 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 for 41 HirschbergSinclair-PT-15-CTLFireability-13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 HirschbergSinclair-PT-15-CTLFireability-13 682556 m, 136511 m/sec, 2274536 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 HirschbergSinclair-PT-15-CTLFireability-13 1316130 m, 126714 m/sec, 4611650 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 HirschbergSinclair-PT-15-CTLFireability-13 1928185 m, 122411 m/sec, 6931550 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 HirschbergSinclair-PT-15-CTLFireability-13 2519340 m, 118231 m/sec, 9222130 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 HirschbergSinclair-PT-15-CTLFireability-13 3069876 m, 110107 m/sec, 11510788 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 HirschbergSinclair-PT-15-CTLFireability-13 3683636 m, 122752 m/sec, 13772442 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 HirschbergSinclair-PT-15-CTLFireability-13 4302710 m, 123814 m/sec, 15982965 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 HirschbergSinclair-PT-15-CTLFireability-13 4892519 m, 117961 m/sec, 18223187 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 HirschbergSinclair-PT-15-CTLFireability-13 5455921 m, 112680 m/sec, 20445867 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 HirschbergSinclair-PT-15-CTLFireability-13 6052921 m, 119400 m/sec, 22768340 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 HirschbergSinclair-PT-15-CTLFireability-13 6650689 m, 119553 m/sec, 25047365 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 HirschbergSinclair-PT-15-CTLFireability-13 7235681 m, 116998 m/sec, 27263917 t fired, . in use: 32 for HirschbergSinclair-PT-15-CTLFireability-13 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AG false state space CTL false CTL model checker false CTL model checker CTL true CTL model checker CONJ false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 0 0 0 2 0 2 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 truncated ======

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-15"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HirschbergSinclair-PT-15, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840346000442"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-15.tgz
mv HirschbergSinclair-PT-15 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;