Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r199-smll-167840345900426.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HirschbergSinclair-PT-05, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840345900426
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 628K
-rw-r--r-- 1 mcc users 12K Feb 26 02:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K Feb 26 02:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 02:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 02:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 16:14 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:14 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:14 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 02:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 26 02:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Feb 26 02:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Feb 26 02:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:14 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 157K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-00
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-01
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-02
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-03
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-04
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-05
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-06
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-07
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-08
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-09
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-10
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-11
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-12
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-13
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-14
FORMULA_NAME HirschbergSinclair-PT-05-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678538319161

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-05
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 12:38:42] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 12:38:42] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 12:38:42] [INFO ] Load time of PNML (sax parser for PT used): 113 ms
[2023-03-11 12:38:42] [INFO ] Transformed 124 places.
[2023-03-11 12:38:43] [INFO ] Transformed 111 transitions.
[2023-03-11 12:38:43] [INFO ] Parsed PT model containing 124 places and 111 transitions and 340 arcs in 266 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 21 ms.
Support contains 84 out of 124 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 111/111 transitions.
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 119 transition count 111
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 6 place count 118 transition count 110
Iterating global reduction 1 with 1 rules applied. Total rules applied 7 place count 118 transition count 110
Applied a total of 7 rules in 41 ms. Remains 118 /124 variables (removed 6) and now considering 110/111 (removed 1) transitions.
// Phase 1: matrix 110 rows 118 cols
[2023-03-11 12:38:43] [INFO ] Computed 8 place invariants in 21 ms
[2023-03-11 12:38:43] [INFO ] Implicit Places using invariants in 376 ms returned []
[2023-03-11 12:38:43] [INFO ] Invariant cache hit.
[2023-03-11 12:38:43] [INFO ] Implicit Places using invariants and state equation in 261 ms returned []
Implicit Place search using SMT with State Equation took 701 ms to find 0 implicit places.
[2023-03-11 12:38:43] [INFO ] Invariant cache hit.
[2023-03-11 12:38:44] [INFO ] Dead Transitions using invariants and state equation in 183 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 118/124 places, 110/111 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 928 ms. Remains : 118/124 places, 110/111 transitions.
Support contains 84 out of 118 places after structural reductions.
[2023-03-11 12:38:44] [INFO ] Flatten gal took : 63 ms
[2023-03-11 12:38:44] [INFO ] Flatten gal took : 25 ms
[2023-03-11 12:38:44] [INFO ] Input system was already deterministic with 110 transitions.
Incomplete random walk after 10000 steps, including 90 resets, run finished after 844 ms. (steps per millisecond=11 ) properties (out of 70) seen :65
Incomplete Best-First random walk after 10001 steps, including 26 resets, run finished after 139 ms. (steps per millisecond=71 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 20 resets, run finished after 87 ms. (steps per millisecond=114 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10000 steps, including 26 resets, run finished after 102 ms. (steps per millisecond=98 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 27 resets, run finished after 108 ms. (steps per millisecond=92 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 27 resets, run finished after 87 ms. (steps per millisecond=114 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-11 12:38:45] [INFO ] Invariant cache hit.
[2023-03-11 12:38:46] [INFO ] [Real]Absence check using 0 positive and 8 generalized place invariants in 9 ms returned sat
[2023-03-11 12:38:46] [INFO ] After 78ms SMT Verify possible using state equation in real domain returned unsat :3 sat :1
[2023-03-11 12:38:46] [INFO ] After 101ms SMT Verify possible using trap constraints in real domain returned unsat :3 sat :1
Attempting to minimize the solution found.
Minimization took 20 ms.
[2023-03-11 12:38:46] [INFO ] After 241ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :1
Fused 4 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 2 ms.
Support contains 2 out of 118 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 118/118 places, 110/110 transitions.
Graph (complete) has 221 edges and 118 vertex of which 113 are kept as prefixes of interest. Removing 5 places using SCC suffix rule.1 ms
Discarding 5 places :
Also discarding 0 output transitions
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 45 transitions
Trivial Post-agglo rules discarded 45 transitions
Performed 45 trivial Post agglomeration. Transition count delta: 45
Iterating post reduction 0 with 50 rules applied. Total rules applied 51 place count 113 transition count 60
Reduce places removed 45 places and 0 transitions.
Graph (complete) has 114 edges and 68 vertex of which 52 are kept as prefixes of interest. Removing 16 places using SCC suffix rule.0 ms
Discarding 16 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 46 rules applied. Total rules applied 97 place count 52 transition count 60
Drop transitions removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 2 with 16 rules applied. Total rules applied 113 place count 52 transition count 44
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 113 place count 52 transition count 43
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 115 place count 51 transition count 43
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 116 place count 50 transition count 42
Iterating global reduction 3 with 1 rules applied. Total rules applied 117 place count 50 transition count 42
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 3 with 1 rules applied. Total rules applied 118 place count 50 transition count 41
Reduce places removed 1 places and 0 transitions.
Graph (complete) has 83 edges and 49 vertex of which 48 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.0 ms
Discarding 1 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 2 rules applied. Total rules applied 120 place count 48 transition count 41
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 121 place count 48 transition count 40
Reduce places removed 5 places and 5 transitions.
Iterating global reduction 6 with 5 rules applied. Total rules applied 126 place count 43 transition count 35
Reduce places removed 3 places and 0 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 6 with 7 rules applied. Total rules applied 133 place count 40 transition count 31
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 7 with 4 rules applied. Total rules applied 137 place count 36 transition count 31
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 8 with 13 Pre rules applied. Total rules applied 137 place count 36 transition count 18
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 8 with 26 rules applied. Total rules applied 163 place count 23 transition count 18
Applied a total of 163 rules in 37 ms. Remains 23 /118 variables (removed 95) and now considering 18/110 (removed 92) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 37 ms. Remains : 23/118 places, 18/110 transitions.
Incomplete random walk after 10000 steps, including 526 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 267 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Finished probabilistic random walk after 147 steps, run visited all 1 properties in 12 ms. (steps per millisecond=12 )
Probabilistic random walk after 147 steps, saw 70 distinct states, run finished after 13 ms. (steps per millisecond=11 ) properties seen :1
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 11 ms
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 13 ms
[2023-03-11 12:38:46] [INFO ] Input system was already deterministic with 110 transitions.
Support contains 78 out of 118 places (down from 81) after GAL structural reductions.
Computed a total of 118 stabilizing places and 110 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 118 transition count 110
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 114 transition count 106
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 114 transition count 106
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 11 place count 111 transition count 103
Iterating global reduction 0 with 3 rules applied. Total rules applied 14 place count 111 transition count 103
Applied a total of 14 rules in 25 ms. Remains 111 /118 variables (removed 7) and now considering 103/110 (removed 7) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 25 ms. Remains : 111/118 places, 103/110 transitions.
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 10 ms
[2023-03-11 12:38:46] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 113 transition count 105
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 113 transition count 105
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 14 place count 109 transition count 101
Iterating global reduction 0 with 4 rules applied. Total rules applied 18 place count 109 transition count 101
Applied a total of 18 rules in 29 ms. Remains 109 /118 variables (removed 9) and now considering 101/110 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 109/118 places, 101/110 transitions.
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 13 ms
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 13 ms
[2023-03-11 12:38:46] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 115 transition count 107
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 115 transition count 107
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 9 place count 112 transition count 104
Iterating global reduction 0 with 3 rules applied. Total rules applied 12 place count 112 transition count 104
Applied a total of 12 rules in 14 ms. Remains 112 /118 variables (removed 6) and now considering 104/110 (removed 6) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 112/118 places, 104/110 transitions.
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 13 ms
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 13 ms
[2023-03-11 12:38:46] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Reduce places removed 3 places and 3 transitions.
Drop transitions removed 26 transitions
Trivial Post-agglo rules discarded 26 transitions
Performed 26 trivial Post agglomeration. Transition count delta: 26
Iterating post reduction 0 with 26 rules applied. Total rules applied 26 place count 115 transition count 81
Reduce places removed 26 places and 0 transitions.
Iterating post reduction 1 with 26 rules applied. Total rules applied 52 place count 89 transition count 81
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 57 place count 84 transition count 76
Iterating global reduction 2 with 5 rules applied. Total rules applied 62 place count 84 transition count 76
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 63 place count 83 transition count 75
Iterating global reduction 2 with 1 rules applied. Total rules applied 64 place count 83 transition count 75
Applied a total of 64 rules in 26 ms. Remains 83 /118 variables (removed 35) and now considering 75/110 (removed 35) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 83/118 places, 75/110 transitions.
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:38:46] [INFO ] Input system was already deterministic with 75 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Reduce places removed 3 places and 3 transitions.
Drop transitions removed 26 transitions
Trivial Post-agglo rules discarded 26 transitions
Performed 26 trivial Post agglomeration. Transition count delta: 26
Iterating post reduction 0 with 26 rules applied. Total rules applied 26 place count 115 transition count 81
Reduce places removed 26 places and 0 transitions.
Iterating post reduction 1 with 26 rules applied. Total rules applied 52 place count 89 transition count 81
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 56 place count 85 transition count 77
Iterating global reduction 2 with 4 rules applied. Total rules applied 60 place count 85 transition count 77
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 1 rules applied. Total rules applied 61 place count 85 transition count 76
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 62 place count 84 transition count 76
Applied a total of 62 rules in 22 ms. Remains 84 /118 variables (removed 34) and now considering 76/110 (removed 34) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 84/118 places, 76/110 transitions.
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:38:46] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 15 transitions
Trivial Post-agglo rules discarded 15 transitions
Performed 15 trivial Post agglomeration. Transition count delta: 15
Iterating post reduction 0 with 15 rules applied. Total rules applied 15 place count 117 transition count 94
Reduce places removed 15 places and 0 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 30 place count 102 transition count 94
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 34 place count 98 transition count 90
Iterating global reduction 2 with 4 rules applied. Total rules applied 38 place count 98 transition count 90
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 39 place count 97 transition count 89
Iterating global reduction 2 with 1 rules applied. Total rules applied 40 place count 97 transition count 89
Applied a total of 40 rules in 25 ms. Remains 97 /118 variables (removed 21) and now considering 89/110 (removed 21) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 97/118 places, 89/110 transitions.
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 10 ms
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 10 ms
[2023-03-11 12:38:46] [INFO ] Input system was already deterministic with 89 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Reduce places removed 4 places and 4 transitions.
Drop transitions removed 38 transitions
Trivial Post-agglo rules discarded 38 transitions
Performed 38 trivial Post agglomeration. Transition count delta: 38
Iterating post reduction 0 with 38 rules applied. Total rules applied 38 place count 114 transition count 68
Reduce places removed 38 places and 0 transitions.
Iterating post reduction 1 with 38 rules applied. Total rules applied 76 place count 76 transition count 68
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 81 place count 71 transition count 63
Iterating global reduction 2 with 5 rules applied. Total rules applied 86 place count 71 transition count 63
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 87 place count 70 transition count 62
Iterating global reduction 2 with 1 rules applied. Total rules applied 88 place count 70 transition count 62
Applied a total of 88 rules in 19 ms. Remains 70 /118 variables (removed 48) and now considering 62/110 (removed 48) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 70/118 places, 62/110 transitions.
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 6 ms
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 7 ms
[2023-03-11 12:38:46] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 114 transition count 106
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 114 transition count 106
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 11 place count 111 transition count 103
Iterating global reduction 0 with 3 rules applied. Total rules applied 14 place count 111 transition count 103
Applied a total of 14 rules in 12 ms. Remains 111 /118 variables (removed 7) and now considering 103/110 (removed 7) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 111/118 places, 103/110 transitions.
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 11 ms
[2023-03-11 12:38:46] [INFO ] Flatten gal took : 11 ms
[2023-03-11 12:38:46] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 113 transition count 105
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 113 transition count 105
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 13 place count 110 transition count 102
Iterating global reduction 0 with 3 rules applied. Total rules applied 16 place count 110 transition count 102
Applied a total of 16 rules in 11 ms. Remains 110 /118 variables (removed 8) and now considering 102/110 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 110/118 places, 102/110 transitions.
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 10 ms
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:38:47] [INFO ] Input system was already deterministic with 102 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 117 transition count 101
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 1 with 8 rules applied. Total rules applied 16 place count 109 transition count 101
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 20 place count 105 transition count 97
Iterating global reduction 2 with 4 rules applied. Total rules applied 24 place count 105 transition count 97
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 1 rules applied. Total rules applied 25 place count 105 transition count 96
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 26 place count 104 transition count 96
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 27 place count 103 transition count 95
Iterating global reduction 4 with 1 rules applied. Total rules applied 28 place count 103 transition count 95
Applied a total of 28 rules in 23 ms. Remains 103 /118 variables (removed 15) and now considering 95/110 (removed 15) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 103/118 places, 95/110 transitions.
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 7 ms
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:38:47] [INFO ] Input system was already deterministic with 95 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Reduce places removed 3 places and 3 transitions.
Drop transitions removed 26 transitions
Trivial Post-agglo rules discarded 26 transitions
Performed 26 trivial Post agglomeration. Transition count delta: 26
Iterating post reduction 0 with 26 rules applied. Total rules applied 26 place count 115 transition count 81
Reduce places removed 26 places and 0 transitions.
Iterating post reduction 1 with 26 rules applied. Total rules applied 52 place count 89 transition count 81
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 57 place count 84 transition count 76
Iterating global reduction 2 with 5 rules applied. Total rules applied 62 place count 84 transition count 76
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 1 rules applied. Total rules applied 63 place count 84 transition count 75
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 64 place count 83 transition count 75
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 65 place count 82 transition count 74
Iterating global reduction 4 with 1 rules applied. Total rules applied 66 place count 82 transition count 74
Applied a total of 66 rules in 17 ms. Remains 82 /118 variables (removed 36) and now considering 74/110 (removed 36) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 82/118 places, 74/110 transitions.
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 6 ms
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 5 ms
[2023-03-11 12:38:47] [INFO ] Input system was already deterministic with 74 transitions.
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 113 transition count 105
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 113 transition count 105
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 14 place count 109 transition count 101
Iterating global reduction 0 with 4 rules applied. Total rules applied 18 place count 109 transition count 101
Applied a total of 18 rules in 8 ms. Remains 109 /118 variables (removed 9) and now considering 101/110 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 109/118 places, 101/110 transitions.
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 6 ms
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:38:47] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 113 transition count 105
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 113 transition count 105
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 14 place count 109 transition count 101
Iterating global reduction 0 with 4 rules applied. Total rules applied 18 place count 109 transition count 101
Applied a total of 18 rules in 9 ms. Remains 109 /118 variables (removed 9) and now considering 101/110 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 109/118 places, 101/110 transitions.
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 6 ms
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:38:47] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 115 transition count 107
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 115 transition count 107
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 7 place count 114 transition count 106
Iterating global reduction 0 with 1 rules applied. Total rules applied 8 place count 114 transition count 106
Applied a total of 8 rules in 7 ms. Remains 114 /118 variables (removed 4) and now considering 106/110 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 114/118 places, 106/110 transitions.
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 7 ms
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 7 ms
[2023-03-11 12:38:47] [INFO ] Input system was already deterministic with 106 transitions.
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 114 transition count 106
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 114 transition count 106
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 11 place count 111 transition count 103
Iterating global reduction 0 with 3 rules applied. Total rules applied 14 place count 111 transition count 103
Applied a total of 14 rules in 7 ms. Remains 111 /118 variables (removed 7) and now considering 103/110 (removed 7) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 111/118 places, 103/110 transitions.
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 6 ms
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 7 ms
[2023-03-11 12:38:47] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 118/118 places, 110/110 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 115 transition count 107
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 115 transition count 107
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 8 place count 113 transition count 105
Iterating global reduction 0 with 2 rules applied. Total rules applied 10 place count 113 transition count 105
Applied a total of 10 rules in 7 ms. Remains 113 /118 variables (removed 5) and now considering 105/110 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 113/118 places, 105/110 transitions.
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 6 ms
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 6 ms
[2023-03-11 12:38:47] [INFO ] Input system was already deterministic with 105 transitions.
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 7 ms
[2023-03-11 12:38:47] [INFO ] Flatten gal took : 7 ms
[2023-03-11 12:38:47] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-11 12:38:47] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 118 places, 110 transitions and 330 arcs took 1 ms.
Total runtime 4746 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HirschbergSinclair-PT-05
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA HirschbergSinclair-PT-05-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678538545827

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 4 (type CNST) for 3 HirschbergSinclair-PT-05-CTLFireability-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 4 (type CNST) for HirschbergSinclair-PT-05-CTLFireability-01
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 1 (type EXCL) for 0 HirschbergSinclair-PT-05-CTLFireability-00
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 53 (type FNDP) for 24 HirschbergSinclair-PT-05-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 24 HirschbergSinclair-PT-05-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type SRCH) for 24 HirschbergSinclair-PT-05-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 56 (type SRCH) for HirschbergSinclair-PT-05-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 53 (type FNDP) for HirschbergSinclair-PT-05-CTLFireability-08
lola: result : true
lola: fired transitions : 9
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 54 (type EQUN) for HirschbergSinclair-PT-05-CTLFireability-08 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 54 (type EQUN) for HirschbergSinclair-PT-05-CTLFireability-08
lola: result : unknown
lola: FINISHED task # 1 (type EXCL) for HirschbergSinclair-PT-05-CTLFireability-00
lola: result : false
lola: markings : 257826
lola: fired transitions : 1037175
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 50 (type EXCL) for 49 HirschbergSinclair-PT-05-CTLFireability-15
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for HirschbergSinclair-PT-05-CTLFireability-15
lola: result : false
lola: markings : 127
lola: fired transitions : 223
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 HirschbergSinclair-PT-05-CTLFireability-14
lola: time limit : 299 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLFireability-00: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-01: INITIAL false preprocessing
HirschbergSinclair-PT-05-CTLFireability-08: CONJ false findpath
HirschbergSinclair-PT-05-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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47 CTL EXCL 3/299 2/32 HirschbergSinclair-PT-05-CTLFireability-14 312227 m, 62445 m/sec, 2020721 t fired, .

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47 CTL EXCL 8/299 4/32 HirschbergSinclair-PT-05-CTLFireability-14 648287 m, 67212 m/sec, 4941796 t fired, .

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47 CTL EXCL 13/299 5/32 HirschbergSinclair-PT-05-CTLFireability-14 1013618 m, 73066 m/sec, 7811230 t fired, .

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47 CTL EXCL 18/299 7/32 HirschbergSinclair-PT-05-CTLFireability-14 1307662 m, 58808 m/sec, 10712020 t fired, .

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47 CTL EXCL 23/299 9/32 HirschbergSinclair-PT-05-CTLFireability-14 1724605 m, 83388 m/sec, 13750115 t fired, .

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47 CTL EXCL 28/299 10/32 HirschbergSinclair-PT-05-CTLFireability-14 2023463 m, 59771 m/sec, 16668312 t fired, .

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47 CTL EXCL 33/299 12/32 HirschbergSinclair-PT-05-CTLFireability-14 2352163 m, 65740 m/sec, 19677080 t fired, .

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47 CTL EXCL 38/299 13/32 HirschbergSinclair-PT-05-CTLFireability-14 2718857 m, 73338 m/sec, 22556717 t fired, .

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47 CTL EXCL 43/299 15/32 HirschbergSinclair-PT-05-CTLFireability-14 2991895 m, 54607 m/sec, 25392629 t fired, .

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47 CTL EXCL 73/299 23/32 HirschbergSinclair-PT-05-CTLFireability-14 4853449 m, 51750 m/sec, 43264066 t fired, .

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47 CTL EXCL 78/299 25/32 HirschbergSinclair-PT-05-CTLFireability-14 5194377 m, 68185 m/sec, 46314848 t fired, .

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41 CTL EXCL 0/351 1/32 HirschbergSinclair-PT-05-CTLFireability-12 43741 m, 8748 m/sec, 303894 t fired, .

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41 CTL EXCL 5/351 2/32 HirschbergSinclair-PT-05-CTLFireability-12 422261 m, 75704 m/sec, 3591298 t fired, .

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41 CTL EXCL 15/351 6/32 HirschbergSinclair-PT-05-CTLFireability-12 1091535 m, 63699 m/sec, 10011931 t fired, .

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41 CTL EXCL 25/351 9/32 HirschbergSinclair-PT-05-CTLFireability-12 1774640 m, 66825 m/sec, 16343126 t fired, .

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41 CTL EXCL 30/351 10/32 HirschbergSinclair-PT-05-CTLFireability-12 2077429 m, 60557 m/sec, 19449792 t fired, .

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41 CTL EXCL 55/351 18/32 HirschbergSinclair-PT-05-CTLFireability-12 3604745 m, 66977 m/sec, 35073053 t fired, .

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41 CTL EXCL 60/351 19/32 HirschbergSinclair-PT-05-CTLFireability-12 3906287 m, 60308 m/sec, 38216634 t fired, .

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41 CTL EXCL 65/351 20/32 HirschbergSinclair-PT-05-CTLFireability-12 4187468 m, 56236 m/sec, 41232007 t fired, .

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41 CTL EXCL 85/351 26/32 HirschbergSinclair-PT-05-CTLFireability-12 5274580 m, 51374 m/sec, 53348615 t fired, .

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38 CTL EXCL 6/380 6/32 HirschbergSinclair-PT-05-CTLFireability-11 1113197 m, 177641 m/sec, 4222946 t fired, .

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lola: markings : 50
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lola: time used : 0.000000
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HirschbergSinclair-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 1/850 1/32 HirschbergSinclair-PT-05-CTLFireability-03 153703 m, 30740 m/sec, 1259602 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLFireability-00: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-01: INITIAL false preprocessing
HirschbergSinclair-PT-05-CTLFireability-02: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-06: AGEF false tscc_search
HirschbergSinclair-PT-05-CTLFireability-07: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-08: CONJ false findpath
HirschbergSinclair-PT-05-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-12: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-13: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-14: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 6/850 3/32 HirschbergSinclair-PT-05-CTLFireability-03 628076 m, 94874 m/sec, 5480611 t fired, .

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HirschbergSinclair-PT-05-CTLFireability-00: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-01: INITIAL false preprocessing
HirschbergSinclair-PT-05-CTLFireability-02: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-06: AGEF false tscc_search
HirschbergSinclair-PT-05-CTLFireability-07: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-08: CONJ false findpath
HirschbergSinclair-PT-05-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-12: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-13: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-14: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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HirschbergSinclair-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 11/850 5/32 HirschbergSinclair-PT-05-CTLFireability-03 1035464 m, 81477 m/sec, 9596725 t fired, .

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lola: FINISHED task # 10 (type EXCL) for HirschbergSinclair-PT-05-CTLFireability-03
lola: result : false
lola: markings : 1065424
lola: fired transitions : 9851030
lola: time used : 12.000000
lola: memory pages used : 5
lola: LAUNCH task # 13 (type EXCL) for 12 HirschbergSinclair-PT-05-CTLFireability-04
lola: time limit : 1129 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLFireability-00: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-01: INITIAL false preprocessing
HirschbergSinclair-PT-05-CTLFireability-02: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-03: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-06: AGEF false tscc_search
HirschbergSinclair-PT-05-CTLFireability-07: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-08: CONJ false findpath
HirschbergSinclair-PT-05-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-12: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-13: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-14: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 4/1129 3/32 HirschbergSinclair-PT-05-CTLFireability-04 508006 m, 101601 m/sec, 3939326 t fired, .

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# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 13 (type EXCL) for HirschbergSinclair-PT-05-CTLFireability-04
lola: result : false
lola: markings : 684146
lola: fired transitions : 5457904
lola: time used : 6.000000
lola: memory pages used : 4
lola: LAUNCH task # 32 (type EXCL) for 31 HirschbergSinclair-PT-05-CTLFireability-09
lola: time limit : 1691 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for HirschbergSinclair-PT-05-CTLFireability-09
lola: result : true
lola: markings : 128
lola: fired transitions : 248
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 HirschbergSinclair-PT-05-CTLFireability-05
lola: time limit : 3383 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for HirschbergSinclair-PT-05-CTLFireability-05
lola: result : false
lola: markings : 705
lola: fired transitions : 1154
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLFireability-00: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-01: INITIAL false preprocessing
HirschbergSinclair-PT-05-CTLFireability-02: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-03: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-04: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-06: AGEF false tscc_search
HirschbergSinclair-PT-05-CTLFireability-07: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-08: CONJ false findpath
HirschbergSinclair-PT-05-CTLFireability-09: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-10: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-12: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-13: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLFireability-14: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-05"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HirschbergSinclair-PT-05, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840345900426"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-05.tgz
mv HirschbergSinclair-PT-05 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;