fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r167-tall-167838853700826
Last Updated
May 14, 2023

About the Execution of LoLa+red for GPPP-PT-C0010N0000000100

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1286.831 159542.00 152864.00 785.30 TTTT???FFTTFFTTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838853700826.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is GPPP-PT-C0010N0000000100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838853700826
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 536K
-rw-r--r-- 1 mcc users 6.6K Feb 26 10:44 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 26 10:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 26 10:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K Feb 26 10:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:10 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:10 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 25 16:10 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:10 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 26 10:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 158K Feb 26 10:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 26 10:45 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Feb 26 10:45 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 17 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1 Mar 5 18:22 large_marking
-rw-r--r-- 1 mcc users 21K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-00
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-01
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-02
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-03
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-04
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-05
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-06
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-07
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-08
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-09
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-10
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-11
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-12
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-13
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-14
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678529987868

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=GPPP-PT-C0010N0000000100
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 10:19:49] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 10:19:49] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 10:19:49] [INFO ] Load time of PNML (sax parser for PT used): 25 ms
[2023-03-11 10:19:49] [INFO ] Transformed 33 places.
[2023-03-11 10:19:49] [INFO ] Transformed 22 transitions.
[2023-03-11 10:19:49] [INFO ] Parsed PT model containing 33 places and 22 transitions and 83 arcs in 81 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 3 formulas.
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 33 out of 33 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 9 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 10:19:49] [INFO ] Computed 12 place invariants in 10 ms
[2023-03-11 10:19:49] [INFO ] Dead Transitions using invariants and state equation in 155 ms found 0 transitions.
[2023-03-11 10:19:49] [INFO ] Invariant cache hit.
[2023-03-11 10:19:49] [INFO ] Implicit Places using invariants in 34 ms returned []
[2023-03-11 10:19:49] [INFO ] Invariant cache hit.
[2023-03-11 10:19:49] [INFO ] Implicit Places using invariants and state equation in 34 ms returned []
Implicit Place search using SMT with State Equation took 70 ms to find 0 implicit places.
[2023-03-11 10:19:49] [INFO ] Invariant cache hit.
[2023-03-11 10:19:49] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 288 ms. Remains : 33/33 places, 22/22 transitions.
Support contains 33 out of 33 places after structural reductions.
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 16 ms
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 6 ms
[2023-03-11 10:19:50] [INFO ] Input system was already deterministic with 22 transitions.
Support contains 32 out of 33 places (down from 33) after GAL structural reductions.
Incomplete random walk after 10006 steps, including 24 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 30) seen :29
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-11 10:19:50] [INFO ] Invariant cache hit.
[2023-03-11 10:19:50] [INFO ] [Real]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-11 10:19:50] [INFO ] [Real]Absence check using 6 positive and 6 generalized place invariants in 3 ms returned sat
[2023-03-11 10:19:50] [INFO ] After 40ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-11 10:19:50] [INFO ] [Nat]Absence check using 6 positive place invariants in 3 ms returned sat
[2023-03-11 10:19:50] [INFO ] [Nat]Absence check using 6 positive and 6 generalized place invariants in 149 ms returned sat
[2023-03-11 10:19:50] [INFO ] After 353ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 13 simplifications.
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 5 ms
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 3 ms
[2023-03-11 10:19:50] [INFO ] Input system was already deterministic with 22 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 3 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 2 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 32 transition count 20
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 31 transition count 20
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 5 rules applied. Total rules applied 8 place count 28 transition count 18
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 11 place count 26 transition count 17
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 13 place count 25 transition count 16
Applied a total of 13 rules in 12 ms. Remains 25 /33 variables (removed 8) and now considering 16/22 (removed 6) transitions.
// Phase 1: matrix 16 rows 25 cols
[2023-03-11 10:19:50] [INFO ] Computed 10 place invariants in 1 ms
[2023-03-11 10:19:50] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 40 ms. Remains : 25/33 places, 16/22 transitions.
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:50] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 10:19:50] [INFO ] Computed 12 place invariants in 2 ms
[2023-03-11 10:19:50] [INFO ] Dead Transitions using invariants and state equation in 39 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 41 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 3 ms
[2023-03-11 10:19:50] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
[2023-03-11 10:19:50] [INFO ] Invariant cache hit.
[2023-03-11 10:19:50] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:50] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 33 transition count 21
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 32 transition count 21
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 32 transition count 20
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 31 transition count 20
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 7 place count 29 transition count 19
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 10 place count 27 transition count 18
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 12 place count 26 transition count 17
Applied a total of 12 rules in 5 ms. Remains 26 /33 variables (removed 7) and now considering 17/22 (removed 5) transitions.
// Phase 1: matrix 17 rows 26 cols
[2023-03-11 10:19:50] [INFO ] Computed 10 place invariants in 1 ms
[2023-03-11 10:19:50] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 37 ms. Remains : 26/33 places, 17/22 transitions.
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:50] [INFO ] Input system was already deterministic with 17 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 10:19:50] [INFO ] Computed 12 place invariants in 1 ms
[2023-03-11 10:19:50] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:50] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 33 transition count 21
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 32 transition count 21
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 32 transition count 20
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 31 transition count 20
Applied a total of 4 rules in 3 ms. Remains 31 /33 variables (removed 2) and now considering 20/22 (removed 2) transitions.
// Phase 1: matrix 20 rows 31 cols
[2023-03-11 10:19:50] [INFO ] Computed 12 place invariants in 1 ms
[2023-03-11 10:19:50] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 33 ms. Remains : 31/33 places, 20/22 transitions.
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 6 ms
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:50] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 33 transition count 21
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 32 transition count 21
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 5 place count 30 transition count 20
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 8 place count 28 transition count 19
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 10 place count 27 transition count 18
Applied a total of 10 rules in 5 ms. Remains 27 /33 variables (removed 6) and now considering 18/22 (removed 4) transitions.
// Phase 1: matrix 18 rows 27 cols
[2023-03-11 10:19:50] [INFO ] Computed 10 place invariants in 0 ms
[2023-03-11 10:19:50] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 38 ms. Remains : 27/33 places, 18/22 transitions.
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:50] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:50] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 10:19:50] [INFO ] Computed 12 place invariants in 2 ms
[2023-03-11 10:19:51] [INFO ] Dead Transitions using invariants and state equation in 45 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 47 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:51] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 2 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 1 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 5 rules applied. Total rules applied 6 place count 29 transition count 19
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 9 place count 27 transition count 18
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 11 place count 26 transition count 17
Applied a total of 11 rules in 5 ms. Remains 26 /33 variables (removed 7) and now considering 17/22 (removed 5) transitions.
// Phase 1: matrix 17 rows 26 cols
[2023-03-11 10:19:51] [INFO ] Computed 10 place invariants in 3 ms
[2023-03-11 10:19:51] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 37 ms. Remains : 26/33 places, 17/22 transitions.
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:51] [INFO ] Input system was already deterministic with 17 transitions.
Finished random walk after 150 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=75 )
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 4 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 32 transition count 20
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 31 transition count 20
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 3 place count 31 transition count 19
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 5 place count 30 transition count 19
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 5 rules applied. Total rules applied 10 place count 27 transition count 17
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 12 place count 26 transition count 16
Applied a total of 12 rules in 3 ms. Remains 26 /33 variables (removed 7) and now considering 16/22 (removed 6) transitions.
// Phase 1: matrix 16 rows 26 cols
[2023-03-11 10:19:51] [INFO ] Computed 11 place invariants in 0 ms
[2023-03-11 10:19:51] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 26/33 places, 16/22 transitions.
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:51] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 10:19:51] [INFO ] Computed 12 place invariants in 1 ms
[2023-03-11 10:19:51] [INFO ] Dead Transitions using invariants and state equation in 44 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 45 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 3 ms
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 3 ms
[2023-03-11 10:19:51] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
[2023-03-11 10:19:51] [INFO ] Invariant cache hit.
[2023-03-11 10:19:51] [INFO ] Dead Transitions using invariants and state equation in 37 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 39 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:51] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
[2023-03-11 10:19:51] [INFO ] Invariant cache hit.
[2023-03-11 10:19:51] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:51] [INFO ] Input system was already deterministic with 22 transitions.
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 2 ms
[2023-03-11 10:19:51] [INFO ] Flatten gal took : 1 ms
[2023-03-11 10:19:51] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-11 10:19:51] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 33 places, 22 transitions and 83 arcs took 0 ms.
Total runtime 1990 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT GPPP-PT-C0010N0000000100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA GPPP-PT-C0010N0000000100-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0010N0000000100-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0010N0000000100-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0010N0000000100-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0010N0000000100-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0010N0000000100-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0010N0000000100-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0010N0000000100-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0010N0000000100-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678530147410

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: LAUNCH task # 13 (type EXCL) for 12 GPPP-PT-C0010N0000000100-CTLFireability-04
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-10: EG 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/276 5/32 GPPP-PT-C0010N0000000100-CTLFireability-04 1128040 m, 225608 m/sec, 8163000 t fired, .

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GPPP-PT-C0010N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-10: EG 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/276 9/32 GPPP-PT-C0010N0000000100-CTLFireability-04 2179373 m, 210266 m/sec, 16267019 t fired, .

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GPPP-PT-C0010N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-10: EG 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/276 13/32 GPPP-PT-C0010N0000000100-CTLFireability-04 3124442 m, 189013 m/sec, 24208087 t fired, .

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GPPP-PT-C0010N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-10: EG 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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19 CTL EXCL 4/1777 4/32 GPPP-PT-C0010N0000000100-CTLFireability-06 952476 m, 190495 m/sec, 7279099 t fired, .

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GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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19 CTL EXCL 9/1777 9/32 GPPP-PT-C0010N0000000100-CTLFireability-06 1992234 m, 207951 m/sec, 16172942 t fired, .

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GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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19 CTL EXCL 24/1777 21/32 GPPP-PT-C0010N0000000100-CTLFireability-06 5122854 m, 210775 m/sec, 42690611 t fired, .

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GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/3515 3/32 GPPP-PT-C0010N0000000100-CTLFireability-05 673397 m, 134679 m/sec, 8493622 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

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16 CTL EXCL 10/3515 6/32 GPPP-PT-C0010N0000000100-CTLFireability-05 1370665 m, 139453 m/sec, 17188959 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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16 CTL EXCL 15/3515 9/32 GPPP-PT-C0010N0000000100-CTLFireability-05 2037998 m, 133466 m/sec, 25677495 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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16 CTL EXCL 20/3515 11/32 GPPP-PT-C0010N0000000100-CTLFireability-05 2597047 m, 111809 m/sec, 34371110 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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16 CTL EXCL 25/3515 13/32 GPPP-PT-C0010N0000000100-CTLFireability-05 3121167 m, 104824 m/sec, 42677677 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 30/3515 16/32 GPPP-PT-C0010N0000000100-CTLFireability-05 3817125 m, 139191 m/sec, 51315652 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 35/3515 18/32 GPPP-PT-C0010N0000000100-CTLFireability-05 4304748 m, 97524 m/sec, 59743405 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
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GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 40/3515 21/32 GPPP-PT-C0010N0000000100-CTLFireability-05 4869990 m, 113048 m/sec, 68053273 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

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GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 45/3515 23/32 GPPP-PT-C0010N0000000100-CTLFireability-05 5564720 m, 138946 m/sec, 76528058 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 50/3515 25/32 GPPP-PT-C0010N0000000100-CTLFireability-05 5980323 m, 83120 m/sec, 84866906 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 55/3515 28/32 GPPP-PT-C0010N0000000100-CTLFireability-05 6618362 m, 127607 m/sec, 93111778 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

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16 CTL EXCL 60/3515 30/32 GPPP-PT-C0010N0000000100-CTLFireability-05 7080827 m, 92493 m/sec, 101352274 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 65/3515 32/32 GPPP-PT-C0010N0000000100-CTLFireability-05 7675412 m, 118917 m/sec, 109804323 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000100-CTLFireability-00: EFEG true state space /EFEG
GPPP-PT-C0010N0000000100-CTLFireability-01: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-02: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-04: CTL unknown AGGR
GPPP-PT-C0010N0000000100-CTLFireability-05: CTL unknown AGGR
GPPP-PT-C0010N0000000100-CTLFireability-06: CTL unknown AGGR
GPPP-PT-C0010N0000000100-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-10: EG true state space / EG
GPPP-PT-C0010N0000000100-CTLFireability-12: CTL false CTL model checker
GPPP-PT-C0010N0000000100-CTLFireability-13: DISJ true state space /EXEF
GPPP-PT-C0010N0000000100-CTLFireability-14: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GPPP-PT-C0010N0000000100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is GPPP-PT-C0010N0000000100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838853700826"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/GPPP-PT-C0010N0000000100.tgz
mv GPPP-PT-C0010N0000000100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;