About the Execution of LoLa+red for FlexibleBarrier-PT-12a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16222.220 | 532207.00 | 530612.00 | 4340.00 | ?T?????T?TTTFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r167-tall-167838853200506.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FlexibleBarrier-PT-12a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838853200506
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 624K
-rw-r--r-- 1 mcc users 7.2K Feb 25 13:14 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 25 13:14 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 12:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 25 12:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 13:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 138K Feb 25 13:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Feb 25 13:19 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 25 13:19 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 128K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-00
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-01
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-02
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-03
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-04
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-05
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-06
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-07
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-08
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-09
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-10
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-11
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-12
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-13
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-14
FORMULA_NAME FlexibleBarrier-PT-12a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678487356207
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FlexibleBarrier-PT-12a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 22:29:17] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 22:29:17] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 22:29:17] [INFO ] Load time of PNML (sax parser for PT used): 62 ms
[2023-03-10 22:29:17] [INFO ] Transformed 147 places.
[2023-03-10 22:29:17] [INFO ] Transformed 448 transitions.
[2023-03-10 22:29:17] [INFO ] Found NUPN structural information;
[2023-03-10 22:29:17] [INFO ] Parsed PT model containing 147 places and 448 transitions and 2045 arcs in 281 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Initial state reduction rules removed 1 formulas.
Ensure Unique test removed 122 transitions
Reduce redundant transitions removed 122 transitions.
FORMULA FlexibleBarrier-PT-12a-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 71 out of 147 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 326/326 transitions.
Drop transitions removed 12 transitions
Redundant transition composition rules discarded 12 transitions
Iterating global reduction 0 with 12 rules applied. Total rules applied 12 place count 147 transition count 314
Applied a total of 12 rules in 19 ms. Remains 147 /147 variables (removed 0) and now considering 314/326 (removed 12) transitions.
// Phase 1: matrix 314 rows 147 cols
[2023-03-10 22:29:18] [INFO ] Computed 14 place invariants in 20 ms
[2023-03-10 22:29:18] [INFO ] Implicit Places using invariants in 241 ms returned []
[2023-03-10 22:29:18] [INFO ] Invariant cache hit.
[2023-03-10 22:29:18] [INFO ] State equation strengthened by 193 read => feed constraints.
[2023-03-10 22:29:18] [INFO ] Implicit Places using invariants and state equation in 195 ms returned []
Implicit Place search using SMT with State Equation took 463 ms to find 0 implicit places.
[2023-03-10 22:29:18] [INFO ] Invariant cache hit.
[2023-03-10 22:29:18] [INFO ] Dead Transitions using invariants and state equation in 166 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 147/147 places, 314/326 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 651 ms. Remains : 147/147 places, 314/326 transitions.
Support contains 71 out of 147 places after structural reductions.
[2023-03-10 22:29:18] [INFO ] Flatten gal took : 42 ms
[2023-03-10 22:29:18] [INFO ] Flatten gal took : 20 ms
[2023-03-10 22:29:19] [INFO ] Input system was already deterministic with 314 transitions.
Support contains 70 out of 147 places (down from 71) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 356 ms. (steps per millisecond=28 ) properties (out of 94) seen :90
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=909 ) properties (out of 3) seen :1
Running SMT prover for 2 properties.
[2023-03-10 22:29:19] [INFO ] Invariant cache hit.
[2023-03-10 22:29:19] [INFO ] [Real]Absence check using 14 positive place invariants in 3 ms returned sat
[2023-03-10 22:29:19] [INFO ] After 151ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:1
[2023-03-10 22:29:19] [INFO ] [Nat]Absence check using 14 positive place invariants in 3 ms returned sat
[2023-03-10 22:29:19] [INFO ] After 72ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :1
[2023-03-10 22:29:19] [INFO ] State equation strengthened by 193 read => feed constraints.
[2023-03-10 22:29:19] [INFO ] After 38ms SMT Verify possible using 193 Read/Feed constraints in natural domain returned unsat :1 sat :1
[2023-03-10 22:29:19] [INFO ] After 89ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :1
Attempting to minimize the solution found.
Minimization took 125 ms.
[2023-03-10 22:29:19] [INFO ] After 352ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :1
Fused 2 Parikh solutions to 1 different solutions.
Finished Parikh walk after 24 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=12 )
Parikh walk visited 1 properties in 4 ms.
Successfully simplified 1 atomic propositions for a total of 15 simplifications.
[2023-03-10 22:29:20] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 29 ms
FORMULA FlexibleBarrier-PT-12a-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 18 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Computed a total of 3 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 6 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 12 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 14 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Graph (trivial) has 118 edges and 147 vertex of which 36 / 147 are part of one of the 12 SCC in 3 ms
Free SCC test removed 24 places
Ensure Unique test removed 79 transitions
Reduce isomorphic transitions removed 79 transitions.
Performed 12 Post agglomeration using F-continuation condition.Transition count delta: 12
Deduced a syphon composed of 12 places in 1 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 0 with 24 rules applied. Total rules applied 25 place count 111 transition count 223
Drop transitions removed 66 transitions
Redundant transition composition rules discarded 66 transitions
Iterating global reduction 0 with 66 rules applied. Total rules applied 91 place count 111 transition count 157
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 92 place count 111 transition count 157
Applied a total of 92 rules in 41 ms. Remains 111 /147 variables (removed 36) and now considering 157/314 (removed 157) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 42 ms. Remains : 111/147 places, 157/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 5 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 6 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 157 transitions.
Finished random walk after 126 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=63 )
FORMULA FlexibleBarrier-PT-12a-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Graph (trivial) has 93 edges and 147 vertex of which 15 / 147 are part of one of the 5 SCC in 0 ms
Free SCC test removed 10 places
Ensure Unique test removed 20 transitions
Reduce isomorphic transitions removed 20 transitions.
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 0 with 18 rules applied. Total rules applied 19 place count 128 transition count 285
Drop transitions removed 70 transitions
Redundant transition composition rules discarded 70 transitions
Iterating global reduction 0 with 70 rules applied. Total rules applied 89 place count 128 transition count 215
Partial Post-agglomeration rule applied 8 times.
Drop transitions removed 8 transitions
Iterating global reduction 0 with 8 rules applied. Total rules applied 97 place count 128 transition count 215
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 100 place count 125 transition count 212
Iterating global reduction 0 with 3 rules applied. Total rules applied 103 place count 125 transition count 212
Applied a total of 103 rules in 39 ms. Remains 125 /147 variables (removed 22) and now considering 212/314 (removed 102) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 39 ms. Remains : 125/147 places, 212/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 7 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 8 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 212 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 2 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 11 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 2 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 3 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 2 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 8 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 2 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 2 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 2 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 16 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 2 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 7 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 7 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Graph (trivial) has 80 edges and 147 vertex of which 3 / 147 are part of one of the 1 SCC in 1 ms
Free SCC test removed 2 places
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 7 place count 142 transition count 309
Drop transitions removed 11 transitions
Redundant transition composition rules discarded 11 transitions
Iterating global reduction 0 with 11 rules applied. Total rules applied 18 place count 142 transition count 298
Partial Post-agglomeration rule applied 9 times.
Drop transitions removed 9 transitions
Iterating global reduction 0 with 9 rules applied. Total rules applied 27 place count 142 transition count 298
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 36 place count 133 transition count 289
Iterating global reduction 0 with 9 rules applied. Total rules applied 45 place count 133 transition count 289
Applied a total of 45 rules in 35 ms. Remains 133 /147 variables (removed 14) and now considering 289/314 (removed 25) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 133/147 places, 289/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 6 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 7 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 289 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 2 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 6 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 7 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
Starting structural reductions in LTL mode, iteration 0 : 147/147 places, 314/314 transitions.
Applied a total of 0 rules in 2 ms. Remains 147 /147 variables (removed 0) and now considering 314/314 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 147/147 places, 314/314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 8 ms
[2023-03-10 22:29:20] [INFO ] Input system was already deterministic with 314 transitions.
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 8 ms
[2023-03-10 22:29:20] [INFO ] Flatten gal took : 8 ms
[2023-03-10 22:29:20] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-10 22:29:20] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 147 places, 314 transitions and 1269 arcs took 2 ms.
Total runtime 3263 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FlexibleBarrier-PT-12a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA FlexibleBarrier-PT-12a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-12a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-12a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-12a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-12a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-12a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678487888414
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 8 (type EXCL) for 7 FlexibleBarrier-PT-12a-CTLFireability-02
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 5/257 4/32 FlexibleBarrier-PT-12a-CTLFireability-02 725581 m, 145116 m/sec, 3882602 t fired, .
Time elapsed: 6 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 10/257 7/32 FlexibleBarrier-PT-12a-CTLFireability-02 1467744 m, 148432 m/sec, 7578635 t fired, .
Time elapsed: 11 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 15/257 10/32 FlexibleBarrier-PT-12a-CTLFireability-02 2156816 m, 137814 m/sec, 11204457 t fired, .
Time elapsed: 16 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 20/257 13/32 FlexibleBarrier-PT-12a-CTLFireability-02 2842385 m, 137113 m/sec, 14595241 t fired, .
Time elapsed: 21 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 25/257 16/32 FlexibleBarrier-PT-12a-CTLFireability-02 3445092 m, 120541 m/sec, 17498201 t fired, .
Time elapsed: 26 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 30/257 18/32 FlexibleBarrier-PT-12a-CTLFireability-02 4007144 m, 112410 m/sec, 20191723 t fired, .
Time elapsed: 31 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 35/257 21/32 FlexibleBarrier-PT-12a-CTLFireability-02 4576700 m, 113911 m/sec, 22863463 t fired, .
Time elapsed: 36 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 40/257 23/32 FlexibleBarrier-PT-12a-CTLFireability-02 5168414 m, 118342 m/sec, 25660422 t fired, .
Time elapsed: 41 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 45/257 26/32 FlexibleBarrier-PT-12a-CTLFireability-02 5767446 m, 119806 m/sec, 28490640 t fired, .
Time elapsed: 46 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 50/257 29/32 FlexibleBarrier-PT-12a-CTLFireability-02 6356243 m, 117759 m/sec, 31305658 t fired, .
Time elapsed: 51 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 55/257 31/32 FlexibleBarrier-PT-12a-CTLFireability-02 6949241 m, 118599 m/sec, 34186500 t fired, .
Time elapsed: 56 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 8 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 41 (type EXCL) for 40 FlexibleBarrier-PT-12a-CTLFireability-15
lola: time limit : 272 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-15
lola: result : false
lola: markings : 1491
lola: fired transitions : 5480
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 FlexibleBarrier-PT-12a-CTLFireability-14
lola: time limit : 294 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-14
lola: result : false
lola: markings : 4
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 FlexibleBarrier-PT-12a-CTLFireability-10
lola: time limit : 321 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-10
lola: result : true
lola: markings : 14
lola: fired transitions : 58
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 FlexibleBarrier-PT-12a-CTLFireability-09
lola: time limit : 353 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-09
lola: result : true
lola: markings : 7
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 FlexibleBarrier-PT-12a-CTLFireability-08
lola: time limit : 393 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/393 2/32 FlexibleBarrier-PT-12a-CTLFireability-08 443612 m, 88722 m/sec, 3736156 t fired, .
Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 10/393 5/32 FlexibleBarrier-PT-12a-CTLFireability-08 915938 m, 94465 m/sec, 7339967 t fired, .
Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 15/393 7/32 FlexibleBarrier-PT-12a-CTLFireability-08 1387652 m, 94342 m/sec, 10914512 t fired, .
Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 20/393 9/32 FlexibleBarrier-PT-12a-CTLFireability-08 1875732 m, 97616 m/sec, 14504699 t fired, .
Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 25/393 11/32 FlexibleBarrier-PT-12a-CTLFireability-08 2363996 m, 97652 m/sec, 17962790 t fired, .
Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 30/393 14/32 FlexibleBarrier-PT-12a-CTLFireability-08 2963004 m, 119801 m/sec, 21239701 t fired, .
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 35/393 16/32 FlexibleBarrier-PT-12a-CTLFireability-08 3366132 m, 80625 m/sec, 24216851 t fired, .
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 40/393 18/32 FlexibleBarrier-PT-12a-CTLFireability-08 3787117 m, 84197 m/sec, 27253373 t fired, .
Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 45/393 20/32 FlexibleBarrier-PT-12a-CTLFireability-08 4367439 m, 116064 m/sec, 30270528 t fired, .
Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 50/393 24/32 FlexibleBarrier-PT-12a-CTLFireability-08 5202895 m, 167091 m/sec, 33159414 t fired, .
Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 55/393 25/32 FlexibleBarrier-PT-12a-CTLFireability-08 5493060 m, 58033 m/sec, 35958101 t fired, .
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 60/393 27/32 FlexibleBarrier-PT-12a-CTLFireability-08 5869380 m, 75264 m/sec, 38987765 t fired, .
Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 65/393 28/32 FlexibleBarrier-PT-12a-CTLFireability-08 6275676 m, 81259 m/sec, 41947545 t fired, .
Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 70/393 30/32 FlexibleBarrier-PT-12a-CTLFireability-08 6694255 m, 83715 m/sec, 44921784 t fired, .
Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 75/393 32/32 FlexibleBarrier-PT-12a-CTLFireability-08 7111589 m, 83466 m/sec, 47898557 t fired, .
Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 26 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 23 (type EXCL) for 22 FlexibleBarrier-PT-12a-CTLFireability-07
lola: time limit : 432 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/432 1/32 FlexibleBarrier-PT-12a-CTLFireability-07 74138 m, 14827 m/sec, 428936 t fired, .
Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/432 1/32 FlexibleBarrier-PT-12a-CTLFireability-07 151179 m, 15408 m/sec, 876933 t fired, .
Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/432 2/32 FlexibleBarrier-PT-12a-CTLFireability-07 240719 m, 17908 m/sec, 1355934 t fired, .
Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 20/432 2/32 FlexibleBarrier-PT-12a-CTLFireability-07 331262 m, 18108 m/sec, 1841329 t fired, .
Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 25/432 2/32 FlexibleBarrier-PT-12a-CTLFireability-07 422465 m, 18240 m/sec, 2334646 t fired, .
Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 30/432 3/32 FlexibleBarrier-PT-12a-CTLFireability-07 516342 m, 18775 m/sec, 2828508 t fired, .
Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 35/432 3/32 FlexibleBarrier-PT-12a-CTLFireability-07 625477 m, 21827 m/sec, 3373889 t fired, .
Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 40/432 4/32 FlexibleBarrier-PT-12a-CTLFireability-07 732598 m, 21424 m/sec, 3899306 t fired, .
Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 45/432 4/32 FlexibleBarrier-PT-12a-CTLFireability-07 825863 m, 18653 m/sec, 4384763 t fired, .
Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 50/432 5/32 FlexibleBarrier-PT-12a-CTLFireability-07 934045 m, 21636 m/sec, 4926968 t fired, .
Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 55/432 5/32 FlexibleBarrier-PT-12a-CTLFireability-07 1034082 m, 20007 m/sec, 5441567 t fired, .
Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 60/432 6/32 FlexibleBarrier-PT-12a-CTLFireability-07 1124196 m, 18022 m/sec, 5931084 t fired, .
Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 65/432 6/32 FlexibleBarrier-PT-12a-CTLFireability-07 1218056 m, 18772 m/sec, 6430407 t fired, .
Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 70/432 6/32 FlexibleBarrier-PT-12a-CTLFireability-07 1338001 m, 23989 m/sec, 7009066 t fired, .
Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 75/432 7/32 FlexibleBarrier-PT-12a-CTLFireability-07 1458060 m, 24011 m/sec, 7592612 t fired, .
Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 80/432 8/32 FlexibleBarrier-PT-12a-CTLFireability-07 1575074 m, 23402 m/sec, 8176660 t fired, .
Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 85/432 8/32 FlexibleBarrier-PT-12a-CTLFireability-07 1699997 m, 24984 m/sec, 8770578 t fired, .
Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 90/432 9/32 FlexibleBarrier-PT-12a-CTLFireability-07 1825059 m, 25012 m/sec, 9373527 t fired, .
Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 95/432 9/32 FlexibleBarrier-PT-12a-CTLFireability-07 1945157 m, 24019 m/sec, 9960493 t fired, .
Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 100/432 10/32 FlexibleBarrier-PT-12a-CTLFireability-07 2080618 m, 27092 m/sec, 10671790 t fired, .
Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 105/432 10/32 FlexibleBarrier-PT-12a-CTLFireability-07 2215349 m, 26946 m/sec, 11409041 t fired, .
Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 110/432 11/32 FlexibleBarrier-PT-12a-CTLFireability-07 2352666 m, 27463 m/sec, 12176931 t fired, .
Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 115/432 12/32 FlexibleBarrier-PT-12a-CTLFireability-07 2476591 m, 24785 m/sec, 12891383 t fired, .
Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 120/432 12/32 FlexibleBarrier-PT-12a-CTLFireability-07 2611432 m, 26968 m/sec, 13624856 t fired, .
Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 125/432 15/32 FlexibleBarrier-PT-12a-CTLFireability-07 3123310 m, 102375 m/sec, 15080767 t fired, .
Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 130/432 15/32 FlexibleBarrier-PT-12a-CTLFireability-07 3151583 m, 5654 m/sec, 15452934 t fired, .
Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: FINISHED task # 23 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-07
lola: result : true
lola: markings : 3151583
lola: fired transitions : 15452934
lola: time used : 130.000000
lola: memory pages used : 15
lola: LAUNCH task # 20 (type EXCL) for 19 FlexibleBarrier-PT-12a-CTLFireability-06
lola: time limit : 475 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/475 3/32 FlexibleBarrier-PT-12a-CTLFireability-06 478347 m, 95669 m/sec, 1779257 t fired, .
Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/475 4/32 FlexibleBarrier-PT-12a-CTLFireability-06 748702 m, 54071 m/sec, 2686034 t fired, .
Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/475 5/32 FlexibleBarrier-PT-12a-CTLFireability-06 1015601 m, 53379 m/sec, 3600714 t fired, .
Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/475 6/32 FlexibleBarrier-PT-12a-CTLFireability-06 1278042 m, 52488 m/sec, 4493904 t fired, .
Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/475 8/32 FlexibleBarrier-PT-12a-CTLFireability-06 1595145 m, 63420 m/sec, 5494301 t fired, .
Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/475 9/32 FlexibleBarrier-PT-12a-CTLFireability-06 1924067 m, 65784 m/sec, 6512737 t fired, .
Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 35/475 11/32 FlexibleBarrier-PT-12a-CTLFireability-06 2394842 m, 94155 m/sec, 7926454 t fired, .
Time elapsed: 306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 40/475 14/32 FlexibleBarrier-PT-12a-CTLFireability-06 2959144 m, 112860 m/sec, 9446332 t fired, .
Time elapsed: 311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 45/475 16/32 FlexibleBarrier-PT-12a-CTLFireability-06 3469050 m, 101981 m/sec, 10830082 t fired, .
Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 50/475 18/32 FlexibleBarrier-PT-12a-CTLFireability-06 3948624 m, 95914 m/sec, 12160760 t fired, .
Time elapsed: 321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 55/475 20/32 FlexibleBarrier-PT-12a-CTLFireability-06 4415167 m, 93308 m/sec, 13521615 t fired, .
Time elapsed: 326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 60/475 22/32 FlexibleBarrier-PT-12a-CTLFireability-06 4922279 m, 101422 m/sec, 15022415 t fired, .
Time elapsed: 331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 65/475 24/32 FlexibleBarrier-PT-12a-CTLFireability-06 5358199 m, 87184 m/sec, 16285009 t fired, .
Time elapsed: 336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 70/475 26/32 FlexibleBarrier-PT-12a-CTLFireability-06 5756194 m, 79599 m/sec, 17488200 t fired, .
Time elapsed: 341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 75/475 28/32 FlexibleBarrier-PT-12a-CTLFireability-06 6223208 m, 93402 m/sec, 18906600 t fired, .
Time elapsed: 346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 80/475 30/32 FlexibleBarrier-PT-12a-CTLFireability-06 6705379 m, 96434 m/sec, 20185552 t fired, .
Time elapsed: 351 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 85/475 32/32 FlexibleBarrier-PT-12a-CTLFireability-06 7133866 m, 85697 m/sec, 21469990 t fired, .
Time elapsed: 356 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 20 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 361 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 17 (type EXCL) for 16 FlexibleBarrier-PT-12a-CTLFireability-05
lola: time limit : 539 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/539 6/32 FlexibleBarrier-PT-12a-CTLFireability-05 1177405 m, 235481 m/sec, 3767169 t fired, .
Time elapsed: 366 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/539 11/32 FlexibleBarrier-PT-12a-CTLFireability-05 2308435 m, 226206 m/sec, 7032447 t fired, .
Time elapsed: 371 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/539 16/32 FlexibleBarrier-PT-12a-CTLFireability-05 3441062 m, 226525 m/sec, 10055704 t fired, .
Time elapsed: 376 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 20/539 21/32 FlexibleBarrier-PT-12a-CTLFireability-05 4510093 m, 213806 m/sec, 12903240 t fired, .
Time elapsed: 381 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 25/539 25/32 FlexibleBarrier-PT-12a-CTLFireability-05 5530307 m, 204042 m/sec, 15748922 t fired, .
Time elapsed: 386 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 30/539 30/32 FlexibleBarrier-PT-12a-CTLFireability-05 6523915 m, 198721 m/sec, 18505458 t fired, .
Time elapsed: 391 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 17 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 396 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 14 (type EXCL) for 13 FlexibleBarrier-PT-12a-CTLFireability-04
lola: time limit : 640 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/640 5/32 FlexibleBarrier-PT-12a-CTLFireability-04 938127 m, 187625 m/sec, 3882898 t fired, .
Time elapsed: 401 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/640 9/32 FlexibleBarrier-PT-12a-CTLFireability-04 1801127 m, 172600 m/sec, 7399611 t fired, .
Time elapsed: 406 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 15/640 13/32 FlexibleBarrier-PT-12a-CTLFireability-04 2647093 m, 169193 m/sec, 10806978 t fired, .
Time elapsed: 411 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 20/640 16/32 FlexibleBarrier-PT-12a-CTLFireability-04 3466304 m, 163842 m/sec, 14143976 t fired, .
Time elapsed: 416 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 25/640 20/32 FlexibleBarrier-PT-12a-CTLFireability-04 4301970 m, 167133 m/sec, 17326836 t fired, .
Time elapsed: 421 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 30/640 23/32 FlexibleBarrier-PT-12a-CTLFireability-04 5129047 m, 165415 m/sec, 20647690 t fired, .
Time elapsed: 426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 35/640 27/32 FlexibleBarrier-PT-12a-CTLFireability-04 5955964 m, 165383 m/sec, 23923652 t fired, .
Time elapsed: 431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 40/640 31/32 FlexibleBarrier-PT-12a-CTLFireability-04 6795239 m, 167855 m/sec, 27095693 t fired, .
Time elapsed: 436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 14 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 11 (type EXCL) for 10 FlexibleBarrier-PT-12a-CTLFireability-03
lola: time limit : 789 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/789 6/32 FlexibleBarrier-PT-12a-CTLFireability-03 1252991 m, 250598 m/sec, 3646731 t fired, .
Time elapsed: 446 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/789 11/32 FlexibleBarrier-PT-12a-CTLFireability-03 2351827 m, 219767 m/sec, 6835674 t fired, .
Time elapsed: 451 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/789 16/32 FlexibleBarrier-PT-12a-CTLFireability-03 3421574 m, 213949 m/sec, 9942724 t fired, .
Time elapsed: 456 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 20/789 21/32 FlexibleBarrier-PT-12a-CTLFireability-03 4451542 m, 205993 m/sec, 12987961 t fired, .
Time elapsed: 461 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 25/789 26/32 FlexibleBarrier-PT-12a-CTLFireability-03 5535750 m, 216841 m/sec, 16032841 t fired, .
Time elapsed: 466 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 30/789 30/32 FlexibleBarrier-PT-12a-CTLFireability-03 6581368 m, 209123 m/sec, 18768265 t fired, .
Time elapsed: 471 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 11 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 476 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 5 (type EXCL) for 0 FlexibleBarrier-PT-12a-CTLFireability-00
lola: time limit : 1041 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 5/1041 2/32 FlexibleBarrier-PT-12a-CTLFireability-00 431722 m, 86344 m/sec, 2870185 t fired, .
Time elapsed: 481 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 10/1041 5/32 FlexibleBarrier-PT-12a-CTLFireability-00 1058692 m, 125394 m/sec, 5854591 t fired, .
Time elapsed: 486 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 15/1041 6/32 FlexibleBarrier-PT-12a-CTLFireability-00 1297484 m, 47758 m/sec, 8585999 t fired, .
Time elapsed: 491 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 20/1041 9/32 FlexibleBarrier-PT-12a-CTLFireability-00 1808378 m, 102178 m/sec, 11438058 t fired, .
Time elapsed: 496 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 25/1041 13/32 FlexibleBarrier-PT-12a-CTLFireability-00 2786034 m, 195531 m/sec, 14033337 t fired, .
Time elapsed: 501 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 30/1041 18/32 FlexibleBarrier-PT-12a-CTLFireability-00 3888962 m, 220585 m/sec, 16843858 t fired, .
Time elapsed: 506 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 35/1041 22/32 FlexibleBarrier-PT-12a-CTLFireability-00 4741212 m, 170450 m/sec, 18933822 t fired, .
Time elapsed: 511 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 40/1041 26/32 FlexibleBarrier-PT-12a-CTLFireability-00 5789186 m, 209594 m/sec, 21595514 t fired, .
Time elapsed: 516 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 45/1041 31/32 FlexibleBarrier-PT-12a-CTLFireability-00 6773928 m, 196948 m/sec, 24215683 t fired, .
Time elapsed: 521 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 5 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ 0 1 0 0 2 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-12a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 526 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 3 (type EXCL) for 0 FlexibleBarrier-PT-12a-CTLFireability-00
lola: time limit : 1537 sec
lola: memory limit: 32 pages
lola: FINISHED task # 3 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-00
lola: result : false
lola: markings : 6
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 FlexibleBarrier-PT-12a-CTLFireability-13
lola: time limit : 3074 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for FlexibleBarrier-PT-12a-CTLFireability-13
lola: result : false
lola: markings : 8
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 13
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-12a-CTLFireability-00: DISJ unknown DISJ
FlexibleBarrier-PT-12a-CTLFireability-02: CTL unknown AGGR
FlexibleBarrier-PT-12a-CTLFireability-03: CTL unknown AGGR
FlexibleBarrier-PT-12a-CTLFireability-04: CTL unknown AGGR
FlexibleBarrier-PT-12a-CTLFireability-05: CTL unknown AGGR
FlexibleBarrier-PT-12a-CTLFireability-06: CTL unknown AGGR
FlexibleBarrier-PT-12a-CTLFireability-07: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-08: CTL unknown AGGR
FlexibleBarrier-PT-12a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-13: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-12a-CTLFireability-15: CTL false CTL model checker
Time elapsed: 526 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FlexibleBarrier-PT-12a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FlexibleBarrier-PT-12a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838853200506"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FlexibleBarrier-PT-12a.tgz
mv FlexibleBarrier-PT-12a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;