Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838853000414.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FamilyReunion-PT-L00050M0005C002P002G001, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838853000414
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 9.6M
-rw-r--r-- 1 mcc users 113K Feb 26 12:12 CTLCardinality.txt
-rw-r--r-- 1 mcc users 682K Feb 26 12:12 CTLCardinality.xml
-rw-r--r-- 1 mcc users 198K Feb 26 12:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 726K Feb 26 12:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 32K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 146K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 81K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 238K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 197K Feb 26 12:36 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 1.2M Feb 26 12:36 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 297K Feb 26 12:26 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 994K Feb 26 12:26 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 35K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 4.7M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1678475374684

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-PT-L00050M0005C002P002G001
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 19:09:36] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-10 19:09:36] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 19:09:36] [INFO ] Load time of PNML (sax parser for PT used): 302 ms
[2023-03-10 19:09:36] [INFO ] Transformed 12194 places.
[2023-03-10 19:09:36] [INFO ] Transformed 10560 transitions.
[2023-03-10 19:09:36] [INFO ] Parsed PT model containing 12194 places and 10560 transitions and 32238 arcs in 430 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 749 ms.
Working with output stream class java.io.PrintStream
Reduce places removed 17 places and 0 transitions.
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 3 resets, run finished after 1096 ms. (steps per millisecond=9 ) properties (out of 15) seen :5
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 184 ms. (steps per millisecond=54 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 296 ms. (steps per millisecond=33 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 339 ms. (steps per millisecond=29 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 546 ms. (steps per millisecond=18 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 10) seen :0
Running SMT prover for 10 properties.
// Phase 1: matrix 10560 rows 12177 cols
[2023-03-10 19:09:41] [INFO ] Computed 2768 place invariants in 668 ms
[2023-03-10 19:09:46] [INFO ] [Real]Absence check using 149 positive place invariants in 309 ms returned sat
[2023-03-10 19:09:47] [INFO ] [Real]Absence check using 149 positive and 2619 generalized place invariants in 1313 ms returned sat
[2023-03-10 19:09:48] [INFO ] After 5130ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:10
[2023-03-10 19:09:51] [INFO ] [Nat]Absence check using 149 positive place invariants in 311 ms returned sat
[2023-03-10 19:09:52] [INFO ] [Nat]Absence check using 149 positive and 2619 generalized place invariants in 1361 ms returned sat
[2023-03-10 19:10:13] [INFO ] After 15066ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :7
[2023-03-10 19:10:13] [INFO ] After 15086ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :7
Attempting to minimize the solution found.
Minimization took 4 ms.
[2023-03-10 19:10:13] [INFO ] After 25081ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :7
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 10 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 5072 out of 12177 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 12177/12177 places, 10560/10560 transitions.
Graph (complete) has 18927 edges and 12177 vertex of which 12115 are kept as prefixes of interest. Removing 62 places using SCC suffix rule.25 ms
Discarding 62 places :
Also discarding 0 output transitions
Discarding 1517 places :
Implicit places reduction removed 1517 places
Drop transitions removed 885 transitions
Trivial Post-agglo rules discarded 885 transitions
Performed 885 trivial Post agglomeration. Transition count delta: 885
Iterating post reduction 0 with 2402 rules applied. Total rules applied 2403 place count 10598 transition count 9675
Reduce places removed 885 places and 0 transitions.
Performed 909 Post agglomeration using F-continuation condition.Transition count delta: 909
Iterating post reduction 1 with 1794 rules applied. Total rules applied 4197 place count 9713 transition count 8766
Reduce places removed 909 places and 0 transitions.
Iterating post reduction 2 with 909 rules applied. Total rules applied 5106 place count 8804 transition count 8766
Performed 405 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 405 Pre rules applied. Total rules applied 5106 place count 8804 transition count 8361
Deduced a syphon composed of 405 places in 28 ms
Ensure Unique test removed 150 places
Reduce places removed 555 places and 0 transitions.
Iterating global reduction 3 with 960 rules applied. Total rules applied 6066 place count 8249 transition count 8361
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 3 with 4 rules applied. Total rules applied 6070 place count 8245 transition count 8361
Discarding 710 places :
Symmetric choice reduction at 4 with 710 rule applications. Total rules 6780 place count 7535 transition count 7601
Iterating global reduction 4 with 710 rules applied. Total rules applied 7490 place count 7535 transition count 7601
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 8 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 7492 place count 7534 transition count 7600
Performed 47 Post agglomeration using F-continuation condition.Transition count delta: 0
Deduced a syphon composed of 47 places in 9 ms
Reduce places removed 47 places and 0 transitions.
Iterating global reduction 4 with 94 rules applied. Total rules applied 7586 place count 7487 transition count 7600
Free-agglomeration rule applied 3 times.
Iterating global reduction 4 with 3 rules applied. Total rules applied 7589 place count 7487 transition count 7597
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 7592 place count 7484 transition count 7597
Applied a total of 7592 rules in 2796 ms. Remains 7484 /12177 variables (removed 4693) and now considering 7597/10560 (removed 2963) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2806 ms. Remains : 7484/12177 places, 7597/10560 transitions.
Incomplete random walk after 10000 steps, including 4 resets, run finished after 602 ms. (steps per millisecond=16 ) properties (out of 8) seen :1
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 319 ms. (steps per millisecond=31 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 565 ms. (steps per millisecond=17 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
// Phase 1: matrix 7597 rows 7484 cols
[2023-03-10 19:10:18] [INFO ] Computed 1042 place invariants in 179 ms
[2023-03-10 19:10:20] [INFO ] [Real]Absence check using 102 positive place invariants in 162 ms returned sat
[2023-03-10 19:10:20] [INFO ] [Real]Absence check using 102 positive and 940 generalized place invariants in 423 ms returned sat
[2023-03-10 19:10:20] [INFO ] After 2088ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:7
[2023-03-10 19:10:22] [INFO ] [Nat]Absence check using 102 positive place invariants in 140 ms returned sat
[2023-03-10 19:10:22] [INFO ] [Nat]Absence check using 102 positive and 940 generalized place invariants in 399 ms returned sat
[2023-03-10 19:10:45] [INFO ] After 21964ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :6
[2023-03-10 19:10:45] [INFO ] After 21979ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :6
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-03-10 19:10:45] [INFO ] After 25096ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :6
Fused 7 Parikh solutions to 4 different solutions.
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 3 properties in 252 ms.
Support contains 394 out of 7484 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 7484/7484 places, 7597/7597 transitions.
Graph (complete) has 11906 edges and 7484 vertex of which 6855 are kept as prefixes of interest. Removing 629 places using SCC suffix rule.4 ms
Discarding 629 places :
Also discarding 380 output transitions
Drop transitions removed 380 transitions
Drop transitions removed 191 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 192 transitions.
Discarding 306 places :
Implicit places reduction removed 306 places
Drop transitions removed 3089 transitions
Trivial Post-agglo rules discarded 3089 transitions
Performed 3089 trivial Post agglomeration. Transition count delta: 3089
Iterating post reduction 0 with 3587 rules applied. Total rules applied 3588 place count 6549 transition count 3936
Reduce places removed 3089 places and 0 transitions.
Ensure Unique test removed 102 transitions
Reduce isomorphic transitions removed 102 transitions.
Discarding 51 places :
Implicit places reduction removed 51 places
Drop transitions removed 101 transitions
Trivial Post-agglo rules discarded 101 transitions
Performed 101 trivial Post agglomeration. Transition count delta: 101
Iterating post reduction 1 with 3343 rules applied. Total rules applied 6931 place count 3409 transition count 3733
Reduce places removed 101 places and 0 transitions.
Performed 402 Post agglomeration using F-continuation condition.Transition count delta: 402
Iterating post reduction 2 with 503 rules applied. Total rules applied 7434 place count 3308 transition count 3331
Reduce places removed 402 places and 0 transitions.
Iterating post reduction 3 with 402 rules applied. Total rules applied 7836 place count 2906 transition count 3331
Performed 293 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 293 Pre rules applied. Total rules applied 7836 place count 2906 transition count 3038
Deduced a syphon composed of 293 places in 2 ms
Ensure Unique test removed 151 places
Reduce places removed 444 places and 0 transitions.
Iterating global reduction 4 with 737 rules applied. Total rules applied 8573 place count 2462 transition count 3038
Discarding 47 places :
Implicit places reduction removed 47 places
Iterating post reduction 4 with 47 rules applied. Total rules applied 8620 place count 2415 transition count 3038
Performed 46 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 46 Pre rules applied. Total rules applied 8620 place count 2415 transition count 2992
Deduced a syphon composed of 46 places in 1 ms
Reduce places removed 46 places and 0 transitions.
Iterating global reduction 5 with 92 rules applied. Total rules applied 8712 place count 2369 transition count 2992
Discarding 397 places :
Symmetric choice reduction at 5 with 397 rule applications. Total rules 9109 place count 1972 transition count 2402
Iterating global reduction 5 with 397 rules applied. Total rules applied 9506 place count 1972 transition count 2402
Discarding 51 places :
Implicit places reduction removed 51 places
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 5 with 57 rules applied. Total rules applied 9563 place count 1921 transition count 2396
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 6 with 6 rules applied. Total rules applied 9569 place count 1915 transition count 2396
Performed 57 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 7 with 57 Pre rules applied. Total rules applied 9569 place count 1915 transition count 2339
Deduced a syphon composed of 57 places in 1 ms
Reduce places removed 57 places and 0 transitions.
Iterating global reduction 7 with 114 rules applied. Total rules applied 9683 place count 1858 transition count 2339
Discarding 38 places :
Symmetric choice reduction at 7 with 38 rule applications. Total rules 9721 place count 1820 transition count 2301
Iterating global reduction 7 with 38 rules applied. Total rules applied 9759 place count 1820 transition count 2301
Ensure Unique test removed 38 transitions
Reduce isomorphic transitions removed 38 transitions.
Iterating post reduction 7 with 38 rules applied. Total rules applied 9797 place count 1820 transition count 2263
Performed 172 Post agglomeration using F-continuation condition.Transition count delta: 172
Deduced a syphon composed of 172 places in 1 ms
Ensure Unique test removed 6 places
Reduce places removed 178 places and 0 transitions.
Iterating global reduction 8 with 350 rules applied. Total rules applied 10147 place count 1642 transition count 2091
Free-agglomeration rule applied 4 times.
Iterating global reduction 8 with 4 rules applied. Total rules applied 10151 place count 1642 transition count 2087
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 8 with 4 rules applied. Total rules applied 10155 place count 1638 transition count 2087
Free-agglomeration rule (complex) applied 201 times.
Iterating global reduction 9 with 201 rules applied. Total rules applied 10356 place count 1638 transition count 1900
Ensure Unique test removed 102 places
Reduce places removed 303 places and 0 transitions.
Iterating post reduction 9 with 303 rules applied. Total rules applied 10659 place count 1335 transition count 1900
Performed 46 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 10 with 46 Pre rules applied. Total rules applied 10659 place count 1335 transition count 1854
Deduced a syphon composed of 46 places in 1 ms
Reduce places removed 46 places and 0 transitions.
Iterating global reduction 10 with 92 rules applied. Total rules applied 10751 place count 1289 transition count 1854
Partial Free-agglomeration rule applied 20 times.
Drop transitions removed 20 transitions
Iterating global reduction 10 with 20 rules applied. Total rules applied 10771 place count 1289 transition count 1854
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 10 with 1 rules applied. Total rules applied 10772 place count 1288 transition count 1853
Applied a total of 10772 rules in 920 ms. Remains 1288 /7484 variables (removed 6196) and now considering 1853/7597 (removed 5744) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 920 ms. Remains : 1288/7484 places, 1853/7597 transitions.
Incomplete random walk after 10000 steps, including 16 resets, run finished after 199 ms. (steps per millisecond=50 ) properties (out of 4) seen :2
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
// Phase 1: matrix 1853 rows 1288 cols
[2023-03-10 19:10:47] [INFO ] Computed 181 place invariants in 22 ms
[2023-03-10 19:10:47] [INFO ] [Real]Absence check using 0 positive and 181 generalized place invariants in 47 ms returned sat
[2023-03-10 19:10:47] [INFO ] After 239ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-10 19:10:47] [INFO ] [Nat]Absence check using 0 positive and 181 generalized place invariants in 48 ms returned sat
[2023-03-10 19:10:49] [INFO ] After 1665ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-10 19:10:50] [INFO ] After 2836ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 1080 ms.
[2023-03-10 19:10:51] [INFO ] After 4190ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Finished Parikh walk after 125 steps, including 0 resets, run visited all 1 properties in 3 ms. (steps per millisecond=41 )
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 2 properties in 20 ms.
All properties solved without resorting to model-checking.
Total runtime 75717 ms.
starting LoLA
BK_INPUT FamilyReunion-PT-L00050M0005C002P002G001
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678475671456

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 49 (type SKEL/FNDP) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SKEL/EQUN) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SKEL/SRCH) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type SKEL/SRCH) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: result : true
lola: markings : 214
lola: fired transitions : 213
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 49 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 50 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 52 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00 (obsolete)
lola: FINISHED task # 49 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 212
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-50.sara.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Rule S: 0 transitions removed,0 places removed
lola: LAUNCH task # 56 (type SKEL/FNDP) for 18 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type SKEL/EQUN) for 18 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SKEL/SRCH) for 18 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SKEL/SRCH) for 18 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 56 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: result : true
lola: fired transitions : 54
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 57 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 60 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 61 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type SKEL/FNDP) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type SKEL/EQUN) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SKEL/SRCH) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SKEL/SRCH) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 67 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: result : true
lola: markings : 211
lola: fired transitions : 210
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 64 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 65 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 68 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01 (obsolete)
lola: FINISHED task # 64 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 209
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-57.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-65.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 65 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: result : true

lola: FINISHED task # 57 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 71 (type SKEL/FNDP) for 24 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type SKEL/EQUN) for 24 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 74 (type SKEL/SRCH) for 24 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SKEL/SRCH) for 24 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 71 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 72 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 74 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 75 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-72.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH INITIAL
lola: LAUNCH task # 13 (type CNST) for 12 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 13 (type CNST) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04
lola: result : true
lola: LAUNCH INITIAL
lola: LAUNCH task # 10 (type CNST) for 9 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 10 (type CNST) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 79 (type SKEL/FNDP) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type SKEL/EQUN) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 82 (type SKEL/SRCH) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SKEL/SRCH) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 79 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 7
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 80 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 82 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 83 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 87 (type SKEL/FNDP) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type SKEL/EQUN) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type SKEL/SRCH) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 91 (type SKEL/SRCH) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 87 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 2422
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 88 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 90 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 91 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-88.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 80 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05: EF 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 4
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 4
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12: AG 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14: EF 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 179 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 94 (type SKEL/FNDP) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type SKEL/EQUN) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 97 (type SKEL/SRCH) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 98 (type SKEL/SRCH) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 97 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02
lola: result : false
lola: markings : 868
lola: fired transitions : 867
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 94 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 95 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 98 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 102 (type SKEL/FNDP) for 33 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type SKEL/EQUN) for 33 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 105 (type SKEL/SRCH) for 33 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type SKEL/SRCH) for 33 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 95 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02
lola: result : false
lola: FINISHED task # 105 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true
lola: markings : 20
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 102 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 103 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 106 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: FINISHED task # 94 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 23141
lola: tried executions : 28
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 102 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 18
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-103.sara.
sara: place or transition ordering is non-deterministic

lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 103 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true

lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 88 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 109 (type SKEL/FNDP) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 110 (type SKEL/EQUN) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 112 (type SKEL/SRCH) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type SKEL/SRCH) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 113 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : true
lola: markings : 629
lola: fired transitions : 628
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 109 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 110 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 112 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 109 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 611
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-110.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 110 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 117 (type SKEL/FNDP) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type SKEL/EQUN) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 120 (type SKEL/SRCH) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 121 (type SKEL/SRCH) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 120 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: result : true
lola: markings : 27
lola: fired transitions : 26
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 117 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 118 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 121 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10 (obsolete)
lola: FINISHED task # 117 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: result : true
lola: fired transitions : 25
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-118.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 125 (type SKEL/FNDP) for 39 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 126 (type SKEL/EQUN) for 39 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type SKEL/SRCH) for 39 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 129 (type SKEL/SRCH) for 39 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 128 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: result : true
lola: markings : 70
lola: fired transitions : 69
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 125 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 126 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 129 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13 (obsolete)
lola: FINISHED task # 125 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 68
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: place or transition ordering is non-deterministic


sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-126.sara.
lola: FINISHED task # 118 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: result : true
lola: FINISHED task # 72 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12: AG 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13: AG 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14: EF 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 184 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12: AG 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13: AG 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14: EF 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 189 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 136 (type EXCL) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: time limit : 262 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 132 (type FNDP) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 133 (type EQUN) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 135 (type SRCH) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 135 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 132 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 133 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 136 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 132 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-133.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 133 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 143 (type EXCL) for 33 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 284 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 139 (type FNDP) for 33 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 140 (type EQUN) for 33 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 142 (type SRCH) for 33 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 142 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 139 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 140 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 143 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: FINISHED task # 139 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-140.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 140 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true

lola: FINISHED task # 126 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 150 (type EXCL) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: time limit : 309 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 146 (type FNDP) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 147 (type EQUN) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 149 (type SRCH) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 150 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: result : true
lola: markings : 113
lola: fired transitions : 112
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 146 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 147 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 149 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01 (obsolete)
lola: FINISHED task # 146 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 111
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01: AG false tandem / relaxed
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12: AG false tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07: AG 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14: EF 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 194 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-147.sara.

lola: FINISHED task # 50 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 156 (type EXCL) for 24 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: time limit : 340 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 152 (type FNDP) for 24 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 153 (type EQUN) for 24 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 155 (type SRCH) for 24 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 152 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 153 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 155 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 156 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-153.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 163 (type EXCL) for 27 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09
lola: time limit : 378 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 159 (type FNDP) for 27 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 160 (type EQUN) for 27 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 162 (type SRCH) for 27 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 162 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09
lola: result : true
lola: markings : 14
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 159 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 160 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 163 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 170 (type EXCL) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 425 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 166 (type FNDP) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 167 (type EQUN) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 169 (type SRCH) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 159 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09
lola: result : true
lola: fired transitions : 12
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: planning for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02 stopped (result already fixed).
lola: FINISHED task # 166 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 1162
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 167 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 169 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 170 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 177 (type EXCL) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: time limit : 486 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 173 (type FNDP) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 174 (type EQUN) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 176 (type SRCH) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-160.sara.
lola: FINISHED task # 176 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: result : true
lola: markings : 14
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 173 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 174 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 177 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10 (obsolete)
lola: FINISHED task # 173 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 1
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-167.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-174.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 184 (type EXCL) for 39 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: time limit : 567 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 180 (type FNDP) for 39 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 181 (type EQUN) for 39 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 183 (type SRCH) for 39 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 180 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 24
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 181 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 183 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 184 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13 (obsolete)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01: AG false tandem / relaxed
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06: EF 0 0 0 0 2 0 0 3
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14: EF 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 199 secs. Pages in use: 3
# running tasks: 0 of 4 Visible: 16

sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-181.sara.
lola: FINISHED task # 147 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 190 (type EXCL) for 42 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14
lola: time limit : 680 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 186 (type FNDP) for 42 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 187 (type EQUN) for 42 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 189 (type SRCH) for 42 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 186 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 62
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 187 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 189 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 190 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-187.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 196 (type EXCL) for 45 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15
lola: time limit : 849 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 192 (type FNDP) for 45 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 193 (type EQUN) for 45 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 195 (type SRCH) for 45 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 192 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15
lola: result : true
lola: fired transitions : 5
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 195 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15
lola: result : true
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 193 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 196 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-193.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01: AG false tandem / relaxed
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06: EF 0 0 0 0 2 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 204 secs. Pages in use: 3
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 202 (type EXCL) for 18 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: time limit : 1131 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 198 (type FNDP) for 18 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 199 (type EQUN) for 18 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 201 (type SRCH) for 18 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 201 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: result : true
lola: markings : 51
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 198 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 199 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 202 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06 (obsolete)
lola: FINISHED task # 198 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06
lola: result : true
lola: fired transitions : 49
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-199.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01: AG false tandem / relaxed
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 209 secs. Pages in use: 3
# running tasks: 0 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 208 (type EXCL) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 1694 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 204 (type FNDP) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 205 (type EQUN) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 207 (type SRCH) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711

lola: FINISHED task # 204 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 424
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 205 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 207 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 208 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-205.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 174 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01: AG false tandem / relaxed
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00: EF 0 0 0 0 3 0 0 2

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 214 secs. Pages in use: 3
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 214 (type EXCL) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: time limit : 3385 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 210 (type FNDP) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 211 (type EQUN) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 213 (type SRCH) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 210 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 230
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 211 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 213 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 214 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-00: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-01: AG false tandem / relaxed
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-02: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-03: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-04: INITIAL true preprocessing
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-05: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-06: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-07: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-10: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-11: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-12: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-13: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-14: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-15: EF true findpath


Time elapsed: 216 secs. Pages in use: 3

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00050M0005C002P002G001"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FamilyReunion-PT-L00050M0005C002P002G001, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838853000414"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00050M0005C002P002G001.tgz
mv FamilyReunion-PT-L00050M0005C002P002G001 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;