MCC'2023- Execution of r167-tall-167838852900332

About the Execution of LoLa+red for FamilyReunion-COL-L00200M0020C010P010G005

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16152.972	3600000.00	3879037.00	26839.20	???????F??FFFF?T	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852900332.qcow2',
Waiting for the VM to be ready (probing ssh)
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============================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FamilyReunion-COL-L00200M0020C010P010G005,
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852900332
=====================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 604K
-rw-r--r-- 1 mcc users 7.8K Feb 26 17:35 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 26 17:35 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 26 15:53 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 15:53 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDe
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVe
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 21:31 ReachabilityCardina
-rw-r--r-- 1 mcc users 120K Feb 26 21:31 ReachabilityCardina
-rw-r--r-- 1 mcc users 10K Feb 26 20:18 ReachabilityFireabi
-rw-r--r-- 1 mcc users 63K Feb 26 20:18 ReachabilityFireabi
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 146K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi
FORMULA_NAME FamilyReunion-COL-L00200M0020C010P010G005-LTLFi

=== Now, execution of the tool begins

BK_START 1678453782038

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L00200M0020C010P010G005
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 13:09:43] [INFO ] Running its-tools with
[2023-03-10 13:09:43] [INFO ] Parsing pnml file :
[2023-03-10 13:09:43] [INFO ] Detected file is not
log4j:WARN No appenders could be found for logger (org.apach
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig
[2023-03-10 13:09:43] [WARNING] Using fallBack plugin,
[2023-03-10 13:09:44] [INFO ] Load time of PNML (colored
[2023-03-10 13:09:44] [INFO ] Detected 5 constant
[2023-03-10 13:09:44] [INFO ] Imported 104 HL places
Parsed 16 properties from file /home/mcc/execution/LTLFireability.xml
Working with output stream class java.io.PrintStream
[2023-03-10 13:09:44] [INFO ] Built PT skeleton of
[2023-03-10 13:09:44] [INFO ] Skeletonized 16 HLPN
Initial state reduction rules removed 4 formulas.
FORMULA FamilyReunion-COL-L00200M0020C010P010G005-LTLFireability-07
FORMULA FamilyReunion-COL-L00200M0020C010P010G005-LTL
FORMULA FamilyReunion-COL-L00200M0020C010P010G005-LTL
FORMULA FamilyReunion-COL-L00200M0020C010P010G005-LTL
Computed a total of 104 stabilizing places and
Complete graph has no SCC; deadlocks are unavoidable.
Detected that all paths lead to deadlock. Applying
Remains 12 properties that can be checked using skeleton
Reduce places removed 5 places and 0 transitions.
Computed a total of 99 stabilizing places and 66 stable
Complete graph has no SCC; deadlocks are unavoidable.
Detected that all paths lead to deadlock. Applying
Incomplete random walk after 10102 steps, including
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10000 steps,
Incomplete Best-First random walk after 10001 steps,
Running SMT prover for 7 properties.
// Phase 1: matrix 66 rows 99 cols
[2023-03-10 13:09:44] [INFO ] Computed 33 place invariants
[2023-03-10 13:09:45] [INFO ] [Real]Absence check using
[2023-03-10 13:09:45] [INFO ] [Real]Absence check using
[2023-03-10 13:09:45] [INFO ] After 68ms SMT Verify
[2023-03-10 13:09:45] [INFO ] After 109ms SMT Verify
Attempting to minimize the solution found.
Minimization took 22 ms.
[2023-03-10 13:09:45] [INFO ] After 317ms SMT Verify
[2023-03-10 13:09:45] [INFO ] [Nat]Absence check using
[2023-03-10 13:09:45] [INFO ] [Nat]Absence check using
[2023-03-10 13:09:45] [INFO ] After 86ms SMT Verify
[2023-03-10 13:09:45] [INFO ] After 152ms SMT Verify
Attempting to minimize the solution found.
Minimization took 40 ms.
[2023-03-10 13:09:45] [INFO ] After 334ms SMT Verify
Fused 7 Parikh solutions to 3 different solutions.
Finished Parikh walk after 223 steps, including 0
Parikh walk visited 7 properties in 6 ms.
[2023-03-10 13:09:45] [INFO ] Flatten gal took : 56 ms
[2023-03-10 13:09:45] [INFO ] Flatten gal took : 7 ms
Transition Gate2ANDJoin forces synchronizations/join
Transition ReceiveLangChoice forces synchronizations/join
Symmetric sort wr.t. initial and guards and successors
Symmetric sort wr.t. initial detected :CINFORMI
Symmetric sort wr.t. initial and guards detected :CINFORMI
Applying symmetric unfolding of full symmetric sort
Transition Gate1ANDJoin forces synchronizations/join
Symmetric sort wr.t. initial and guards and successors
Symmetric sort wr.t. initial detected :GovernmentCommission
Symmetric sort wr.t. initial and guards detected :Government
Applying symmetric unfolding of full symmetric sort
Symmetric sort wr.t. initial and guards and successors
Symmetric sort wr.t. initial detected :Response
Transition SendClearanceToRel : guard parameter $r(Response:2)
[2023-03-10 13:09:46] [INFO ] Unfolded HLPN to a
[2023-03-10 13:09:46] [INFO ] Unfolded 12 HLPN properties
[2023-03-10 13:09:46] [INFO ] Reduced 4020 identical
Deduced a syphon composed of 201 places in 363 ms
Reduce places removed 237 places and 0 transitions.
Support contains 39397 out of 128732 places. Attempting
Starting structural reductions in LTL mode, iteration
Reduce places removed 649 places and 0 transitions.
Discarding 17487 places :
Implicit places reduction removed 17487 places
Iterating post reduction 0 with 18136 rules applied.
Applied a total of 18136 rules in 7423 ms. Remains
// Phase 1: matrix 110159 rows 110596 cols
[2023-03-10 13:10:54] [INFO ] Computed 12668 place
[2023-03-10 13:11:03] [INFO ] SMT solver returned
[2023-03-10 13:11:03] [INFO ] Implicit Places using
Implicit Place search using SMT only with invariants
[2023-03-10 13:11:03] [INFO ] Invariant cache hit.
[2023-03-10 13:11:12] [INFO ] SMT solver returned
[2023-03-10 13:11:12] [INFO ] Dead Transitions using
Starting structural reductions in LTL mode, iteration
Finished structural reductions in LTL mode , in 1 iterations
Support contains 39397 out of 110596 places after structural
[2023-03-10 13:11:16] [INFO ] Flatten gal took : 3303 ms
[2023-03-10 13:11:20] [INFO ] Flatten gal took : 2967 ms
[2023-03-10 13:11:27] [INFO ] Input system was already
Support contains 35176 out of 110596 places (down from
Incomplete random walk after 10000 steps, including
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Incomplete Best-First random walk after 10001 steps,
Running SMT prover for 10 properties.
[2023-03-10 13:11:38] [INFO ] Invariant cache hit.
java.lang.RuntimeException: SMT solver raised an error
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckRes
at fr.lip6.move.gal.structural.smt.DeadlockTester.assertInv
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPos
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnrea
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnrea
at fr.lip6.move.gal.application.solver.ReachabilitySolver.a
at fr.lip6.move.gal.application.solver.logic.AtomicReducerS
at fr.lip6.move.gal.application.solver.logic.AtomicReducerS
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolve
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolve
at fr.lip6.move.gal.application.Application.startNoEx(Appli
at fr.lip6.move.gal.application.Application.start(Applicati
at fr.lip6.move.gal.itscl.application.Application.start(App
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(Ec
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLaun
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLaun
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(Ecli
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(Ecli
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.
at java.base/jdk.internal.reflect.DelegatingMethodAccessorI
at java.base/java.lang.reflect.Method.invoke(Method.java:56
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.j
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-10 13:12:03] [WARNING] SMT solver failed with
[2023-03-10 13:12:03] [INFO ] After 25068ms SMT Verify
Fused 10 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 10654 out of 110596 places. Attempting
Starting structural reductions in REACHABILITY mode,
Graph (complete) has 155373 edges and 110596 vertex
Discarding 413 places :
Also discarding 212 output transitions
Drop transitions removed 212 transitions
Drop transitions removed 402 transitions
Reduce isomorphic transitions removed 402 transitions.
Discarding 8643 places :
Implicit places reduction removed 8643 places
Drop transitions removed 55275 transitions
Trivial Post-agglo rules discarded 55275 transitions
Performed 55275 trivial Post agglomeration. Transition
Iterating post reduction 0 with 64320 rules applied.
Reduce places removed 55275 places and 0 transitions.
Performed 4623 Post agglomeration using F-continuation
Iterating post reduction 1 with 59898 rules applied.
Reduce places removed 4623 places and 0 transitions.
Iterating post reduction 2 with 4623 rules applied.
Performed 7638 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 3 with 7638 Pre rules applied.
Deduced a syphon composed of 7638 places in 36 ms
Ensure Unique test removed 2814 places
Reduce places removed 10452 places and 0 transitions.
Iterating global reduction 3 with 18090 rules applied.
Drop transitions removed 201 transitions
Trivial Post-agglo rules discarded 201 transitions
Performed 201 trivial Post agglomeration. Transition
Iterating post reduction 3 with 201 rules applied.
Reduce places removed 201 places and 0 transitions.
Iterating post reduction 4 with 201 rules applied.
Performed 4824 Post agglomeration using F-continuation
Deduced a syphon composed of 4824 places in 23 ms
Reduce places removed 4824 places and 0 transitions.
Iterating global reduction 5 with 9648 rules applied.
Free-agglomeration rule applied 2211 times.
Iterating global reduction 5 with 2211 rules applied.
Reduce places removed 2211 places and 0 transitions.
Iterating post reduction 5 with 2211 rules applied.
Free-agglomeration rule (complex) applied 4623 times.
Iterating global reduction 6 with 4623 rules applied.
Ensure Unique test removed 201 places
Reduce places removed 4824 places and 0 transitions.
Iterating post reduction 6 with 4824 rules applied.
Discarding 2030 places :
Symmetric choice reduction at 7 with 2030 rule applications. Total rules
Iterating global reduction 7 with 2030 rules applied.
Applied a total of 174911 rules in 39155 ms. Remains
Finished structural reductions in REACHABILITY mode
Finished random walk after 2035 steps, including 0
FORMULA FamilyReunion-COL-L00200M0020C010P010G005-LTLFireability-11
FORMULA FamilyReunion-COL-L00200M0020C010P010G005-LTL
Computed a total of 110596 stabilizing places and
Complete graph has no SCC; deadlocks are unavoidable.
Detected that all paths lead to deadlock. Applying
Running Spot : '/home/mcc/BenchKit/itstools/itstools/plugins
Support contains 6432 out of 110596 places. Attempting
Starting structural reductions in LTL mode, iteration
Discarding 8643 places :
Implicit places reduction removed 8643 places
Iterating post reduction 0 with 8643 rules applied.
Applied a total of 8643 rules in 2063 ms. Remains 101953
// Phase 1: matrix 110159 rows 101953 cols
[2023-03-10 13:13:07] [INFO ] Computed 4025 place
[2023-03-10 13:13:16] [INFO ] SMT solver returned
[2023-03-10 13:13:16] [INFO ] Implicit Places using
Implicit Place search using SMT only with invariants
[2023-03-10 13:13:16] [INFO ] Invariant cache hit.
[2023-03-10 13:13:24] [INFO ] SMT solver returned
[2023-03-10 13:13:24] [INFO ] Dead Transitions using
Starting structural reductions in LTL mode, iteration
Finished structural reductions in LTL mode , in 1 iterations
Stuttering acceptance computed with spot in 307 ms
Running random walk in product with property : FamilyReunion
Product exploration timeout after 40150 steps with
Product exploration timeout after 40000 steps with
Computed a total of 101953 stabilizing places and 110159
Complete graph has no SCC; deadlocks are unavoidable.
Detected that all paths lead to deadlock. Applying
Detected that all paths lead to deadlock. Applying
Could not satisfy deadlock states : solver returned sat
Knowledge obtained : [(AND (NOT p1) (NOT p0)), true,
False Knowledge obtained : []
Knowledge based reduction with 4 factoid took 206 ms.
Stuttering acceptance computed with spot in 194 ms
Finished random walk after 2263 steps, including 0
Knowledge obtained : [(AND (NOT p1) (NOT p0)), true,
False Knowledge obtained : [(F (AND p1 (NOT p0))),
Knowledge based reduction with 4 factoid took 252 ms.
Stuttering acceptance computed with spot in 178 ms
Stuttering acceptance computed with spot in 168 ms
starting LoLA
BK_INPUT FamilyReunion-COL-L00200M0020C010P010G005
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../..
current directory: /home/mcc/execution
LTLFireability

FORMULA FamilyReunion-COL-L00200M0020C010P010G005-LTLFireability-12
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 9871000 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16046068 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//it
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/LTLFireabil
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:493
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
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lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
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lola: findlow criterion violated for transition 26
lola: CHECK FINDLOW FOR TRANS AppointReceived
lola: INVENT VAR FOR PLACE l31
lola: INVENT VAR FOR PLACE cl2
lola: CHECK EQ TRANS AppointReceived
lola: findlow criterion violated for transition 29
lola: CHECK FINDLOW FOR TRANS SendClearanceToRel
lola: INVENT VAR FOR PLACE l39
lola: CHECK EQ TRANS SendClearanceToRel
lola: findlow criterion violated for transition 28
lola: CHECK FINDLOW FOR TRANS ReqAppointCINFORMI
lola: INVENT VAR FOR PLACE l9
lola: CHECK EQ TRANS ReqAppointCINFORMI
lola: CHECK FINDLOW FOR TRANS GotoOSSAndProdDoc
lola: INVENT VAR FOR PLACE l35
lola: CHECK EQ TRANS GotoOSSAndProdDoc
lola: CHECK FINDLOW FOR TRANS Gate1XORSplit
lola: INVENT VAR FOR PLACE l12
lola: CHECK EQ TRANS Gate1XORSplit
lola: CHECK FINDLOW FOR TRANS ObtainFamRelCertif
lola: INVENT VAR FOR PLACE l25
lola: CHECK EQ TRANS ObtainFamRelCertif
lola: CHECK FINDLOW FOR TRANS AskCINFORMI
lola: INVENT VAR FOR PLACE l13
lola: CHECK EQ TRANS AskCINFORMI
lola: CHECK FINDLOW FOR TRANS AccessMicTerminal
lola: INVENT VAR FOR PLACE l0
lola: CHECK EQ TRANS AccessMicTerminal
lola: CHECK FINDLOW FOR TRANS DisplayLangChoice
lola: INVENT VAR FOR PLACE m1
lola: CHECK EQ TRANS DisplayLangChoice
lola: CHECK FINDLOW FOR TRANS TransmitReq
lola: INVENT VAR FOR PLACE c6
lola: CHECK EQ TRANS TransmitReq
lola: CHECK FINDLOW FOR TRANS SummonApplicant
lola: INVENT VAR FOR PLACE g1
lola: CHECK EQ TRANS SummonApplicant
lola: CHECK FINDLOW FOR TRANS SendSuitabilityCertif
lola: INVENT VAR FOR PLACE p9
lola: CHECK EQ TRANS SendSuitabilityCertif
lola: CHECK FINDLOW FOR TRANS GoToAppoint
lola: INVENT VAR FOR PLACE l11
lola: CHECK EQ TRANS GoToAppoint
lola: CHECK FINDLOW FOR TRANS ReserveAppoint
lola: INVENT VAR FOR PLACE m9
lola: CHECK EQ TRANS ReserveAppoint
lola: CHECK FINDLOW FOR TRANS ProvidePersonalnfo
lola: INVENT VAR FOR PLACE l33
lola: CHECK EQ TRANS ProvidePersonalnfo
lola: CHECK FINDLOW FOR TRANS ExplainHowToObtainMissingDoc
lola: INVENT VAR FOR PLACE m7
lola: CHECK EQ TRANS ExplainHowToObtainMissingDocs
lola: CHECK FINDLOW FOR TRANS SendLangChoice
lola: INVENT VAR FOR PLACE l2
lola: CHECK EQ TRANS SendLangChoice
lola: CHECK FINDLOW FOR TRANS ObtainRelativeFinStatement
lola: INVENT VAR FOR PLACE l24
lola: CHECK EQ TRANS ObtainRelativeFinStatement
lola: CHECK FINDLOW FOR TRANS ReserveAppCINFORMI
lola: INVENT VAR FOR PLACE l30
lola: CHECK EQ TRANS ReserveAppCINFORMI
lola: CHECK FINDLOW FOR TRANS TickDocsObtained
lola: INVENT VAR FOR PLACE l6
lola: CHECK EQ TRANS TickDocsObtained
lola: CHECK FINDLOW FOR TRANS ArchiveReq
lola: INVENT VAR FOR PLACE p7
lola: CHECK EQ TRANS ArchiveReq
lola: CHECK FINDLOW FOR TRANS CheckSanityReq
lola: INVENT VAR FOR PLACE p3
lola: CHECK EQ TRANS CheckSanityReq
lola: CHECK FINDLOW FOR TRANS Gate1ANDSplit
lola: INVENT VAR FOR PLACE p1
lola: CHECK EQ TRANS Gate1ANDSplit
lola: CHECK FINDLOW FOR TRANS SetUpAppoint
lola: INVENT VAR FOR PLACE c3
lola: CHECK EQ TRANS SetUpAppoint
lola: CHECK FINDLOW FOR TRANS ReqHousingSuitCertif
lola: INVENT VAR FOR PLACE l17
lola: CHECK EQ TRANS ReqHousingSuitCertif
lola: CHECK FINDLOW FOR TRANS DisplayNeedChoice
lola: INVENT VAR FOR PLACE m3
lola: CHECK EQ TRANS DisplayNeedChoice
lola: CHECK FINDLOW FOR TRANS Gate2XORSplit
lola: INVENT VAR FOR PLACE p6
lola: CHECK EQ TRANS Gate2XORSplit
lola: CHECK FINDLOW FOR TRANS ObtainRelHealtCondStatement
lola: INVENT VAR FOR PLACE l23
lola: CHECK EQ TRANS ObtainRelHealtCondStatement
lola: CHECK FINDLOW FOR TRANS ChoseFamilyReunion
lola: INVENT VAR FOR PLACE l4
lola: CHECK EQ TRANS ChoseFamilyReunion
lola: CHECK FINDLOW FOR TRANS ObtainMissingDocs
lola: INVENT VAR FOR PLACE l8
lola: CHECK EQ TRANS ObtainMissingDocs
lola: CHECK FINDLOW FOR TRANS ExplainProcedure
lola: INVENT VAR FOR PLACE cl0
lola: CHECK EQ TRANS ExplainProcedure
lola: CHECK FINDLOW FOR TRANS CheckHousingSuitReq
lola: INVENT VAR FOR PLACE p2
lola: CHECK EQ TRANS CheckHousingSuitReq
lola: CHECK FINDLOW FOR TRANS RegisterRelativePubHealth
lola: INVENT VAR FOR PLACE l19
lola: CHECK EQ TRANS RegisterRelativePubHealth
lola: CHECK FINDLOW FOR TRANS PrepIncomeCertif
lola: INVENT VAR FOR PLACE l22
lola: CHECK EQ TRANS PrepIncomeCertif
lola: CHECK FINDLOW FOR TRANS Gate3XORSplit
lola: INVENT VAR FOR PLACE l37
lola: CHECK EQ TRANS Gate3XORSplit
lola: CHECK FINDLOW FOR TRANS Gate2ANDSplit
lola: INVENT VAR FOR PLACE l21
lola: CHECK EQ TRANS Gate2ANDSplit
lola: CHECK FINDLOW FOR TRANS GiveAppoint
lola: INVENT VAR FOR PLACE m10
lola: CHECK EQ TRANS GiveAppoint
lola: CHECK FINDLOW FOR TRANS DisplayReqDocs
lola: INVENT VAR FOR PLACE m5
lola: CHECK EQ TRANS DisplayReqDocs
lola: CHECK FINDLOW FOR TRANS BringReqtoCINFORMI
lola: INVENT VAR FOR PLACE l32
lola: CHECK EQ TRANS BringReqtoCINFORMI
lola: findlow criterion violated for 19 clusters
lola: Time for checking findlow: 119.000000
lola: TRANS 59: Gate2ANDJoin is minimal, eq to 59
lola: TRANS 64: GotIt is minimal, eq to 64
lola: TRANS 63: HousingSuitCertifObtained is minimal,
lola: TRANS 60: ReceiveAccessReq is minimal, eq to 60
lola: TRANS 4: ReceiveNeedReq is minimal, eq to 4
lola: TRANS 5: ReceiveNeedChoice is minimal, eq to 5
lola: TRANS 6: ReceiveDocsObtained is minimal, eq to 6
lola: TRANS 0: ReceiveHousingSuitCertifReq is minimal,
lola: TRANS 58: ReceiveRegsitration is minimal, eq to 58
lola: TRANS 54: CheckRequiredDoc is minimal, eq to 54
lola: TRANS 53: Summoned is minimal, eq to 53
lola: TRANS 11: AppReqReceived is minimal, eq to 11
lola: TRANS 12: Gate1ANDJoin is minimal, eq to 12
lola: TRANS 13: Gate1XORJoin is minimal, eq to 13
lola: TRANS 50: ReceiveInstructions is minimal, eq to 50
lola: TRANS 49: ClearanceReqReceived is minimal, eq to 49
lola: TRANS 45: ReceiveLangChoice is minimal, eq to 45
lola: TRANS 43: PrepFamReuClearReq is minimal, eq to 43
lola: TRANS 18: EvaluateReq is minimal, eq to 18
lola: TRANS 42: RegisterRelative is minimal, eq to 42
lola: TRANS 41: ReceiveAppointReq is minimal, eq to 41
lola: TRANS 39: ReceiveAppoint is minimal, eq to 39
lola: TRANS 35: ReceiveLangReq is minimal, eq to 35
lola: TRANS 34: RespReceived is minimal, eq to 34
lola: TRANS 24: CommunicateResp is minimal, eq to 24
lola: TRANS 32: ReceiveQuestion is minimal, eq to 32
lola: TRANS 26: ReceiveReqDocsReq is minimal, eq to 26
lola: TRANS 29: AppointReceived is minimal, eq to 29
lola: TRANS 28: SendClearanceToRel is minimal, eq to 28
lola: TRANS 27: ReqAppointCINFORMI is minimal, eq to 27
lola: TRANS 30: GotoOSSAndProdDoc is minimal, eq to 30
lola: TRANS 31: Gate1XORSplit is minimal, eq to 31
lola: TRANS 25: ObtainFamRelCertif is minimal, eq to 25
lola: TRANS 33: AskCINFORMI is minimal, eq to 33
lola: TRANS 23: AccessMicTerminal is minimal, eq to 23
lola: TRANS 22: DisplayLangChoice is minimal, eq to 22
lola: TRANS 36: TransmitReq is minimal, eq to 36
lola: TRANS 37: SummonApplicant is minimal, eq to 37
lola: TRANS 38: SendSuitabilityCertif is minimal, eq to 38
lola: TRANS 21: GoToAppoint is minimal, eq to 21
lola: TRANS 40: ReserveAppoint is minimal, eq to 40
lola: TRANS 20: ProvidePersonalnfo is minimal, eq to 20
lola: TRANS 19: ExplainHowToObtainMissingDocs is
lola: TRANS 17: SendLangChoice is minimal, eq to 17
lola: TRANS 44: ObtainRelativeFinStatement is minimal,
lola: TRANS 16: ReserveAppCINFORMI is minimal, eq to 16
lola: TRANS 46: TickDocsObtained is minimal, eq to 46
lola: TRANS 47: ArchiveReq is minimal, eq to 47
lola: TRANS 48: CheckSanityReq is minimal, eq to 48
lola: TRANS 15: Gate1ANDSplit is minimal, eq to 15
lola: TRANS 14: SetUpAppoint is minimal, eq to 14
lola: TRANS 51: ReqHousingSuitCertif is minimal, eq to 51
lola: TRANS 52: DisplayNeedChoice is minimal, eq to 52
lola: TRANS 10: Gate2XORSplit is minimal, eq to 10
lola: TRANS 9: ObtainRelHealtCondStatement is minimal,
lola: TRANS 55: ChoseFamilyReunion is minimal, eq to 55
lola: TRANS 56: ObtainMissingDocs is minimal, eq to 56
lola: TRANS 57: ExplainProcedure is minimal, eq to 57
lola: TRANS 8: CheckHousingSuitReq is minimal, eq to 8
lola: TRANS 7: RegisterRelativePubHealth is minimal,
lola: TRANS 3: PrepIncomeCertif is minimal, eq to 3
lola: TRANS 61: Gate3XORSplit is minimal, eq to 61
lola: TRANS 62: Gate2ANDSplit is minimal, eq to 62
lola: TRANS 2: GiveAppoint is minimal, eq to 2
lola: TRANS 1: DisplayReqDocs is minimal, eq to 1
lola: TRANS 65: BringReqtoCINFORMI is minimal, eq to 65
lola: HLNOFINDLOW
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========= examination is LTLFireability ================ finition.xml rdict.xml lity.txt lity.xml lity.txt lity.xml template) text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 ; echo ; echo -n "BK_STOP " ; date -u +%s%3N arguments : [-pnfolder, /home/mcc/execution, -examination, LTLFireability, -timeout, 360, -rebuildPNML] /home/mcc/execution/model.pnml PT type :http://www.pnml.org/version-2009/grammar/symmetricnet e.axiom.locator.DefaultOMMetaFactoryLocator). for more info. rng conformance not checked model parsed with PNMLFW) : 687 ms HL places corresponding to 56 PT places. and 66 HL transitions for a total of 144109 PT places and 134480.0 transition bindings in 35 ms. in 9 ms. HLPN with 104 places and 66 transitions 198 arcs in 7 ms. properties in 2 ms. FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE Fireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE Fireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE Fireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE 66 stable transitions place count 104 transition count 66 this knowledge to assert that all AP eventually converge (and all enablings converge to false). over-approximation. transitions place count 99 transition count 66 this knowledge to assert that all AP eventually converge (and all enablings converge to false). 2 resets, run finished after 24 ms. (steps per millisecond=420 ) properties (out of 20) seen :7 including 2 resets, run finished after 73 ms. (steps per millisecond=137 ) properties (out of 13) seen :5 including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 8) seen :1 including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 7) seen :0 including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 7) seen :0 including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 7) seen :0 including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 7) seen :0 including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 7) seen :0 including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 7) seen :0 in 18 ms 4 positive place invariants in 3 ms returned sat 4 positive and 29 generalized place invariants in 7 ms returned sat possible using state equation in real domain returned unsat :0 sat :6 real:1 possible using trap constraints in real domain returned unsat :0 sat :4 real:3 possible using all constraints in real domain returned unsat :0 sat :0 real:7 4 positive place invariants in 10 ms returned sat 4 positive and 29 generalized place invariants in 16 ms returned sat possible using state equation in natural domain returned unsat :0 sat :7 possible using trap constraints in natural domain returned unsat :0 sat :7 possible using all constraints in natural domain returned unsat :0 sat :7 resets, run visited all 7 properties in 6 ms. (steps per millisecond=37 ) behavior on parameter l of sort LegalResident behavior on parameter m of sort MICSystem and join/free detected :CINFORMI :CINFORMI domain size was 11 behavior on parameter p of sort PublicAdminOffice and join/free detected :GovernmentCommission Commission :GovernmentCommission domain size was 6 and join/free detected :Response in guard (EQ $r 0)introduces in Response(2) partition with 2 elements Petri net with 128969 places and 110159 transitions 316597 arcs in 586 ms. in 7 ms. enabling conditions. structural reductions. 0 : 128732/128732 places, 110159/110159 transitions. Total rules applied 18136 place count 110596 transition count 110159 110596 /128732 variables (removed 18136) and now considering 110159/110159 (removed 0) transitions. invariants in 58819 ms unknown. Retrying; invariants in 68279 ms returned [] took 68280 ms to find 0 implicit places. unknown. Retrying; invariants and state equation in 8748 ms found 0 transitions. 1 : 110596/128732 places, 110159/110159 transitions. and 84466 ms. Remains : 110596/128732 places, 110159/110159 transitions. reductions. deterministic with 110159 transitions. 39397) after GAL structural reductions. 2 resets, run finished after 3644 ms. (steps per millisecond=2 ) properties (out of 20) seen :10 including 2 resets, run finished after 491 ms. (steps per millisecond=20 ) properties (out of 10) seen :0 including 2 resets, run finished after 109 ms. (steps per millisecond=91 ) properties (out of 10) seen :0 including 2 resets, run finished after 111 ms. (steps per millisecond=90 ) properties (out of 10) seen :0 including 2 resets, run finished after 1340 ms. (steps per millisecond=7 ) properties (out of 10) seen :0 including 2 resets, run finished after 179 ms. (steps per millisecond=55 ) properties (out of 10) seen :0 including 2 resets, run finished after 180 ms. (steps per millisecond=55 ) properties (out of 10) seen :0 including 2 resets, run finished after 175 ms. (steps per millisecond=57 ) properties (out of 10) seen :0 including 2 resets, run finished after 177 ms. (steps per millisecond=56 ) properties (out of 10) seen :0 including 2 resets, run finished after 3369 ms. (steps per millisecond=2 ) properties (out of 10) seen :0 including 2 resets, run finished after 113 ms. (steps per millisecond=88 ) properties (out of 10) seen :0 when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close... ult(SMTUtils.java:251) ariants(DeadlockTester.java:2347) sible(DeadlockTester.java:618) chableWithSMTIncremental(DeadlockTester.java:339) chableWithSMT(DeadlockTester.java:223) pplyReductions(ReachabilitySolver.java:95) R.checkAtomicPropositionsLogic(AtomicReducerSR.java:105) R.strongReductions(AtomicReducerSR.java:44) r.preSolveForLogic(LTLPropertySolver.java:176) r.runStructuralLTLCheck(LTLPropertySolver.java:71) cation.java:762) on.java:178) lication.java:45) lipseAppHandle.java:203) cher.runApplication(EclipseAppLauncher.java:136) cher.start(EclipseAppLauncher.java:104) pseStarter.java:402) pseStarter.java:255) invoke0(Native Method) invoke(NativeMethodAccessorImpl.java:77) mpl.invoke(DelegatingMethodAccessorImpl.java:43) 8) ava:659) ) error :SMT solver raised an error when submitting script.... while checking expressions. possible using all constraints in real domain returned unsat :0 sat :0 structural reductions. iteration 0 : 110596/110596 places, 110159/110159 transitions. of which 110183 are kept as prefixes of interest. Removing 413 places using SCC suffix rule.173 ms count delta: 55275 Total rules applied 64321 place count 101540 transition count 54270 condition.Transition count delta: 4623 Total rules applied 124219 place count 46265 transition count 49647 Total rules applied 128842 place count 41642 transition count 49647 + Divergent Free condition.. Total rules applied 128842 place count 41642 transition count 42009 Total rules applied 146932 place count 31190 transition count 42009 count delta: 201 Total rules applied 147133 place count 31190 transition count 41808 Total rules applied 147334 place count 30989 transition count 41808 condition.Transition count delta: 4824 Total rules applied 156982 place count 26165 transition count 36984 Total rules applied 159193 place count 26165 transition count 34773 Total rules applied 161404 place count 23954 transition count 34773 Total rules applied 166027 place count 23954 transition count 30150 Total rules applied 170851 place count 19130 transition count 30150 172881 place count 17100 transition count 24120 Total rules applied 174911 place count 17100 transition count 24120 17100 /110596 variables (removed 93496) and now considering 24120/110159 (removed 86039) transitions. , in 1 iterations and 39159 ms. Remains : 17100/110596 places, 24120/110159 transitions. resets, run visited all 10 properties in 451 ms. (steps per millisecond=4 ) FALSE TECHNIQUES REACHABILITY_KNOWLEDGE Fireability-10 FALSE TECHNIQUES REACHABILITY_KNOWLEDGE 110159 stable transitions place count 110596 transition count 110159 this knowledge to assert that all AP eventually converge (and all enablings converge to false). /fr.lip6.ltl.spot.binaries_1.0.0.202303021504/bin/ltl2tgba-linux64' '--check=stutter' '--hoaf=tv' '-f' '!(X(X(X(F((G(p1)||p0))))))' structural reductions. 0 : 110596/110596 places, 110159/110159 transitions. Total rules applied 8643 place count 101953 transition count 110159 /110596 variables (removed 8643) and now considering 110159/110159 (removed 0) transitions. invariants in 21383 ms unknown. Retrying; invariants in 30171 ms returned [] took 30172 ms to find 0 implicit places. unknown. Retrying; invariants and state equation in 8491 ms found 0 transitions. 1 : 101953/110596 places, 110159/110159 transitions. and 40731 ms. Remains : 101953/110596 places, 110159/110159 transitions. :[(AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))] -COL-L00200M0020C010P010G005-LTLFireability-00 automaton TGBA Formula[mat=[[{ cond=(AND p1 (NOT p0)), acceptance={} source=0 dest: 0}, { cond=(AND (NOT p1) (NOT p0)), acceptance={0} source=0 dest: 0}], [{ cond=true, acceptance={} source=1 dest: 0}], [{ cond=true, acceptance={} source=2 dest: 1}], [{ cond=true, acceptance={} source=3 dest: 2}]], initial=3, aps=[p1:(OR (GEQ s70747 1) (GEQ s71088 1) (GEQ s71787 1) (GEQ s70048 1) (GEQ s73168 1) (GEQ s69707 1) (GEQ s72128 1) (GEQ s72827 1) (GEQ s70389 1) (GEQ s71966 ...], nbAcceptance=1, properties=[trans-labels, explicit-labels, trans-acc, deterministic, no-univ-branch, unambiguous, semi-deterministic, stutter-sensitive], stateDesc=[null, null, null, null][false, false, false, false]] 9 reset in 10002 ms. 9 reset in 10001 ms. stable transitions place count 101953 transition count 110159 this knowledge to assert that all AP eventually converge (and all enablings converge to false). this knowledge to assert that all AP eventually converge : F ( (Ga|G!a) & (Gb|G!b)...) (F (OR (G p1) (G (NOT p1)))), (F (OR (G p0) (G (NOT p0))))] Reduced automaton from 4 states, 5 edges and 2 AP (stutter sensitive) to 4 states, 5 edges and 2 AP (stutter sensitive). :[(AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))] resets, run visited all 2 properties in 768 ms. (steps per millisecond=2 ) (F (OR (G p1) (G (NOT p1)))), (F (OR (G p0) (G (NOT p0))))] (F (NOT (AND (NOT p1) (NOT p0))))] Reduced automaton from 4 states, 5 edges and 2 AP (stutter sensitive) to 4 states, 5 edges and 2 AP (stutter sensitive). :[(AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))] :[(AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0)), (AND (NOT p1) (NOT p0))] /lola/bin/ FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT //itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar stools/its-tools -pnfolder /home/mcc/execution -examination LTLFireability -timeout 360 -rebuildPNML ity.xml on-COL-L00200M0020C010P010G005-LTLFireability-10 n-COL-L00200M0020C010P010G005-LTLFireability-10 on-COL-L00200M0020C010P010G005-LTLFireability-12 on-COL-L00200M0020C010P010G005-LTLFireability-11 on-COL-L00200M0020C010P010G005-LTLFireability-11 on-COL-L00200M0020C010P010G005-LTLFireability-11 n-COL-L00200M0020C010P010G005-LTLFireability-11 -L00200M0020C010P010G005-LTLFireability-11 (obsolete) -L00200M0020C010P010G005-LTLFireability-11 (obsolete) on-COL-L00200M0020C010P010G005-LTLFireability-10 on-COL-L00200M0020C010P010G005-LTLFireability-10 on-COL-L00200M0020C010P010G005-LTLFireability-10 n-COL-L00200M0020C010P010G005-LTLFireability-10 -L00200M0020C010P010G005-LTLFireability-10 (obsolete) -L00200M0020C010P010G005-LTLFireability-10 (obsolete) n-COL-L00200M0020C010P010G005-LTLFireability-10 n-COL-L00200M0020C010P010G005-LTLFireability-12 n-COL-L00200M0020C010P010G005-LTLFireability-11 ility-71.sara. ility-65.sara. n-COL-L00200M0020C010P010G005-LTLFireability-10 n-COL-L00200M0020C010P010G005-LTLFireability-11 VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 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STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 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false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 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ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 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0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS s eq to 63 eq to 0 minimal, eq to 19 eq to 44 eq to 9 eq to 7 VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 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0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 STATUS VALUE PRODUCED BY CONJ false skeleton: preprocessing IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 1 AG 0 0 0 0 3 0 0 1 LTL 0 0 0 0 1 0 0 0

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00200M0020C010P010G005"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FamilyReunion-COL-L00200M0020C010P010G005, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852900332"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00200M0020C010P010G005.tgz
mv FamilyReunion-COL-L00200M0020C010P010G005 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;