Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852700202.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FMS-PT-00010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852700202
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 444K
-rw-r--r-- 1 mcc users 6.3K Feb 25 20:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K Feb 25 20:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 20:18 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 25 20:18 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 20:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Feb 25 20:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 25 20:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Feb 25 20:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 16:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 17K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-00010-CTLFireability-00
FORMULA_NAME FMS-PT-00010-CTLFireability-01
FORMULA_NAME FMS-PT-00010-CTLFireability-02
FORMULA_NAME FMS-PT-00010-CTLFireability-03
FORMULA_NAME FMS-PT-00010-CTLFireability-04
FORMULA_NAME FMS-PT-00010-CTLFireability-05
FORMULA_NAME FMS-PT-00010-CTLFireability-06
FORMULA_NAME FMS-PT-00010-CTLFireability-07
FORMULA_NAME FMS-PT-00010-CTLFireability-08
FORMULA_NAME FMS-PT-00010-CTLFireability-09
FORMULA_NAME FMS-PT-00010-CTLFireability-10
FORMULA_NAME FMS-PT-00010-CTLFireability-11
FORMULA_NAME FMS-PT-00010-CTLFireability-12
FORMULA_NAME FMS-PT-00010-CTLFireability-13
FORMULA_NAME FMS-PT-00010-CTLFireability-14
FORMULA_NAME FMS-PT-00010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678446462757

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FMS-PT-00010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 11:07:44] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 11:07:44] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 11:07:44] [INFO ] Load time of PNML (sax parser for PT used): 20 ms
[2023-03-10 11:07:44] [INFO ] Transformed 22 places.
[2023-03-10 11:07:44] [INFO ] Transformed 20 transitions.
[2023-03-10 11:07:44] [INFO ] Parsed PT model containing 22 places and 20 transitions and 50 arcs in 74 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Initial state reduction rules removed 1 formulas.
FORMULA FMS-PT-00010-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 22 out of 22 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 7 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
// Phase 1: matrix 20 rows 22 cols
[2023-03-10 11:07:44] [INFO ] Computed 6 place invariants in 9 ms
[2023-03-10 11:07:44] [INFO ] Implicit Places using invariants in 125 ms returned []
[2023-03-10 11:07:44] [INFO ] Invariant cache hit.
[2023-03-10 11:07:44] [INFO ] Implicit Places using invariants and state equation in 40 ms returned []
Implicit Place search using SMT with State Equation took 185 ms to find 0 implicit places.
[2023-03-10 11:07:44] [INFO ] Invariant cache hit.
[2023-03-10 11:07:44] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 226 ms. Remains : 22/22 places, 20/20 transitions.
Support contains 22 out of 22 places after structural reductions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 14 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 4 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Finished random walk after 439 steps, including 0 resets, run visited all 32 properties in 33 ms. (steps per millisecond=13 )
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 3 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 3 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 17
Reduce places removed 5 places and 0 transitions.
Graph (trivial) has 10 edges and 17 vertex of which 6 / 17 are part of one of the 2 SCC in 1 ms
Free SCC test removed 4 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 8 rules applied. Total rules applied 11 place count 13 transition count 15
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 9 rules applied. Total rules applied 20 place count 10 transition count 9
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 22 place count 8 transition count 9
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 2 Pre rules applied. Total rules applied 22 place count 8 transition count 7
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 4 with 5 rules applied. Total rules applied 27 place count 5 transition count 7
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 4 with 1 rules applied. Total rules applied 28 place count 5 transition count 6
Applied a total of 28 rules in 8 ms. Remains 5 /22 variables (removed 17) and now considering 6/20 (removed 14) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 5/22 places, 6/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 2 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 17
Reduce places removed 4 places and 0 transitions.
Graph (trivial) has 9 edges and 18 vertex of which 6 / 18 are part of one of the 2 SCC in 0 ms
Free SCC test removed 4 places
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 6 rules applied. Total rules applied 9 place count 14 transition count 16
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 15 place count 12 transition count 12
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 3 Pre rules applied. Total rules applied 15 place count 12 transition count 9
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 7 rules applied. Total rules applied 22 place count 8 transition count 9
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 23 place count 8 transition count 8
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 23 place count 8 transition count 7
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 25 place count 7 transition count 7
Applied a total of 25 rules in 4 ms. Remains 7 /22 variables (removed 15) and now considering 7/20 (removed 13) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 7/22 places, 7/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 22 transition count 19
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 21 transition count 19
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 2 place count 21 transition count 17
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 5 rules applied. Total rules applied 7 place count 18 transition count 17
Applied a total of 7 rules in 2 ms. Remains 18 /22 variables (removed 4) and now considering 17/20 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 18/22 places, 17/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 17 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 22 transition count 18
Reduce places removed 3 places and 0 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 5 rules applied. Total rules applied 7 place count 19 transition count 16
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 9 place count 17 transition count 16
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 9 place count 17 transition count 12
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 9 rules applied. Total rules applied 18 place count 12 transition count 12
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 3 rules applied. Total rules applied 21 place count 10 transition count 11
Applied a total of 21 rules in 2 ms. Remains 10 /22 variables (removed 12) and now considering 11/20 (removed 9) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 10/22 places, 11/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 22 transition count 19
Reduce places removed 2 places and 0 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 3 rules applied. Total rules applied 4 place count 20 transition count 18
Reduce places removed 1 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 2 with 4 rules applied. Total rules applied 8 place count 19 transition count 15
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 11 place count 16 transition count 15
Applied a total of 11 rules in 1 ms. Remains 16 /22 variables (removed 6) and now considering 15/20 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 16/22 places, 15/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:07:44] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 22 transition count 15
Reduce places removed 7 places and 0 transitions.
Graph (trivial) has 11 edges and 15 vertex of which 9 / 15 are part of one of the 3 SCC in 0 ms
Free SCC test removed 6 places
Iterating post reduction 1 with 8 rules applied. Total rules applied 13 place count 9 transition count 15
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 7 rules applied. Total rules applied 20 place count 8 transition count 9
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 20 place count 8 transition count 8
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 22 place count 7 transition count 8
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 24 place count 6 transition count 7
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 3 with 2 rules applied. Total rules applied 26 place count 6 transition count 5
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 26 place count 6 transition count 3
Deduced a syphon composed of 2 places in 0 ms
Application raised an uncaught exception Index 10 out of bounds for length 4
java.lang.IndexOutOfBoundsException: Index 10 out of bounds for length 4
at java.base/jdk.internal.util.Preconditions.outOfBounds(Preconditions.java:64)
at java.base/jdk.internal.util.Preconditions.outOfBoundsCheckIndex(Preconditions.java:70)
at java.base/jdk.internal.util.Preconditions.checkIndex(Preconditions.java:266)
at java.base/java.util.Objects.checkIndex(Objects.java:359)
at java.base/java.util.ArrayList.get(ArrayList.java:427)
at fr.lip6.move.gal.structural.StructuralReduction.ensureUnique(StructuralReduction.java:916)
at fr.lip6.move.gal.structural.StructuralReduction.ruleReducePlaces(StructuralReduction.java:1056)
at fr.lip6.move.gal.structural.StructuralReduction.reduce(StructuralReduction.java:240)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:452)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:649)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
Total runtime 731 ms.
starting LoLA
BK_INPUT FMS-PT-00010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA FMS-PT-00010-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00010-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678446493378

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 52 (type EXCL) for 3 FMS-PT-00010-CTLFireability-01
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 52 (type EXCL) for FMS-PT-00010-CTLFireability-01
lola: result : true
lola: markings : 1257
lola: fired transitions : 4282
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 FMS-PT-00010-CTLFireability-14
lola: time limit : 143 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 47 (type EXCL) for FMS-PT-00010-CTLFireability-14
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 42 (type EXCL) for 39 FMS-PT-00010-CTLFireability-13
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for FMS-PT-00010-CTLFireability-13
lola: result : true
lola: markings : 189
lola: fired transitions : 205
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 FMS-PT-00010-CTLFireability-11
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for FMS-PT-00010-CTLFireability-11
lola: result : true
lola: markings : 10
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 FMS-PT-00010-CTLFireability-10
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 31 (type EXCL) for FMS-PT-00010-CTLFireability-10
lola: result : false
lola: markings : 55
lola: fired transitions : 54
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 28 (type EXCL) for 27 FMS-PT-00010-CTLFireability-09
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 28 (type EXCL) for FMS-PT-00010-CTLFireability-09
lola: result : true
lola: markings : 3087
lola: fired transitions : 6511
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 FMS-PT-00010-CTLFireability-08
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for FMS-PT-00010-CTLFireability-08
lola: result : false
lola: markings : 243
lola: fired transitions : 386
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 FMS-PT-00010-CTLFireability-07
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for FMS-PT-00010-CTLFireability-07
lola: result : true
lola: markings : 9902
lola: fired transitions : 20060
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 FMS-PT-00010-CTLFireability-03
lola: time limit : 399 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00010-CTLFireability-01: SP ACTL true LTL model checker
FMS-PT-00010-CTLFireability-07: CTL true CTL model checker
FMS-PT-00010-CTLFireability-08: CTL false CTL model checker
FMS-PT-00010-CTLFireability-09: CTL true CTL model checker
FMS-PT-00010-CTLFireability-10: CTL false CTL model checker
FMS-PT-00010-CTLFireability-11: CTL true CTL model checker
FMS-PT-00010-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FMS-PT-00010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
FMS-PT-00010-CTLFireability-15: AGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/399 9/32 FMS-PT-00010-CTLFireability-03 2100733 m, 420146 m/sec, 5995970 t fired, .

Time elapsed: 6 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00010-CTLFireability-01: SP ACTL true LTL model checker
FMS-PT-00010-CTLFireability-07: CTL true CTL model checker
FMS-PT-00010-CTLFireability-08: CTL false CTL model checker
FMS-PT-00010-CTLFireability-09: CTL true CTL model checker
FMS-PT-00010-CTLFireability-10: CTL false CTL model checker
FMS-PT-00010-CTLFireability-11: CTL true CTL model checker
FMS-PT-00010-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FMS-PT-00010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
FMS-PT-00010-CTLFireability-15: AGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/399 16/32 FMS-PT-00010-CTLFireability-03 3707911 m, 321435 m/sec, 11176175 t fired, .

Time elapsed: 11 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00010-CTLFireability-01: SP ACTL true LTL model checker
FMS-PT-00010-CTLFireability-07: CTL true CTL model checker
FMS-PT-00010-CTLFireability-08: CTL false CTL model checker
FMS-PT-00010-CTLFireability-09: CTL true CTL model checker
FMS-PT-00010-CTLFireability-10: CTL false CTL model checker
FMS-PT-00010-CTLFireability-11: CTL true CTL model checker
FMS-PT-00010-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FMS-PT-00010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
FMS-PT-00010-CTLFireability-15: AGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/399 22/32 FMS-PT-00010-CTLFireability-03 5131329 m, 284683 m/sec, 15985876 t fired, .

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# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00010-CTLFireability-01: SP ACTL true LTL model checker
FMS-PT-00010-CTLFireability-07: CTL true CTL model checker
FMS-PT-00010-CTLFireability-08: CTL false CTL model checker
FMS-PT-00010-CTLFireability-09: CTL true CTL model checker
FMS-PT-00010-CTLFireability-10: CTL false CTL model checker
FMS-PT-00010-CTLFireability-11: CTL true CTL model checker
FMS-PT-00010-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FMS-PT-00010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
FMS-PT-00010-CTLFireability-15: AGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/399 28/32 FMS-PT-00010-CTLFireability-03 6507113 m, 275156 m/sec, 20773546 t fired, .

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lola: CANCELED task # 10 (type EXCL) for FMS-PT-00010-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00010-CTLFireability-01: SP ACTL true LTL model checker
FMS-PT-00010-CTLFireability-07: CTL true CTL model checker
FMS-PT-00010-CTLFireability-08: CTL false CTL model checker
FMS-PT-00010-CTLFireability-09: CTL true CTL model checker
FMS-PT-00010-CTLFireability-10: CTL false CTL model checker
FMS-PT-00010-CTLFireability-11: CTL true CTL model checker
FMS-PT-00010-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-00010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-00010-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
FMS-PT-00010-CTLFireability-15: AGEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 7 (type EXCL) for 6 FMS-PT-00010-CTLFireability-02
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for FMS-PT-00010-CTLFireability-02
lola: result : true
lola: markings : 103
lola: fired transitions : 105
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 FMS-PT-00010-CTLFireability-00
lola: time limit : 510 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for FMS-PT-00010-CTLFireability-00
lola: result : true
lola: markings : 525222
lola: fired transitions : 1688460
lola: time used : 1.000000
lola: memory pages used : 3
lola: LAUNCH task # 53 (type EXCL) for 39 FMS-PT-00010-CTLFireability-13
lola: time limit : 595 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for FMS-PT-00010-CTLFireability-13
lola: result : true
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 FMS-PT-00010-CTLFireability-06
lola: time limit : 714 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for FMS-PT-00010-CTLFireability-06
lola: result : true
lola: markings : 1331
lola: fired transitions : 6836
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 49 FMS-PT-00010-CTLFireability-15
lola: time limit : 893 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for FMS-PT-00010-CTLFireability-15
lola: result : true
lola: markings : 3
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 FMS-PT-00010-CTLFireability-12
lola: time limit : 1191 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for FMS-PT-00010-CTLFireability-12
lola: result : true
lola: markings : 282
lola: fired transitions : 538
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 FMS-PT-00010-CTLFireability-04
lola: time limit : 1786 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for FMS-PT-00010-CTLFireability-04
lola: result : false
lola: markings : 1869
lola: fired transitions : 8524
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 FMS-PT-00010-CTLFireability-05
lola: time limit : 3573 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for FMS-PT-00010-CTLFireability-05
lola: result : false
lola: markings : 81
lola: fired transitions : 148
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00010-CTLFireability-00: CTL true CTL model checker
FMS-PT-00010-CTLFireability-01: SP ACTL true LTL model checker
FMS-PT-00010-CTLFireability-02: CTL true CTL model checker
FMS-PT-00010-CTLFireability-03: CTL unknown AGGR
FMS-PT-00010-CTLFireability-04: CTL false CTL model checker
FMS-PT-00010-CTLFireability-05: CTL false CTL model checker
FMS-PT-00010-CTLFireability-06: AGEF true tscc_search
FMS-PT-00010-CTLFireability-07: CTL true CTL model checker
FMS-PT-00010-CTLFireability-08: CTL false CTL model checker
FMS-PT-00010-CTLFireability-09: CTL true CTL model checker
FMS-PT-00010-CTLFireability-10: CTL false CTL model checker
FMS-PT-00010-CTLFireability-11: CTL true CTL model checker
FMS-PT-00010-CTLFireability-12: CTL true CTL model checker
FMS-PT-00010-CTLFireability-13: CONJ false state space / EG
FMS-PT-00010-CTLFireability-14: CTL true CTL model checker
FMS-PT-00010-CTLFireability-15: AGEF true tscc_search


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-00010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FMS-PT-00010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852700202"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-00010.tgz
mv FMS-PT-00010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;