About the Execution of LoLa+red for FMS-PT-00005
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 534.716 | 26955.00 | 29847.00 | 413.40 | FTFTTFTTTFTFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852700194.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FMS-PT-00005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852700194
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 6.7K Feb 25 19:48 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K Feb 25 19:48 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 19:47 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 25 19:47 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 19:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Feb 25 19:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 19:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 111K Feb 25 19:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 16:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 17K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-00005-CTLFireability-00
FORMULA_NAME FMS-PT-00005-CTLFireability-01
FORMULA_NAME FMS-PT-00005-CTLFireability-02
FORMULA_NAME FMS-PT-00005-CTLFireability-03
FORMULA_NAME FMS-PT-00005-CTLFireability-04
FORMULA_NAME FMS-PT-00005-CTLFireability-05
FORMULA_NAME FMS-PT-00005-CTLFireability-06
FORMULA_NAME FMS-PT-00005-CTLFireability-07
FORMULA_NAME FMS-PT-00005-CTLFireability-08
FORMULA_NAME FMS-PT-00005-CTLFireability-09
FORMULA_NAME FMS-PT-00005-CTLFireability-10
FORMULA_NAME FMS-PT-00005-CTLFireability-11
FORMULA_NAME FMS-PT-00005-CTLFireability-12
FORMULA_NAME FMS-PT-00005-CTLFireability-13
FORMULA_NAME FMS-PT-00005-CTLFireability-14
FORMULA_NAME FMS-PT-00005-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678446387120
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FMS-PT-00005
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 11:06:28] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 11:06:28] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 11:06:28] [INFO ] Load time of PNML (sax parser for PT used): 22 ms
[2023-03-10 11:06:28] [INFO ] Transformed 22 places.
[2023-03-10 11:06:28] [INFO ] Transformed 20 transitions.
[2023-03-10 11:06:28] [INFO ] Parsed PT model containing 22 places and 20 transitions and 50 arcs in 83 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Initial state reduction rules removed 2 formulas.
FORMULA FMS-PT-00005-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FMS-PT-00005-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 22 out of 22 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 8 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
// Phase 1: matrix 20 rows 22 cols
[2023-03-10 11:06:28] [INFO ] Computed 6 place invariants in 7 ms
[2023-03-10 11:06:28] [INFO ] Implicit Places using invariants in 128 ms returned []
[2023-03-10 11:06:28] [INFO ] Invariant cache hit.
[2023-03-10 11:06:28] [INFO ] Implicit Places using invariants and state equation in 45 ms returned []
Implicit Place search using SMT with State Equation took 198 ms to find 0 implicit places.
[2023-03-10 11:06:28] [INFO ] Invariant cache hit.
[2023-03-10 11:06:28] [INFO ] Dead Transitions using invariants and state equation in 41 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 249 ms. Remains : 22/22 places, 20/20 transitions.
Support contains 22 out of 22 places after structural reductions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 14 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 5 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 81 ms. (steps per millisecond=123 ) properties (out of 40) seen :39
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-10 11:06:29] [INFO ] Invariant cache hit.
[2023-03-10 11:06:29] [INFO ] [Real]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-10 11:06:29] [INFO ] After 37ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 14 simplifications.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 3 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 3 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 17
Reduce places removed 5 places and 0 transitions.
Graph (trivial) has 7 edges and 17 vertex of which 3 / 17 are part of one of the 1 SCC in 2 ms
Free SCC test removed 2 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 8 rules applied. Total rules applied 11 place count 15 transition count 15
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 6 rules applied. Total rules applied 17 place count 13 transition count 11
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 19 place count 11 transition count 11
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 1 Pre rules applied. Total rules applied 19 place count 11 transition count 10
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 21 place count 10 transition count 10
Applied a total of 21 rules in 10 ms. Remains 10 /22 variables (removed 12) and now considering 10/20 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 10/22 places, 10/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 22 transition count 15
Reduce places removed 7 places and 0 transitions.
Graph (trivial) has 11 edges and 15 vertex of which 9 / 15 are part of one of the 3 SCC in 0 ms
Free SCC test removed 6 places
Iterating post reduction 1 with 8 rules applied. Total rules applied 13 place count 9 transition count 15
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 7 rules applied. Total rules applied 20 place count 8 transition count 9
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 20 place count 8 transition count 7
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 5 rules applied. Total rules applied 25 place count 5 transition count 7
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 3 with 2 rules applied. Total rules applied 27 place count 5 transition count 5
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 27 place count 5 transition count 3
Deduced a syphon composed of 2 places in 0 ms
Ensure Unique test removed 1 places
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 5 rules applied. Total rules applied 32 place count 2 transition count 3
Applied a total of 32 rules in 9 ms. Remains 2 /22 variables (removed 20) and now considering 3/20 (removed 17) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 2/22 places, 3/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 3 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=0 )
FORMULA FMS-PT-00005-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 17
Reduce places removed 5 places and 0 transitions.
Graph (trivial) has 8 edges and 17 vertex of which 3 / 17 are part of one of the 1 SCC in 0 ms
Free SCC test removed 2 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 7 rules applied. Total rules applied 10 place count 15 transition count 16
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 4 rules applied. Total rules applied 14 place count 14 transition count 13
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 15 place count 13 transition count 13
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 1 Pre rules applied. Total rules applied 15 place count 13 transition count 12
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 17 place count 12 transition count 12
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 4 with 3 rules applied. Total rules applied 20 place count 10 transition count 11
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 4 with 1 rules applied. Total rules applied 21 place count 10 transition count 11
Applied a total of 21 rules in 5 ms. Remains 10 /22 variables (removed 12) and now considering 11/20 (removed 9) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 10/22 places, 11/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 17
Reduce places removed 4 places and 0 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 6 rules applied. Total rules applied 9 place count 18 transition count 15
Reduce places removed 2 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 3 rules applied. Total rules applied 12 place count 16 transition count 14
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 13 place count 15 transition count 14
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 3 Pre rules applied. Total rules applied 13 place count 15 transition count 11
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 4 with 7 rules applied. Total rules applied 20 place count 11 transition count 11
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 4 with 3 rules applied. Total rules applied 23 place count 9 transition count 10
Applied a total of 23 rules in 4 ms. Remains 9 /22 variables (removed 13) and now considering 10/20 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 9/22 places, 10/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Input system was already deterministic with 20 transitions.
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:29] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:29] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 1 ms.
[2023-03-10 11:06:29] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 22 places, 20 transitions and 50 arcs took 0 ms.
Total runtime 1088 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FMS-PT-00005
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability
FORMULA FMS-PT-00005-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678446414075
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 21 (type EXCL) for 18 FMS-PT-00005-CTLFireability-07
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 21 (type EXCL) for FMS-PT-00005-CTLFireability-07
lola: result : true
lola: markings : 105
lola: fired transitions : 139
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 35 (type EXCL) for 18 FMS-PT-00005-CTLFireability-07
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for FMS-PT-00005-CTLFireability-07
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 FMS-PT-00005-CTLFireability-03
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for FMS-PT-00005-CTLFireability-03
lola: result : true
lola: markings : 384
lola: fired transitions : 498
lola: time used : 0.000000
lola: memory pages used : 1
lola: planning for (null) stopped (result already fixed).
lola: LAUNCH task # 29 (type EXCL) for 18 FMS-PT-00005-CTLFireability-07
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: FINISHED task # 29 (type EXCL) for FMS-PT-00005-CTLFireability-07
lola: result : true
lola: markings : 20874
lola: fired transitions : 315909
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 49 FMS-PT-00005-CTLFireability-14
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for FMS-PT-00005-CTLFireability-14
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 56 FMS-PT-00005-CTLFireability-15
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for FMS-PT-00005-CTLFireability-15
lola: result : false
lola: markings : 77
lola: fired transitions : 89
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 49 FMS-PT-00005-CTLFireability-14
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for FMS-PT-00005-CTLFireability-14
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 FMS-PT-00005-CTLFireability-13
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for FMS-PT-00005-CTLFireability-13
lola: result : false
lola: markings : 17
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lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 FMS-PT-00005-CTLFireability-10
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for FMS-PT-00005-CTLFireability-10
lola: result : true
lola: markings : 22
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 FMS-PT-00005-CTLFireability-06
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for FMS-PT-00005-CTLFireability-06
lola: result : true
lola: markings : 1862
lola: fired transitions : 3674
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 FMS-PT-00005-CTLFireability-05
lola: time limit : 514 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLFireability-03: CTL true CTL model checker
FMS-PT-00005-CTLFireability-06: CTL true CTL model checker
FMS-PT-00005-CTLFireability-10: CTL true CTL model checker
FMS-PT-00005-CTLFireability-13: CTL false CTL model checker
FMS-PT-00005-CTLFireability-14: CONJ false CTL model checker
FMS-PT-00005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/514 6/32 FMS-PT-00005-CTLFireability-05 1297000 m, 259400 m/sec, 6248399 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLFireability-03: CTL true CTL model checker
FMS-PT-00005-CTLFireability-06: CTL true CTL model checker
FMS-PT-00005-CTLFireability-10: CTL true CTL model checker
FMS-PT-00005-CTLFireability-13: CTL false CTL model checker
FMS-PT-00005-CTLFireability-14: CONJ false CTL model checker
FMS-PT-00005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/514 10/32 FMS-PT-00005-CTLFireability-05 2340539 m, 208707 m/sec, 12109953 t fired, .
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FMS-PT-00005-CTLFireability-03: CTL true CTL model checker
FMS-PT-00005-CTLFireability-06: CTL true CTL model checker
FMS-PT-00005-CTLFireability-10: CTL true CTL model checker
FMS-PT-00005-CTLFireability-13: CTL false CTL model checker
FMS-PT-00005-CTLFireability-14: CONJ false CTL model checker
FMS-PT-00005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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13 CTL EXCL 15/514 12/32 FMS-PT-00005-CTLFireability-05 2837609 m, 99414 m/sec, 17886406 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLFireability-03: CTL true CTL model checker
FMS-PT-00005-CTLFireability-06: CTL true CTL model checker
FMS-PT-00005-CTLFireability-10: CTL true CTL model checker
FMS-PT-00005-CTLFireability-13: CTL false CTL model checker
FMS-PT-00005-CTLFireability-14: CONJ false CTL model checker
FMS-PT-00005-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/514 12/32 FMS-PT-00005-CTLFireability-05 2886010 m, 9680 m/sec, 23220253 t fired, .
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lola: FINISHED task # 13 (type EXCL) for FMS-PT-00005-CTLFireability-05
lola: result : false
lola: markings : 2895018
lola: fired transitions : 27036281
lola: time used : 23.000000
lola: memory pages used : 12
lola: LAUNCH task # 7 (type EXCL) for 6 FMS-PT-00005-CTLFireability-02
lola: time limit : 596 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for FMS-PT-00005-CTLFireability-02
lola: result : false
lola: markings : 11461
lola: fired transitions : 126039
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 FMS-PT-00005-CTLFireability-00
lola: time limit : 715 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for FMS-PT-00005-CTLFireability-00
lola: result : false
lola: markings : 217
lola: fired transitions : 489
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 18 FMS-PT-00005-CTLFireability-07
lola: time limit : 894 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for FMS-PT-00005-CTLFireability-07
lola: result : true
lola: markings : 5
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 FMS-PT-00005-CTLFireability-12
lola: time limit : 1192 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for FMS-PT-00005-CTLFireability-12
lola: result : true
lola: markings : 4732
lola: fired transitions : 26260
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 FMS-PT-00005-CTLFireability-09
lola: time limit : 1788 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for FMS-PT-00005-CTLFireability-09
lola: result : false
lola: markings : 1974
lola: fired transitions : 15960
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 FMS-PT-00005-CTLFireability-01
lola: time limit : 3576 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for FMS-PT-00005-CTLFireability-01
lola: result : true
lola: markings : 1062
lola: fired transitions : 2835
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLFireability-00: CTL false CTL model checker
FMS-PT-00005-CTLFireability-01: CTL true CTL model checker
FMS-PT-00005-CTLFireability-02: CTL false CTL model checker
FMS-PT-00005-CTLFireability-03: CTL true CTL model checker
FMS-PT-00005-CTLFireability-05: CTL false CTL model checker
FMS-PT-00005-CTLFireability-06: CTL true CTL model checker
FMS-PT-00005-CTLFireability-07: CONJ true CONJ
FMS-PT-00005-CTLFireability-09: CTL false CTL model checker
FMS-PT-00005-CTLFireability-10: CTL true CTL model checker
FMS-PT-00005-CTLFireability-12: AGEF true tscc_search
FMS-PT-00005-CTLFireability-13: CTL false CTL model checker
FMS-PT-00005-CTLFireability-14: CONJ false CTL model checker
FMS-PT-00005-CTLFireability-15: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-00005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FMS-PT-00005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852700194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-00005.tgz
mv FMS-PT-00005 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;