About the Execution of LoLa+red for FMS-PT-00005
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1420.132 | 87146.00 | 92041.00 | 641.10 | FTTTTTFFFTTTFTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852700193.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FMS-PT-00005, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852700193
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 6.7K Feb 25 19:48 CTLCardinality.txt
-rw-r--r-- 1 mcc users 71K Feb 25 19:48 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 19:47 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 25 19:47 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 19:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Feb 25 19:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 19:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 111K Feb 25 19:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 16:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 17K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-00005-CTLCardinality-00
FORMULA_NAME FMS-PT-00005-CTLCardinality-01
FORMULA_NAME FMS-PT-00005-CTLCardinality-02
FORMULA_NAME FMS-PT-00005-CTLCardinality-03
FORMULA_NAME FMS-PT-00005-CTLCardinality-04
FORMULA_NAME FMS-PT-00005-CTLCardinality-05
FORMULA_NAME FMS-PT-00005-CTLCardinality-06
FORMULA_NAME FMS-PT-00005-CTLCardinality-07
FORMULA_NAME FMS-PT-00005-CTLCardinality-08
FORMULA_NAME FMS-PT-00005-CTLCardinality-09
FORMULA_NAME FMS-PT-00005-CTLCardinality-10
FORMULA_NAME FMS-PT-00005-CTLCardinality-11
FORMULA_NAME FMS-PT-00005-CTLCardinality-12
FORMULA_NAME FMS-PT-00005-CTLCardinality-13
FORMULA_NAME FMS-PT-00005-CTLCardinality-14
FORMULA_NAME FMS-PT-00005-CTLCardinality-15
=== Now, execution of the tool begins
BK_START 1678446377149
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FMS-PT-00005
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 11:06:18] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-10 11:06:18] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 11:06:18] [INFO ] Load time of PNML (sax parser for PT used): 20 ms
[2023-03-10 11:06:18] [INFO ] Transformed 22 places.
[2023-03-10 11:06:18] [INFO ] Transformed 20 transitions.
[2023-03-10 11:06:18] [INFO ] Parsed PT model containing 22 places and 20 transitions and 50 arcs in 77 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 14 ms.
Support contains 22 out of 22 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 11 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
// Phase 1: matrix 20 rows 22 cols
[2023-03-10 11:06:19] [INFO ] Computed 6 place invariants in 8 ms
[2023-03-10 11:06:19] [INFO ] Implicit Places using invariants in 138 ms returned []
[2023-03-10 11:06:19] [INFO ] Invariant cache hit.
[2023-03-10 11:06:19] [INFO ] Implicit Places using invariants and state equation in 51 ms returned []
Implicit Place search using SMT with State Equation took 423 ms to find 0 implicit places.
[2023-03-10 11:06:19] [INFO ] Invariant cache hit.
[2023-03-10 11:06:19] [INFO ] Dead Transitions using invariants and state equation in 47 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 484 ms. Remains : 22/22 places, 20/20 transitions.
Support contains 22 out of 22 places after structural reductions.
[2023-03-10 11:06:19] [INFO ] Flatten gal took : 15 ms
[2023-03-10 11:06:19] [INFO ] Flatten gal took : 4 ms
[2023-03-10 11:06:19] [INFO ] Input system was already deterministic with 20 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 338 ms. (steps per millisecond=29 ) properties (out of 75) seen :62
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 58 ms. (steps per millisecond=172 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 13) seen :2
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 11) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 10) seen :0
Running SMT prover for 10 properties.
[2023-03-10 11:06:20] [INFO ] Invariant cache hit.
[2023-03-10 11:06:20] [INFO ] [Real]Absence check using 6 positive place invariants in 1 ms returned sat
[2023-03-10 11:06:20] [INFO ] After 69ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:8
[2023-03-10 11:06:20] [INFO ] [Nat]Absence check using 6 positive place invariants in 1 ms returned sat
[2023-03-10 11:06:20] [INFO ] After 49ms SMT Verify possible using all constraints in natural domain returned unsat :10 sat :0
Fused 10 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 10 atomic propositions for a total of 16 simplifications.
FORMULA FMS-PT-00005-CTLCardinality-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 4 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 22 transition count 15
Reduce places removed 8 places and 0 transitions.
Graph (trivial) has 12 edges and 14 vertex of which 9 / 14 are part of one of the 3 SCC in 1 ms
Free SCC test removed 6 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 11 rules applied. Total rules applied 16 place count 8 transition count 13
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 10 rules applied. Total rules applied 26 place count 5 transition count 6
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 27 place count 4 transition count 6
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 4 with 2 rules applied. Total rules applied 29 place count 4 transition count 4
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 1 Pre rules applied. Total rules applied 29 place count 4 transition count 3
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 4 with 3 rules applied. Total rules applied 32 place count 2 transition count 3
Applied a total of 32 rules in 9 ms. Remains 2 /22 variables (removed 20) and now considering 3/20 (removed 17) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 2/22 places, 3/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 3 transitions.
Finished random walk after 6 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=6 )
FORMULA FMS-PT-00005-CTLCardinality-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 22 transition count 18
Reduce places removed 3 places and 0 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 4 rules applied. Total rules applied 6 place count 19 transition count 17
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 2 rules applied. Total rules applied 8 place count 18 transition count 16
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 9 place count 17 transition count 16
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 2 Pre rules applied. Total rules applied 9 place count 17 transition count 14
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 4 with 4 rules applied. Total rules applied 13 place count 15 transition count 14
Applied a total of 13 rules in 3 ms. Remains 15 /22 variables (removed 7) and now considering 14/20 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 15/22 places, 14/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 14 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 22 transition count 16
Reduce places removed 6 places and 0 transitions.
Graph (trivial) has 8 edges and 16 vertex of which 3 / 16 are part of one of the 1 SCC in 0 ms
Free SCC test removed 2 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 8 rules applied. Total rules applied 12 place count 14 transition count 15
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 5 rules applied. Total rules applied 17 place count 13 transition count 11
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 20 place count 10 transition count 11
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 1 Pre rules applied. Total rules applied 20 place count 10 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 22 place count 9 transition count 10
Applied a total of 22 rules in 3 ms. Remains 9 /22 variables (removed 13) and now considering 10/20 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 9/22 places, 10/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 22 transition count 19
Reduce places removed 2 places and 0 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 3 rules applied. Total rules applied 4 place count 20 transition count 18
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 5 place count 19 transition count 18
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 5 place count 19 transition count 16
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 9 place count 17 transition count 16
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 3 rules applied. Total rules applied 12 place count 15 transition count 15
Applied a total of 12 rules in 4 ms. Remains 15 /22 variables (removed 7) and now considering 15/20 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 15/22 places, 15/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 22 transition count 18
Reduce places removed 3 places and 0 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 4 rules applied. Total rules applied 6 place count 19 transition count 17
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 2 rules applied. Total rules applied 8 place count 18 transition count 16
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 9 place count 17 transition count 16
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 3 Pre rules applied. Total rules applied 9 place count 17 transition count 13
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 4 with 6 rules applied. Total rules applied 15 place count 14 transition count 13
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 17 place count 13 transition count 12
Applied a total of 17 rules in 3 ms. Remains 13 /22 variables (removed 9) and now considering 12/20 (removed 8) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 13/22 places, 12/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Input system was already deterministic with 20 transitions.
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:06:20] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:06:20] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 3 ms.
[2023-03-10 11:06:20] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 22 places, 20 transitions and 50 arcs took 1 ms.
Total runtime 2103 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FMS-PT-00005
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
FORMULA FMS-PT-00005-CTLCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678446464295
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 49 (type CNST) for 48 FMS-PT-00005-CTLCardinality-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 49 (type CNST) for FMS-PT-00005-CTLCardinality-14
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 7 (type EXCL) for 6 FMS-PT-00005-CTLCardinality-04
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:664
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 3 0 0 3 0 0 0
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/225 8/32 FMS-PT-00005-CTLCardinality-04 1937505 m, 387501 m/sec, 6634272 t fired, .
Time elapsed: 5 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 3 0 0 3 0 0 0
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/225 12/32 FMS-PT-00005-CTLCardinality-04 2888531 m, 190205 m/sec, 12992703 t fired, .
Time elapsed: 10 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 3 0 0 3 0 0 0
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/225 12/32 FMS-PT-00005-CTLCardinality-04 2893826 m, 1059 m/sec, 18138587 t fired, .
Time elapsed: 15 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 3 0 0 3 0 0 0
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/225 12/32 FMS-PT-00005-CTLCardinality-04 2894910 m, 216 m/sec, 23214307 t fired, .
Time elapsed: 20 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 7 (type EXCL) for FMS-PT-00005-CTLCardinality-04
lola: result : true
lola: markings : 2895018
lola: fired transitions : 25989192
lola: time used : 22.000000
lola: memory pages used : 12
lola: LAUNCH task # 54 (type EXCL) for 12 FMS-PT-00005-CTLCardinality-06
lola: time limit : 238 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for FMS-PT-00005-CTLCardinality-06
lola: result : true
lola: markings : 863
lola: fired transitions : 1093
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 51 FMS-PT-00005-CTLCardinality-15
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for FMS-PT-00005-CTLCardinality-15
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 FMS-PT-00005-CTLCardinality-13
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for FMS-PT-00005-CTLCardinality-13
lola: result : true
lola: markings : 93
lola: fired transitions : 132
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 FMS-PT-00005-CTLCardinality-12
lola: time limit : 325 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 1 0 0 4 0 0 1
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 3/325 4/32 FMS-PT-00005-CTLCardinality-12 743210 m, 148642 m/sec, 3463585 t fired, .
Time elapsed: 25 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 1 0 0 4 0 0 1
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 8/325 7/32 FMS-PT-00005-CTLCardinality-12 1542401 m, 159838 m/sec, 9909105 t fired, .
Time elapsed: 30 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 1 0 0 4 0 0 1
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 13/325 9/32 FMS-PT-00005-CTLCardinality-12 2134593 m, 118438 m/sec, 16382353 t fired, .
Time elapsed: 35 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 1 0 0 4 0 0 1
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 18/325 11/32 FMS-PT-00005-CTLCardinality-12 2632175 m, 99516 m/sec, 22810654 t fired, .
Time elapsed: 40 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 1 0 0 4 0 0 1
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 23/325 12/32 FMS-PT-00005-CTLCardinality-12 2892618 m, 52088 m/sec, 29430873 t fired, .
Time elapsed: 45 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 1 0 0 4 0 0 1
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 28/325 12/32 FMS-PT-00005-CTLCardinality-12 2894681 m, 412 m/sec, 34603994 t fired, .
Time elapsed: 50 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 1 0 0 4 0 0 1
FMS-PT-00005-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 33/325 12/32 FMS-PT-00005-CTLCardinality-12 2895013 m, 66 m/sec, 40257237 t fired, .
Time elapsed: 55 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 43 (type EXCL) for FMS-PT-00005-CTLCardinality-12
lola: result : false
lola: markings : 2895018
lola: fired transitions : 41835985
lola: time used : 35.000000
lola: memory pages used : 12
lola: LAUNCH task # 40 (type EXCL) for 39 FMS-PT-00005-CTLCardinality-11
lola: time limit : 354 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for FMS-PT-00005-CTLCardinality-11
lola: result : true
lola: markings : 2859
lola: fired transitions : 13053
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 FMS-PT-00005-CTLCardinality-07
lola: time limit : 393 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for FMS-PT-00005-CTLCardinality-07
lola: result : false
lola: markings : 731469
lola: fired transitions : 3321384
lola: time used : 2.000000
lola: memory pages used : 3
lola: LAUNCH task # 21 (type EXCL) for 12 FMS-PT-00005-CTLCardinality-06
lola: time limit : 442 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-07: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-11: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-12: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 0 1 0 4 0 0 1
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 1/442 3/32 FMS-PT-00005-CTLCardinality-06 547857 m, 109571 m/sec, 1101815 t fired, .
Time elapsed: 60 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-07: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-11: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-12: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 0 1 0 4 0 0 1
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 6/442 8/32 FMS-PT-00005-CTLCardinality-06 1895737 m, 269576 m/sec, 4814982 t fired, .
Time elapsed: 65 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-07: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-11: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-12: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 0 1 0 4 0 0 1
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 11/442 12/32 FMS-PT-00005-CTLCardinality-06 2885644 m, 197981 m/sec, 9299138 t fired, .
Time elapsed: 70 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-07: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-11: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-12: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 0 1 0 4 0 0 1
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 16/442 12/32 FMS-PT-00005-CTLCardinality-06 2893417 m, 1554 m/sec, 14902910 t fired, .
Time elapsed: 75 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-07: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-11: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-12: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-00005-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-06: DISJ 0 0 1 0 4 0 0 1
FMS-PT-00005-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-00005-CTLCardinality-09: DISJ 0 2 0 0 2 0 0 0
FMS-PT-00005-CTLCardinality-10: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 21/442 12/32 FMS-PT-00005-CTLCardinality-06 2894904 m, 297 m/sec, 20682341 t fired, .
Time elapsed: 80 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 21 (type EXCL) for FMS-PT-00005-CTLCardinality-06
lola: result : false
lola: markings : 2895018
lola: fired transitions : 23527185
lola: time used : 24.000000
lola: memory pages used : 12
lola: LAUNCH task # 4 (type EXCL) for 3 FMS-PT-00005-CTLCardinality-03
lola: time limit : 502 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for FMS-PT-00005-CTLCardinality-03
lola: result : true
lola: markings : 224
lola: fired transitions : 670
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 FMS-PT-00005-CTLCardinality-01
lola: time limit : 586 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for FMS-PT-00005-CTLCardinality-01
lola: result : true
lola: markings : 2145
lola: fired transitions : 3245
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 36 FMS-PT-00005-CTLCardinality-10
lola: time limit : 703 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for FMS-PT-00005-CTLCardinality-10
lola: result : false
lola: markings : 669
lola: fired transitions : 1237
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 29 FMS-PT-00005-CTLCardinality-09
lola: time limit : 879 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for FMS-PT-00005-CTLCardinality-09
lola: result : false
lola: markings : 812
lola: fired transitions : 6147
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 FMS-PT-00005-CTLCardinality-05
lola: time limit : 1172 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for FMS-PT-00005-CTLCardinality-05
lola: result : true
lola: markings : 73
lola: fired transitions : 84
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 29 FMS-PT-00005-CTLCardinality-09
lola: time limit : 1758 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for FMS-PT-00005-CTLCardinality-09
lola: result : true
lola: markings : 30
lola: fired transitions : 44
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 FMS-PT-00005-CTLCardinality-08
lola: time limit : 3517 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for FMS-PT-00005-CTLCardinality-08
lola: result : false
lola: markings : 3780
lola: fired transitions : 28619
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-00005-CTLCardinality-01: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-03: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-04: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-05: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-06: DISJ false DISJ
FMS-PT-00005-CTLCardinality-07: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-08: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-09: DISJ true CTL model checker
FMS-PT-00005-CTLCardinality-10: SP ECTL true LTL model checker
FMS-PT-00005-CTLCardinality-11: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-12: CTL false CTL model checker
FMS-PT-00005-CTLCardinality-13: CTL true CTL model checker
FMS-PT-00005-CTLCardinality-14: INITIAL true preprocessing
FMS-PT-00005-CTLCardinality-15: CTL false CTL model checker
Time elapsed: 83 secs. Pages in use: 12
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-00005"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FMS-PT-00005, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852700193"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-00005.tgz
mv FMS-PT-00005 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;