Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852500106.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Echo-PT-d04r03, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852500106
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 976K
-rw-r--r-- 1 mcc users 6.6K Feb 25 14:07 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 25 14:07 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 14:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 14:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 14:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Feb 25 14:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 25 14:08 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 25 14:08 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 530K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Echo-PT-d04r03-CTLFireability-00
FORMULA_NAME Echo-PT-d04r03-CTLFireability-01
FORMULA_NAME Echo-PT-d04r03-CTLFireability-02
FORMULA_NAME Echo-PT-d04r03-CTLFireability-03
FORMULA_NAME Echo-PT-d04r03-CTLFireability-04
FORMULA_NAME Echo-PT-d04r03-CTLFireability-05
FORMULA_NAME Echo-PT-d04r03-CTLFireability-06
FORMULA_NAME Echo-PT-d04r03-CTLFireability-07
FORMULA_NAME Echo-PT-d04r03-CTLFireability-08
FORMULA_NAME Echo-PT-d04r03-CTLFireability-09
FORMULA_NAME Echo-PT-d04r03-CTLFireability-10
FORMULA_NAME Echo-PT-d04r03-CTLFireability-11
FORMULA_NAME Echo-PT-d04r03-CTLFireability-12
FORMULA_NAME Echo-PT-d04r03-CTLFireability-13
FORMULA_NAME Echo-PT-d04r03-CTLFireability-14
FORMULA_NAME Echo-PT-d04r03-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678441690954

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Echo-PT-d04r03
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 09:48:12] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 09:48:12] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 09:48:12] [INFO ] Load time of PNML (sax parser for PT used): 108 ms
[2023-03-10 09:48:12] [INFO ] Transformed 1019 places.
[2023-03-10 09:48:12] [INFO ] Transformed 850 transitions.
[2023-03-10 09:48:12] [INFO ] Found NUPN structural information;
[2023-03-10 09:48:12] [INFO ] Parsed PT model containing 1019 places and 850 transitions and 6340 arcs in 182 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Support contains 280 out of 1019 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1019/1019 places, 850/850 transitions.
Reduce places removed 81 places and 0 transitions.
Iterating post reduction 0 with 81 rules applied. Total rules applied 81 place count 938 transition count 850
Applied a total of 81 rules in 69 ms. Remains 938 /1019 variables (removed 81) and now considering 850/850 (removed 0) transitions.
// Phase 1: matrix 850 rows 938 cols
[2023-03-10 09:48:13] [INFO ] Computed 432 place invariants in 817 ms
[2023-03-10 09:49:07] [INFO ] Performed 676/938 implicitness test of which 0 returned IMPLICIT in 53 seconds.
[2023-03-10 09:50:34] [INFO ] Performed 819/938 implicitness test of which 0 returned IMPLICIT in 139 seconds.
[2023-03-10 09:50:34] [INFO ] Timeout of Implicit test with SMT after 139 seconds.
[2023-03-10 09:50:34] [INFO ] Implicit Places using invariants in 141329 ms returned []
[2023-03-10 09:50:34] [INFO ] Invariant cache hit.
[2023-03-10 09:53:14] [INFO ] Implicit Places using invariants and state equation in 160026 ms returned []
Implicit Place search using SMT with State Equation took 301380 ms to find 0 implicit places.
[2023-03-10 09:53:14] [INFO ] Invariant cache hit.
[2023-03-10 09:54:14] [INFO ] Performed 4/850 'is it Dead' test of which 0 returned DEAD in 59 seconds.
[2023-03-10 09:54:14] [INFO ] Dead Transitions using invariants and state equation in 60014 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 938/1019 places, 850/850 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 361468 ms. Remains : 938/1019 places, 850/850 transitions.
Support contains 280 out of 938 places after structural reductions.
[2023-03-10 09:54:14] [INFO ] Flatten gal took : 134 ms
[2023-03-10 09:54:14] [INFO ] Flatten gal took : 83 ms
[2023-03-10 09:54:14] [INFO ] Input system was already deterministic with 850 transitions.
Support contains 257 out of 938 places (down from 280) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 61 resets, run finished after 363 ms. (steps per millisecond=27 ) properties (out of 61) seen :59
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-10 09:54:15] [INFO ] Invariant cache hit.
[2023-03-10 09:54:16] [INFO ] [Real]Absence check using 0 positive and 432 generalized place invariants in 777 ms returned sat
[2023-03-10 09:54:16] [INFO ] After 1297ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-10 09:54:26] [INFO ] [Nat]Absence check using 0 positive and 432 generalized place invariants in 9824 ms returned sat
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:631)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-10 09:54:41] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-10 09:54:41] [INFO ] After 25026ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:2
Fused 2 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 44 out of 938 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 938/938 places, 850/850 transitions.
Graph (complete) has 3593 edges and 938 vertex of which 924 are kept as prefixes of interest. Removing 14 places using SCC suffix rule.5 ms
Discarding 14 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 6 place count 924 transition count 844
Applied a total of 6 rules in 72 ms. Remains 924 /938 variables (removed 14) and now considering 844/850 (removed 6) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 72 ms. Remains : 924/938 places, 844/850 transitions.
Incomplete random walk after 10000 steps, including 62 resets, run finished after 175 ms. (steps per millisecond=57 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 2) seen :1
Finished Best-First random walk after 2314 steps, including 0 resets, run visited all 1 properties in 9 ms. (steps per millisecond=257 )
[2023-03-10 09:54:41] [INFO ] Flatten gal took : 56 ms
[2023-03-10 09:54:41] [INFO ] Flatten gal took : 52 ms
[2023-03-10 09:54:42] [INFO ] Input system was already deterministic with 850 transitions.
Computed a total of 938 stabilizing places and 850 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 938 transition count 850
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 2 formulas.
FORMULA Echo-PT-d04r03-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in SI_CTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Graph (complete) has 3593 edges and 938 vertex of which 929 are kept as prefixes of interest. Removing 9 places using SCC suffix rule.7 ms
Discarding 9 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 45 ms. Remains 928 /938 variables (removed 10) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 46 ms. Remains : 928/938 places, 848/850 transitions.
[2023-03-10 09:54:42] [INFO ] Flatten gal took : 44 ms
[2023-03-10 09:54:42] [INFO ] Flatten gal took : 47 ms
[2023-03-10 09:54:42] [INFO ] Input system was already deterministic with 848 transitions.
Starting structural reductions in LTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Applied a total of 0 rules in 12 ms. Remains 938 /938 variables (removed 0) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 938/938 places, 850/850 transitions.
[2023-03-10 09:54:42] [INFO ] Flatten gal took : 44 ms
[2023-03-10 09:54:42] [INFO ] Flatten gal took : 46 ms
[2023-03-10 09:54:42] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in LTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Applied a total of 0 rules in 10 ms. Remains 938 /938 variables (removed 0) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 938/938 places, 850/850 transitions.
[2023-03-10 09:54:42] [INFO ] Flatten gal took : 41 ms
[2023-03-10 09:54:42] [INFO ] Flatten gal took : 41 ms
[2023-03-10 09:54:42] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Graph (complete) has 3593 edges and 938 vertex of which 929 are kept as prefixes of interest. Removing 9 places using SCC suffix rule.5 ms
Discarding 9 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Applied a total of 1 rules in 35 ms. Remains 929 /938 variables (removed 9) and now considering 849/850 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 929/938 places, 849/850 transitions.
[2023-03-10 09:54:42] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:54:42] [INFO ] Flatten gal took : 42 ms
[2023-03-10 09:54:42] [INFO ] Input system was already deterministic with 849 transitions.
Starting structural reductions in LTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Applied a total of 0 rules in 11 ms. Remains 938 /938 variables (removed 0) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 938/938 places, 850/850 transitions.
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 43 ms
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:54:43] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Graph (complete) has 3593 edges and 938 vertex of which 929 are kept as prefixes of interest. Removing 9 places using SCC suffix rule.4 ms
Discarding 9 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Applied a total of 1 rules in 34 ms. Remains 929 /938 variables (removed 9) and now considering 849/850 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 36 ms. Remains : 929/938 places, 849/850 transitions.
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 41 ms
[2023-03-10 09:54:43] [INFO ] Input system was already deterministic with 849 transitions.
Starting structural reductions in LTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Applied a total of 0 rules in 10 ms. Remains 938 /938 variables (removed 0) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 938/938 places, 850/850 transitions.
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 37 ms
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 38 ms
[2023-03-10 09:54:43] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in LTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Applied a total of 0 rules in 11 ms. Remains 938 /938 variables (removed 0) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 938/938 places, 850/850 transitions.
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 37 ms
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 40 ms
[2023-03-10 09:54:43] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Graph (complete) has 3593 edges and 938 vertex of which 929 are kept as prefixes of interest. Removing 9 places using SCC suffix rule.3 ms
Discarding 9 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 30 ms. Remains 928 /938 variables (removed 10) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 928/938 places, 848/850 transitions.
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 37 ms
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:54:43] [INFO ] Input system was already deterministic with 848 transitions.
Starting structural reductions in LTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Applied a total of 0 rules in 11 ms. Remains 938 /938 variables (removed 0) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 938/938 places, 850/850 transitions.
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 37 ms
[2023-03-10 09:54:43] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:54:44] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in LTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Applied a total of 0 rules in 12 ms. Remains 938 /938 variables (removed 0) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 938/938 places, 850/850 transitions.
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 40 ms
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 41 ms
[2023-03-10 09:54:44] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Graph (complete) has 3593 edges and 938 vertex of which 929 are kept as prefixes of interest. Removing 9 places using SCC suffix rule.3 ms
Discarding 9 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 27 ms. Remains 928 /938 variables (removed 10) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 928/938 places, 848/850 transitions.
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 42 ms
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 38 ms
[2023-03-10 09:54:44] [INFO ] Input system was already deterministic with 848 transitions.
Finished random walk after 1215 steps, including 7 resets, run visited all 1 properties in 16 ms. (steps per millisecond=75 )
FORMULA Echo-PT-d04r03-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Applied a total of 0 rules in 11 ms. Remains 938 /938 variables (removed 0) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 938/938 places, 850/850 transitions.
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 37 ms
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:54:44] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Graph (complete) has 3593 edges and 938 vertex of which 929 are kept as prefixes of interest. Removing 9 places using SCC suffix rule.3 ms
Discarding 9 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 25 ms. Remains 928 /938 variables (removed 10) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 928/938 places, 848/850 transitions.
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 35 ms
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 38 ms
[2023-03-10 09:54:44] [INFO ] Input system was already deterministic with 848 transitions.
Finished random walk after 10 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=5 )
FORMULA Echo-PT-d04r03-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 938/938 places, 850/850 transitions.
Graph (complete) has 3593 edges and 938 vertex of which 929 are kept as prefixes of interest. Removing 9 places using SCC suffix rule.2 ms
Discarding 9 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 24 ms. Remains 928 /938 variables (removed 10) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 928/938 places, 848/850 transitions.
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 36 ms
[2023-03-10 09:54:44] [INFO ] Flatten gal took : 44 ms
[2023-03-10 09:54:44] [INFO ] Input system was already deterministic with 848 transitions.
[2023-03-10 09:54:45] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:54:45] [INFO ] Flatten gal took : 40 ms
[2023-03-10 09:54:45] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-10 09:54:45] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 938 places, 850 transitions and 5915 arcs took 6 ms.
Total runtime 392744 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Echo-PT-d04r03
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA Echo-PT-d04r03-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d04r03-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d04r03-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d04r03-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d04r03-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d04r03-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678442929669

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: LAUNCH task # 25 (type EXCL) for 24 Echo-PT-d04r03-CTLFireability-09
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 25 (type EXCL) for Echo-PT-d04r03-CTLFireability-09
lola: result : false
lola: markings : 150
lola: fired transitions : 149
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 Echo-PT-d04r03-CTLFireability-02
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d04r03-CTLFireability-09: AGEF false tscc_search

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Echo-PT-d04r03-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLFireability-10: CONJ 0 3 0 0 3 0 0 0
Echo-PT-d04r03-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 4/256 2/32 Echo-PT-d04r03-CTLFireability-02 201171 m, 40234 m/sec, 1234878 t fired, .

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7 CTL EXCL 9/256 3/32 Echo-PT-d04r03-CTLFireability-02 435260 m, 46817 m/sec, 2866323 t fired, .

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7 CTL EXCL 14/256 5/32 Echo-PT-d04r03-CTLFireability-02 670520 m, 47052 m/sec, 4487502 t fired, .

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7 CTL EXCL 19/256 6/32 Echo-PT-d04r03-CTLFireability-02 894441 m, 44784 m/sec, 6100964 t fired, .

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7 CTL EXCL 24/256 8/32 Echo-PT-d04r03-CTLFireability-02 1121160 m, 45343 m/sec, 7725322 t fired, .

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7 CTL EXCL 29/256 9/32 Echo-PT-d04r03-CTLFireability-02 1330514 m, 41870 m/sec, 9318884 t fired, .

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Echo-PT-d04r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 110/2877 31/32 Echo-PT-d04r03-CTLFireability-03 4717187 m, 42602 m/sec, 35677439 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d04r03-CTLFireability-00: CTL false CTL model checker
Echo-PT-d04r03-CTLFireability-01: CTL true CTL model checker
Echo-PT-d04r03-CTLFireability-05: CTL true CTL model checker
Echo-PT-d04r03-CTLFireability-09: AGEF false tscc_search
Echo-PT-d04r03-CTLFireability-10: CONJ false CTL model checker
Echo-PT-d04r03-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d04r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d04r03-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 115/2877 32/32 Echo-PT-d04r03-CTLFireability-03 4915363 m, 39635 m/sec, 37304433 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d04r03-CTLFireability-00: CTL false CTL model checker
Echo-PT-d04r03-CTLFireability-01: CTL true CTL model checker
Echo-PT-d04r03-CTLFireability-05: CTL true CTL model checker
Echo-PT-d04r03-CTLFireability-09: AGEF false tscc_search
Echo-PT-d04r03-CTLFireability-10: CONJ false CTL model checker
Echo-PT-d04r03-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d04r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d04r03-CTLFireability-00: CTL false CTL model checker
Echo-PT-d04r03-CTLFireability-01: CTL true CTL model checker
Echo-PT-d04r03-CTLFireability-02: CTL unknown AGGR
Echo-PT-d04r03-CTLFireability-03: CTL unknown AGGR
Echo-PT-d04r03-CTLFireability-05: CTL true CTL model checker
Echo-PT-d04r03-CTLFireability-06: CTL unknown AGGR
Echo-PT-d04r03-CTLFireability-07: CTL unknown AGGR
Echo-PT-d04r03-CTLFireability-08: CTL unknown AGGR
Echo-PT-d04r03-CTLFireability-09: AGEF false tscc_search
Echo-PT-d04r03-CTLFireability-10: CONJ false CTL model checker
Echo-PT-d04r03-CTLFireability-11: CTL unknown AGGR
Echo-PT-d04r03-CTLFireability-13: CTL false CTL model checker
Echo-PT-d04r03-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Echo-PT-d04r03"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Echo-PT-d04r03, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852500106"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Echo-PT-d04r03.tgz
mv Echo-PT-d04r03 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;