MCC'2023- Execution of r167-tall-167838852500090

About the Execution of LoLa+red for Echo-PT-d03r05

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
2957.184	1325476.00	1334246.00	3653.90	?F????TFTFT?TTF?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input
Waiting for the VM to be
.................................
===========
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Echo-PT-d03r05,
Time confinement is
Memory confinement is
Number of cores is 4
Run identifier is r167-tall-1
=================================

--------------------
preparation of the directory
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.6K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 4.7K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 4.2K
-rw-r--r-- 1 mcc users 5.9K
-rw-r--r-- 1 mcc users 3.8K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 2.2K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 109K
-rw-r--r-- 1 mcc users 9.3K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 1.6K
-rw-r--r-- 1 mcc users 3.6K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 716K Mar

--------------------
content from stdout:

=== Data for post analysis

The expected result is a
BOOL_VECTOR

here is the order used to
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi
FORMULA_NAME Echo-PT-d03r05-CTLFi

=== Now, execution of the

BK_START 1678438473008

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bi
BK_TIME_CONFINEMENT=3600
BK_INPUT=Echo-PT-d03r05
Applying reductions before
Invoking reducer
Running Version 202303021504
[2023-03-10 08:54:34] [INFO
[2023-03-10 08:54:34] [INFO
[2023-03-10 08:54:34] [INFO
[2023-03-10 08:54:34] [INFO
[2023-03-10 08:54:34] [INFO
[2023-03-10 08:54:34] [INFO
[2023-03-10 08:54:34] [INFO
Parsed 16 properties from
Support contains 275 out
Starting structural reductions
Reduce places removed 125
Iterating post reduction
Applied a total of 125 rules
// Phase 1: matrix 1190
[2023-03-10 08:54:36] [INFO
[2023-03-10 08:54:38] [INFO
[2023-03-10 08:54:38] [INFO
[2023-03-10 08:57:18] [INFO
[2023-03-10 08:57:18] [INFO
[2023-03-10 08:57:18] [INFO
Implicit Place search using
[2023-03-10 08:57:18] [INFO
[2023-03-10 08:57:26] [INFO
Starting structural reductions
Finished structural reductions
Support contains 275 out
[2023-03-10 08:57:26] [INFO
[2023-03-10 08:57:26] [INFO
[2023-03-10 08:57:26] [INFO
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Running SMT prover for 1
[2023-03-10 08:57:27] [INFO
[2023-03-10 08:57:30] [INFO
java.lang.RuntimeException:
at fr.lip6.move.gal.structural.s
at fr.lip6.move.gal.structural.s
at fr.lip6.move.gal.structural.s
at fr.lip6.move.gal.structural.s
at fr.lip6.move.gal.structural.s
at fr.lip6.move.gal.application.
at fr.lip6.move.gal.application.
at fr.lip6.move.gal.application.
at fr.lip6.move.gal.application.
at fr.lip6.move.gal.application.
at fr.lip6.move.gal.application.
at fr.lip6.move.gal.itscl.applic
at org.eclipse.equinox.internal.
at org.eclipse.core.runtime.inte
at org.eclipse.core.runtime.inte
at org.eclipse.core.runtime.adap
at org.eclipse.core.runtime.adap
at java.base/jdk.internal.reflec
at java.base/jdk.internal.reflec
at java.base/jdk.internal.reflec
at java.base/java.lang.reflect.M
at org.eclipse.equinox.launcher.
at org.eclipse.equinox.launcher.
at org.eclipse.equinox.launcher.
at org.eclipse.equinox.launcher.
[2023-03-10 08:57:52] [WARNING]
[2023-03-10 08:57:52] [INFO
Parikh walk visited 0 properties
Support contains 6 out of
Starting structural reductions
Graph (complete) has 4723
Discarding 13 places :
Also discarding 1 output
Drop transitions removed
Drop transitions removed
Reduce isomorphic transitions
Iterating post reduction
Reduce places removed 1
Iterating global reduction
Applied a total of 8 rules
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Interrupted probabilistic
Probabilistic random walk after 556491
Running SMT prover for 1
// Phase 1: matrix 1182
[2023-03-10 08:57:57] [INFO
[2023-03-10 08:57:58] [INFO
[2023-03-10 08:58:08] [INFO
Parikh walk visited 0 properties
Support contains 6 out of
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
Starting structural reductions
Applied a total of 0 rules
[2023-03-10 08:58:08] [INFO
[2023-03-10 08:58:22] [INFO
Discarding 5 places :
Implicit Place search using
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
Finished random walk after 836
[2023-03-10 08:58:22] [INFO
[2023-03-10 08:58:22] [INFO
[2023-03-10 08:58:22] [INFO
Computed a total of 1320
Complete graph has no SCC;
Detected that all paths
AF dead knowledge conclusive
FORMULA Echo-PT-d03r05-CTLFireability-08
FORMULA Echo-PT-d03r05-CTL
FORMULA Echo-PT-d03r05-CTL
Starting structural
Applied a total of 0 rules
Finished structural reductions
[2023-03-10 08:58:22] [INFO
[2023-03-10 08:58:23] [INFO
[2023-03-10 08:58:23] [INFO
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
[2023-03-10 08:58:23] [INFO
[2023-03-10 08:58:23] [INFO
[2023-03-10 08:58:23] [INFO
Starting structural reductions
Graph (complete) has 4723
Discarding 7 places :
Also discarding 1 output
Drop transitions removed
Applied a total of 1 rules
Finished structural reductions
[2023-03-10 08:58:23] [INFO
[2023-03-10 08:58:23] [INFO
[2023-03-10 08:58:23] [INFO
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
[2023-03-10 08:58:23] [INFO
[2023-03-10 08:58:23] [INFO
[2023-03-10 08:58:23] [INFO
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
[2023-03-10 08:58:24] [INFO
[2023-03-10 08:58:24] [INFO
[2023-03-10 08:58:24] [INFO
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
[2023-03-10 08:58:24] [INFO
[2023-03-10 08:58:24] [INFO
[2023-03-10 08:58:24] [INFO
Starting structural reductions
Graph (complete) has 4723
Discarding 7 places :
Also discarding 1 output
Drop transitions removed
Reduce places removed 1
Applied a total of 1 rules
Finished structural reductions
[2023-03-10 08:58:24] [INFO
[2023-03-10 08:58:24] [INFO
[2023-03-10 08:58:24] [INFO
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
[2023-03-10 08:58:24] [INFO
[2023-03-10 08:58:24] [INFO
[2023-03-10 08:58:24] [INFO
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
[2023-03-10 08:58:25] [INFO
[2023-03-10 08:58:25] [INFO
[2023-03-10 08:58:25] [INFO
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
[2023-03-10 08:58:25] [INFO
[2023-03-10 08:58:25] [INFO
[2023-03-10 08:58:25] [INFO
Starting structural reductions
Graph (complete) has 4723
Discarding 7 places :
Also discarding 1 output
Drop transitions removed
Reduce places removed 1
Applied a total of 1 rules
Finished structural reductions
[2023-03-10 08:58:25] [INFO
[2023-03-10 08:58:25] [INFO
[2023-03-10 08:58:25] [INFO
Starting structural reductions
Applied a total of 0 rules
Finished structural reductions
[2023-03-10 08:58:25] [INFO
[2023-03-10 08:58:25] [INFO
[2023-03-10 08:58:25] [INFO
Starting structural reductions
Graph (complete) has 4723
Discarding 7 places :
Also discarding 1 output
Drop transitions removed
Reduce places removed 1
Applied a total of 1 rules
Finished structural reductions
[2023-03-10 08:58:26] [INFO
[2023-03-10 08:58:26] [INFO
[2023-03-10 08:58:26] [INFO
[2023-03-10 08:58:26] [INFO
[2023-03-10 08:58:26] [INFO
[2023-03-10 08:58:26] [INFO
[2023-03-10 08:58:26] [INFO
Total runtime 231921 ms.
There are residual formulas
starting LoLA
BK_INPUT Echo-PT-d03r05
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit
current directory: /home/mcc/exec
CTLFireability

FORMULA Echo-PT-d03r05-CTLFireability-13

FORMULA Echo-PT-d03r05-CTLFireability-09

FORMULA Echo-PT-d03r05-CTLFireability-07

FORMULA Echo-PT-d03r05-CTLFireability-01

FORMULA Echo-PT-d03r05-CTLFireability-12

FORMULA Echo-PT-d03r05-CTLFireability-06

BK_STOP 1678439798484

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=85899345
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/Ben
+ PYTHONPATH=/home/mcc/BenchKit/i
+ export LD_LIBRARY_PATH=/home/mc
+ LD_LIBRARY_PATH=/home/mcc/Bench
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../
+ VERSION=202303021504
+ echo 'Running Version
+ /home/mcc/BenchKit/bin//../redu
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file
lola: reading net from
lola: reading pnml
lola: PNML file contains
lola: finished parsing
lola: closed net file
lola: Reading formula.
lola: Using XML format
lola: reading XML formula
lola: reading formula
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: RELEASE
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: RELEASE
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: RELEASE
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Rule S: 0 transitions
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: LAUNCH task # 24
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: FINISHED task #
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 13
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
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lola: rewrite Frontend/Parser/f
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lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
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lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
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lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
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lola: rewrite Frontend/Parser/f
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lola: rewrite Frontend/Parser/f
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lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
lola: rewrite Frontend/Parser/f
FINISHED FORMULA: CATEGORY

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Echo-PT-d03r05-CTLFireability-02: SP ACTL
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.r167-tall-167838852500090.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16 ready (probing ssh) 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========================================================== examination is CTLFireability 3600 seconds 16384 MBytes 67838852500090 ==================================== to be used: Feb 25 14:05 CTLCardinality.txt 69K Feb 25 14:05 CTLCardinality.xml Feb 25 14:04 CTLFireability.txt 41K Feb 25 14:04 CTLFireability.xml Jan 29 11:40 GenericPropertiesDefinition.xml Jan 29 11:40 GenericPropertiesVerdict.xml Feb 25 16:03 LTLCardinality.txt 26K Feb 25 16:03 LTLCardinality.xml Feb 25 16:03 LTLFireability.txt 17K Feb 25 16:03 LTLFireability.xml 11K Feb 25 14:07 ReachabilityCardinality.txt Feb 25 14:07 ReachabilityCardinality.xml Feb 25 14:06 ReachabilityFireability.txt 82K Feb 25 14:06 ReachabilityFireability.xml Feb 25 16:03 UpperBounds.txt Feb 25 16:03 UpperBounds.xml 6 Mar 5 18:22 equiv_col 7 Mar 5 18:22 instance 6 Mar 5 18:22 iscolored 5 18:22 model.pnml generated by BenchKit (invocation template) vector of booleans build the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 tool begins 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N n/ tool lola ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML] ] Parsing pnml file : /home/mcc/execution/model.pnml ] Load time of PNML (sax parser for PT used): 130 ms ] Transformed 1445 places. ] Transformed 1190 transitions. ] Found NUPN structural information; ] Parsed PT model containing 1445 places and 1190 transitions and 8260 arcs in 203 ms. file /home/mcc/execution/CTLFireability.xml in 7 ms. of 1445 places. Attempting structural reductions. in LTL mode, iteration 0 : 1445/1445 places, 1190/1190 transitions. places and 0 transitions. 0 with 125 rules applied. Total rules applied 125 place count 1320 transition count 1190 in 101 ms. Remains 1320 /1445 variables (removed 125) and now considering 1190/1190 (removed 0) transitions. rows 1320 cols ] Computed 600 place invariants in 1735 ms ] Implicit Places using invariants in 3048 ms returned [] ] Invariant cache hit. ] Performed 0/1320 implicitness test of which 0 returned IMPLICIT in 157 seconds. ] Timeout of Implicit test with SMT after 157 seconds. ] Implicit Places using invariants and state equation in 160016 ms returned [] SMT with State Equation took 163269 ms to find 0 implicit places. ] Invariant cache hit. ] Dead Transitions using invariants and state equation in 8129 ms found 0 transitions. in LTL mode, iteration 1 : 1320/1445 places, 1190/1190 transitions. in LTL mode , in 1 iterations and 171512 ms. Remains : 1320/1445 places, 1190/1190 transitions. of 1320 places after structural reductions. ] Flatten gal took : 170 ms ] Flatten gal took : 120 ms ] Input system was already deterministic with 1190 transitions. steps, including 39 resets, run finished after 475 ms. (steps per millisecond=21 ) properties (out of 65) seen :62 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 3) seen :1 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 2) seen :0 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 2) seen :1 properties. ] Invariant cache hit. ] [Real]Absence check using 0 positive and 600 generalized place invariants in 2290 ms returned sat SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ... mt.SMTUtils.execAndCheckResult(SMTUtils.java:251) mt.DeadlockTester.checkResults(DeadlockTester.java:797) mt.DeadlockTester.verifyPossible(DeadlockTester.java:631) mt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339) mt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223) solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95) solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105) solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44) solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176) Application.startNoEx(Application.java:626) Application.start(Application.java:178) ation.Application.start(Application.java:45) app.EclipseAppHandle.run(EclipseAppHandle.java:203) rnal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136) rnal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) tor.EclipseStarter.run(EclipseStarter.java:402) tor.EclipseStarter.run(EclipseStarter.java:255) t.NativeMethodAccessorImpl.invoke0(Native Method) t.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77) t.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) ethod.invoke(Method.java:568) Main.invokeFramework(Main.java:659) Main.basicRun(Main.java:596) Main.run(Main.java:1467) Main.main(Main.java:1440) SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions. ] After 25029ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 in 0 ms. 1320 places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. edges and 1320 vertex of which 1307 are kept as prefixes of interest. Removing 13 places using SCC suffix rule.7 ms transitions 1 transitions 6 transitions removed 6 transitions. 0 with 6 rules applied. Total rules applied 7 place count 1307 transition count 1183 places and 1 transitions. 1 with 1 rules applied. Total rules applied 8 place count 1306 transition count 1182 in 198 ms. Remains 1306 /1320 variables (removed 14) and now considering 1182/1190 (removed 8) transitions. in REACHABILITY mode , in 1 iterations and 198 ms. Remains : 1306/1320 places, 1182/1190 transitions. steps, including 40 resets, run finished after 146 ms. (steps per millisecond=68 ) properties (out of 1) seen :0 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 1) seen :0 random walk after 556491 steps, run timeout after 3001 ms. (steps per millisecond=185 ) properties seen :{} steps, saw 90260 distinct states, run finished after 3002 ms. (steps per millisecond=185 ) properties seen :0 properties. rows 1306 cols ] Computed 588 place invariants in 1688 ms ] [Real]Absence check using 0 positive and 588 generalized place invariants in 974 ms returned sat ] After 10886ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 in 0 ms. 1306 places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 1306/1306 places, 1182/1182 transitions. in 41 ms. Remains 1306 /1306 variables (removed 0) and now considering 1182/1182 (removed 0) transitions. in REACHABILITY mode , in 1 iterations and 42 ms. Remains : 1306/1306 places, 1182/1182 transitions. in REACHABILITY mode, iteration 0 : 1306/1306 places, 1182/1182 transitions. in 37 ms. Remains 1306 /1306 variables (removed 0) and now considering 1182/1182 (removed 0) transitions. ] Invariant cache hit. ] Implicit Places using invariants in 13812 ms returned [712, 733, 738, 759, 860] SMT only with invariants took 13823 ms to find 5 implicit places. in REACHABILITY mode, iteration 1 : 1301/1306 places, 1182/1182 transitions. in 46 ms. Remains 1301 /1301 variables (removed 0) and now considering 1182/1182 (removed 0) transitions. in REACHABILITY mode , in 2 iterations and 13908 ms. Remains : 1301/1306 places, 1182/1182 transitions. steps, including 3 resets, run visited all 1 properties in 14 ms. (steps per millisecond=59 ) ] Flatten gal took : 68 ms ] Flatten gal took : 69 ms ] Input system was already deterministic with 1190 transitions. stabilizing places and 1190 stable transitions deadlocks are unavoidable. place count 1320 transition count 1190 lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false). for 3 formulas. TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE Fireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE Fireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE reductions in LTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. in 27 ms. Remains 1320 /1320 variables (removed 0) and now considering 1190/1190 (removed 0) transitions. in LTL mode , in 1 iterations and 27 ms. Remains : 1320/1320 places, 1190/1190 transitions. ] Flatten gal took : 57 ms ] Flatten gal took : 61 ms ] Input system was already deterministic with 1190 transitions. in LTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. in 18 ms. Remains 1320 /1320 variables (removed 0) and now considering 1190/1190 (removed 0) transitions. in LTL mode , in 1 iterations and 18 ms. Remains : 1320/1320 places, 1190/1190 transitions. ] Flatten gal took : 54 ms ] Flatten gal took : 59 ms ] Input system was already deterministic with 1190 transitions. in SI_CTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. edges and 1320 vertex of which 1313 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.7 ms transitions 1 transitions in 95 ms. Remains 1313 /1320 variables (removed 7) and now considering 1189/1190 (removed 1) transitions. in SI_CTL mode , in 1 iterations and 95 ms. Remains : 1313/1320 places, 1189/1190 transitions. ] Flatten gal took : 48 ms ] Flatten gal took : 53 ms ] Input system was already deterministic with 1189 transitions. in LTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. in 19 ms. Remains 1320 /1320 variables (removed 0) and now considering 1190/1190 (removed 0) transitions. in LTL mode , in 1 iterations and 20 ms. Remains : 1320/1320 places, 1190/1190 transitions. ] Flatten gal took : 48 ms ] Flatten gal took : 50 ms ] Input system was already deterministic with 1190 transitions. in LTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. in 18 ms. Remains 1320 /1320 variables (removed 0) and now considering 1190/1190 (removed 0) transitions. in LTL mode , in 1 iterations and 18 ms. Remains : 1320/1320 places, 1190/1190 transitions. ] Flatten gal took : 47 ms ] Flatten gal took : 50 ms ] Input system was already deterministic with 1190 transitions. in LTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. in 17 ms. Remains 1320 /1320 variables (removed 0) and now considering 1190/1190 (removed 0) transitions. in LTL mode , in 1 iterations and 18 ms. Remains : 1320/1320 places, 1190/1190 transitions. ] Flatten gal took : 46 ms ] Flatten gal took : 50 ms ] Input system was already deterministic with 1190 transitions. in SI_CTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. edges and 1320 vertex of which 1313 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.4 ms transitions 1 transitions places and 1 transitions. in 46 ms. Remains 1312 /1320 variables (removed 8) and now considering 1188/1190 (removed 2) transitions. in SI_CTL mode , in 1 iterations and 47 ms. Remains : 1312/1320 places, 1188/1190 transitions. ] Flatten gal took : 47 ms ] Flatten gal took : 50 ms ] Input system was already deterministic with 1188 transitions. in LTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. in 17 ms. Remains 1320 /1320 variables (removed 0) and now considering 1190/1190 (removed 0) transitions. in LTL mode , in 1 iterations and 18 ms. Remains : 1320/1320 places, 1190/1190 transitions. ] Flatten gal took : 46 ms ] Flatten gal took : 48 ms ] Input system was already deterministic with 1190 transitions. in LTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. in 16 ms. Remains 1320 /1320 variables (removed 0) and now considering 1190/1190 (removed 0) transitions. in LTL mode , in 1 iterations and 17 ms. Remains : 1320/1320 places, 1190/1190 transitions. ] Flatten gal took : 47 ms ] Flatten gal took : 54 ms ] Input system was already deterministic with 1190 transitions. in LTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. in 18 ms. Remains 1320 /1320 variables (removed 0) and now considering 1190/1190 (removed 0) transitions. in LTL mode , in 1 iterations and 19 ms. Remains : 1320/1320 places, 1190/1190 transitions. ] Flatten gal took : 47 ms ] Flatten gal took : 49 ms ] Input system was already deterministic with 1190 transitions. in SI_CTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. edges and 1320 vertex of which 1313 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.4 ms transitions 1 transitions places and 1 transitions. in 44 ms. Remains 1312 /1320 variables (removed 8) and now considering 1188/1190 (removed 2) transitions. in SI_CTL mode , in 1 iterations and 44 ms. Remains : 1312/1320 places, 1188/1190 transitions. ] Flatten gal took : 47 ms ] Flatten gal took : 51 ms ] Input system was already deterministic with 1188 transitions. in LTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. in 21 ms. Remains 1320 /1320 variables (removed 0) and now considering 1190/1190 (removed 0) transitions. in LTL mode , in 1 iterations and 22 ms. Remains : 1320/1320 places, 1190/1190 transitions. ] Flatten gal took : 45 ms ] Flatten gal took : 49 ms ] Input system was already deterministic with 1190 transitions. in SI_CTL mode, iteration 0 : 1320/1320 places, 1190/1190 transitions. edges and 1320 vertex of which 1313 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.4 ms transitions 1 transitions places and 1 transitions. in 38 ms. Remains 1312 /1320 variables (removed 8) and now considering 1188/1190 (removed 2) transitions. in SI_CTL mode , in 1 iterations and 38 ms. Remains : 1312/1320 places, 1188/1190 transitions. ] Flatten gal took : 51 ms ] Flatten gal took : 47 ms ] Input system was already deterministic with 1188 transitions. ] Flatten gal took : 50 ms ] Flatten gal took : 50 ms ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms. ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1320 places, 1190 transitions and 7665 arcs took 8 ms. that ITS could not solve within timeout /bin//../reducer/bin//../../lola/bin/ ution/372 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT 92 chKit/itstools/pylibs tstools/pylibs c/BenchKit/itstools/pylibs: Kit/itstools/pylibs: reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar 202303021504' cer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML (--pnmlnet) /home/mcc/execution/372/model.pnml place/transition net /home/mcc/execution/372/model.pnml (--xmlformula) from /home/mcc/execution/372/CTLFireability.xml ormula_rewrite.k:250 ormula_rewrite.k:322 ormula_rewrite.k:331 ormula_rewrite.k:296 ormula_rewrite.k:317 ormula_rewrite.k:325 ormula_rewrite.k:328 ormula_rewrite.k:299 ormula_rewrite.k:322 ormula_rewrite.k:331 ormula_rewrite.k:296 ormula_rewrite.k:250 ormula_rewrite.k:317 ormula_rewrite.k:296 ormula_rewrite.k:317 ormula_rewrite.k:296 ormula_rewrite.k:322 ormula_rewrite.k:334 ormula_rewrite.k:325 ormula_rewrite.k:331 ormula_rewrite.k:296 ormula_rewrite.k:475 ormula_rewrite.k:325 ormula_rewrite.k:334 ormula_rewrite.k:325 ormula_rewrite.k:337 ormula_rewrite.k:296 ormula_rewrite.k:296 ormula_rewrite.k:325 ormula_rewrite.k:331 ormula_rewrite.k:325 ormula_rewrite.k:328 ormula_rewrite.k:296 ormula_rewrite.k:475 ormula_rewrite.k:325 ormula_rewrite.k:337 ormula_rewrite.k:296 ormula_rewrite.k:314 ormula_rewrite.k:322 ormula_rewrite.k:334 ormula_rewrite.k:296 ormula_rewrite.k:322 ormula_rewrite.k:328 ormula_rewrite.k:296 ormula_rewrite.k:325 ormula_rewrite.k:328 ormula_rewrite.k:296 ormula_rewrite.k:253 ormula_rewrite.k:317 ormula_rewrite.k:325 ormula_rewrite.k:334 ormula_rewrite.k:296 ormula_rewrite.k:317 ormula_rewrite.k:296 ormula_rewrite.k:296 ormula_rewrite.k:544 ormula_rewrite.k:397 ormula_rewrite.k:544 ormula_rewrite.k:544 ormula_rewrite.k:397 ormula_rewrite.k:544 ormula_rewrite.k:325 ormula_rewrite.k:334 ormula_rewrite.k:296 ormula_rewrite.k:478 ormula_rewrite.k:553 ormula_rewrite.k:553 ormula_rewrite.k:553 ormula_rewrite.k:322 ormula_rewrite.k:337 ormula_rewrite.k:296 ormula_rewrite.k:296 in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. removed,0 places removed in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. ormula_rewrite.k:679 ormula_rewrite.k:679 ormula_rewrite.k:813 ormula_rewrite.k:811 ormula_rewrite.k:813 ormula_rewrite.k:815 ormula_rewrite.k:812 ormula_rewrite.k:809 ormula_rewrite.k:809 ormula_rewrite.k:811 ormula_rewrite.k:811 ormula_rewrite.k:808 ormula_rewrite.k:807 ormula_rewrite.k:814 ormula_rewrite.k:809 ormula_rewrite.k:813 ormula_rewrite.k:807 (type EXCL) for 21 Echo-PT-d03r05-CTLFireability-07 ormula_rewrite.k:730 ormula_rewrite.k:811 ormula_rewrite.k:808 24 (type EXCL) for Echo-PT-d03r05-CTLFireability-07 : false 1 1 0.000000 1 (type EXCL) for 12 Echo-PT-d03r05-CTLFireability-04 ormula_rewrite.k:808 ormula_rewrite.k:806 ormula_rewrite.k:808 ormula_rewrite.k:813 ormula_rewrite.k:807 ormula_rewrite.k:814 ormula_rewrite.k:814 ormula_rewrite.k:812 ormula_rewrite.k:811 ormula_rewrite.k:809 ormula_rewrite.k:813 ormula_rewrite.k:807 ormula_rewrite.k:811 ormula_rewrite.k:812 ormula_rewrite.k:811 ormula_rewrite.k:813 ormula_rewrite.k:811 ormula_rewrite.k:808 ormula_rewrite.k:808 ormula_rewrite.k:809 ormula_rewrite.k:809 ormula_rewrite.k:807 ormula_rewrite.k:808 ormula_rewrite.k:809 ormula_rewrite.k:811 ormula_rewrite.k:809 ormula_rewrite.k:808 ormula_rewrite.k:809 ormula_rewrite.k:807 ormula_rewrite.k:807 ormula_rewrite.k:807 ormula_rewrite.k:807 ormula_rewrite.k:814 ormula_rewrite.k:807 ormula_rewrite.k:814 ormula_rewrite.k:811 ormula_rewrite.k:810 ormula_rewrite.k:811 ormula_rewrite.k:813 ormula_rewrite.k:806 ormula_rewrite.k:813 ormula_rewrite.k:809 ormula_rewrite.k:807 ormula_rewrite.k:812 ormula_rewrite.k:806 ormula_rewrite.k:811 ormula_rewrite.k:813 ormula_rewrite.k:807 ormula_rewrite.k:806 ormula_rewrite.k:815 ormula_rewrite.k:813 ormula_rewrite.k:812 ormula_rewrite.k:811 ormula_rewrite.k:813 ormula_rewrite.k:813 ormula_rewrite.k:812 ormula_rewrite.k:813 ormula_rewrite.k:813 ormula_rewrite.k:814 ormula_rewrite.k:714 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 Echo-PT-d03r05-CTLFireability-04 160623 m, 32124 m/sec, 954368 t fired, . Pages in use: 2 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 Echo-PT-d03r05-CTLFireability-04 328712 m, 33617 m/sec, 2098607 t fired, . Pages in use: 3 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 Echo-PT-d03r05-CTLFireability-04 494780 m, 33213 m/sec, 3238934 t fired, . Pages in use: 4 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 Echo-PT-d03r05-CTLFireability-04 660900 m, 33224 m/sec, 4389572 t fired, . Pages in use: 5 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 Echo-PT-d03r05-CTLFireability-04 829725 m, 33765 m/sec, 5537818 t fired, . Pages in use: 7 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 Echo-PT-d03r05-CTLFireability-04 986562 m, 31367 m/sec, 6680101 t fired, . Pages in use: 8 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 Echo-PT-d03r05-CTLFireability-04 1126982 m, 28084 m/sec, 7791988 t fired, . Pages in use: 9 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 Echo-PT-d03r05-CTLFireability-04 1270413 m, 28686 m/sec, 8917918 t fired, . Pages in use: 10 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 Echo-PT-d03r05-CTLFireability-04 1414270 m, 28771 m/sec, 10056921 t fired, . Pages in use: 11 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 Echo-PT-d03r05-CTLFireability-04 1558381 m, 28822 m/sec, 11186854 t fired, . Pages in use: 12 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 Echo-PT-d03r05-CTLFireability-04 1719638 m, 32251 m/sec, 12318038 t fired, . Pages in use: 13 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 Echo-PT-d03r05-CTLFireability-04 1863265 m, 28725 m/sec, 13439233 t fired, . Pages in use: 14 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 Echo-PT-d03r05-CTLFireability-04 2003316 m, 28010 m/sec, 14549583 t fired, . Pages in use: 15 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 Echo-PT-d03r05-CTLFireability-04 2145488 m, 28434 m/sec, 15665095 t fired, . Pages in use: 16 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 Echo-PT-d03r05-CTLFireability-04 2286548 m, 28212 m/sec, 16779948 t fired, . Pages in use: 17 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 Echo-PT-d03r05-CTLFireability-04 2444053 m, 31501 m/sec, 17915191 t fired, . Pages in use: 18 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 Echo-PT-d03r05-CTLFireability-04 2590867 m, 29362 m/sec, 19030744 t fired, . Pages in use: 19 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 Echo-PT-d03r05-CTLFireability-04 2731755 m, 28177 m/sec, 20135543 t fired, . Pages in use: 20 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 Echo-PT-d03r05-CTLFireability-04 2873095 m, 28268 m/sec, 21254552 t fired, . Pages in use: 21 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 Echo-PT-d03r05-CTLFireability-04 3016479 m, 28676 m/sec, 22382069 t fired, . Pages in use: 22 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 Echo-PT-d03r05-CTLFireability-04 3160719 m, 28848 m/sec, 23513982 t fired, . Pages in use: 23 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 Echo-PT-d03r05-CTLFireability-04 3296222 m, 27100 m/sec, 24624595 t fired, . Pages in use: 24 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 Echo-PT-d03r05-CTLFireability-04 3419592 m, 24674 m/sec, 25721384 t fired, . Pages in use: 25 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 Echo-PT-d03r05-CTLFireability-04 3542310 m, 24543 m/sec, 26816807 t fired, . Pages in use: 26 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 Echo-PT-d03r05-CTLFireability-04 3667567 m, 25051 m/sec, 27934460 t fired, . Pages in use: 27 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 Echo-PT-d03r05-CTLFireability-04 3795402 m, 25567 m/sec, 29063776 t fired, . Pages in use: 28 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 Echo-PT-d03r05-CTLFireability-04 3927577 m, 26435 m/sec, 30188246 t fired, . Pages in use: 29 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 Echo-PT-d03r05-CTLFireability-04 4064040 m, 27292 m/sec, 31296052 t fired, . Pages in use: 30 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 Echo-PT-d03r05-CTLFireability-04 4187776 m, 24747 m/sec, 32396335 t fired, . Pages in use: 30 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-04 4310668 m, 24578 m/sec, 33491190 t fired, . Pages in use: 31 Visible: 13 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 Echo-PT-d03r05-CTLFireability-04 4434243 m, 24715 m/sec, 34592392 t fired, . Pages in use: 32 Visible: 13 13 (type EXCL) for Echo-PT-d03r05-CTLFireability-04 (memory limit exceeded) VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 EXEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 Visible: 13 (type EXCL) for 41 Echo-PT-d03r05-CTLFireability-13 42 (type EXCL) for Echo-PT-d03r05-CTLFireability-13 : true 12 11 0.000000 1 (type EXCL) for 35 Echo-PT-d03r05-CTLFireability-11 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 Echo-PT-d03r05-CTLFireability-11 184916 m, 36983 m/sec, 1105768 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 Echo-PT-d03r05-CTLFireability-11 344273 m, 31871 m/sec, 2207968 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 Echo-PT-d03r05-CTLFireability-11 505432 m, 32231 m/sec, 3314252 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 Echo-PT-d03r05-CTLFireability-11 666227 m, 32159 m/sec, 4425920 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 Echo-PT-d03r05-CTLFireability-11 829565 m, 32667 m/sec, 5536741 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 Echo-PT-d03r05-CTLFireability-11 982486 m, 30584 m/sec, 6646605 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 Echo-PT-d03r05-CTLFireability-11 1119927 m, 27488 m/sec, 7735127 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 Echo-PT-d03r05-CTLFireability-11 1259048 m, 27824 m/sec, 8830086 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 Echo-PT-d03r05-CTLFireability-11 1399531 m, 28096 m/sec, 9938180 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 Echo-PT-d03r05-CTLFireability-11 1539234 m, 27940 m/sec, 11045630 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 Echo-PT-d03r05-CTLFireability-11 1695685 m, 31290 m/sec, 12145781 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 Echo-PT-d03r05-CTLFireability-11 1838451 m, 28553 m/sec, 13242877 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 Echo-PT-d03r05-CTLFireability-11 1976215 m, 27552 m/sec, 14332073 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 Echo-PT-d03r05-CTLFireability-11 2113648 m, 27486 m/sec, 15420807 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 Echo-PT-d03r05-CTLFireability-11 2253601 m, 27990 m/sec, 16518064 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 Echo-PT-d03r05-CTLFireability-11 2402768 m, 29833 m/sec, 17617446 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 Echo-PT-d03r05-CTLFireability-11 2552258 m, 29898 m/sec, 18722256 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 Echo-PT-d03r05-CTLFireability-11 2688450 m, 27238 m/sec, 19800975 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 Echo-PT-d03r05-CTLFireability-11 2828013 m, 27912 m/sec, 20895228 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 Echo-PT-d03r05-CTLFireability-11 2967314 m, 27860 m/sec, 21998779 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 Echo-PT-d03r05-CTLFireability-11 3105652 m, 27667 m/sec, 23095064 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 Echo-PT-d03r05-CTLFireability-11 3245176 m, 27904 m/sec, 24199788 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 Echo-PT-d03r05-CTLFireability-11 3368468 m, 24658 m/sec, 25273198 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 Echo-PT-d03r05-CTLFireability-11 3486607 m, 23627 m/sec, 26319218 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 Echo-PT-d03r05-CTLFireability-11 3608072 m, 24293 m/sec, 27397428 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 Echo-PT-d03r05-CTLFireability-11 3727789 m, 23943 m/sec, 28464004 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 Echo-PT-d03r05-CTLFireability-11 3849463 m, 24334 m/sec, 29547408 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 Echo-PT-d03r05-CTLFireability-11 3981941 m, 26495 m/sec, 30622799 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 Echo-PT-d03r05-CTLFireability-11 4108020 m, 25215 m/sec, 31689207 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-11 4227157 m, 23827 m/sec, 32751962 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-11 4345549 m, 23678 m/sec, 33805266 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 Echo-PT-d03r05-CTLFireability-11 4466393 m, 24168 m/sec, 34873228 t fired, . Pages in use: 32 Visible: 13 36 (type EXCL) for Echo-PT-d03r05-CTLFireability-11 (memory limit exceeded) VALUE PRODUCED BY EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 Visible: 13 (type EXCL) for 32 Echo-PT-d03r05-CTLFireability-09 33 (type EXCL) for Echo-PT-d03r05-CTLFireability-09 : false 251 250 0.000000 1 (type EXCL) for 21 Echo-PT-d03r05-CTLFireability-07 30 (type EXCL) for Echo-PT-d03r05-CTLFireability-07 : false 7761 15770 0.000000 1 (type EXCL) for 15 Echo-PT-d03r05-CTLFireability-05 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 Echo-PT-d03r05-CTLFireability-05 163233 m, 32646 m/sec, 1134064 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 Echo-PT-d03r05-CTLFireability-05 308052 m, 28963 m/sec, 2261604 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 Echo-PT-d03r05-CTLFireability-05 452473 m, 28884 m/sec, 3405269 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 Echo-PT-d03r05-CTLFireability-05 599493 m, 29404 m/sec, 4560263 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 Echo-PT-d03r05-CTLFireability-05 745267 m, 29154 m/sec, 5712885 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 Echo-PT-d03r05-CTLFireability-05 890980 m, 29142 m/sec, 6866226 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 Echo-PT-d03r05-CTLFireability-05 1023871 m, 26578 m/sec, 8002954 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 Echo-PT-d03r05-CTLFireability-05 1149676 m, 25161 m/sec, 9124335 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 Echo-PT-d03r05-CTLFireability-05 1280154 m, 26095 m/sec, 10275206 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 Echo-PT-d03r05-CTLFireability-05 1408573 m, 25683 m/sec, 11418638 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 Echo-PT-d03r05-CTLFireability-05 1537282 m, 25741 m/sec, 12566473 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 Echo-PT-d03r05-CTLFireability-05 1678934 m, 28330 m/sec, 13704280 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 Echo-PT-d03r05-CTLFireability-05 1809552 m, 26123 m/sec, 14830994 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 Echo-PT-d03r05-CTLFireability-05 1936220 m, 25333 m/sec, 15950840 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 Echo-PT-d03r05-CTLFireability-05 2062296 m, 25215 m/sec, 17071062 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 Echo-PT-d03r05-CTLFireability-05 2188190 m, 25178 m/sec, 18193197 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 Echo-PT-d03r05-CTLFireability-05 2311905 m, 24743 m/sec, 19295001 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 Echo-PT-d03r05-CTLFireability-05 2453361 m, 28291 m/sec, 20433500 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 Echo-PT-d03r05-CTLFireability-05 2583457 m, 26019 m/sec, 21553938 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 Echo-PT-d03r05-CTLFireability-05 2708310 m, 24970 m/sec, 22661073 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 Echo-PT-d03r05-CTLFireability-05 2836031 m, 25544 m/sec, 23794407 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 Echo-PT-d03r05-CTLFireability-05 2962525 m, 25298 m/sec, 24922224 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 Echo-PT-d03r05-CTLFireability-05 3089664 m, 25427 m/sec, 26055767 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 Echo-PT-d03r05-CTLFireability-05 3216996 m, 25466 m/sec, 27188907 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 Echo-PT-d03r05-CTLFireability-05 3334501 m, 23501 m/sec, 28301887 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 Echo-PT-d03r05-CTLFireability-05 3444897 m, 22079 m/sec, 29394599 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 Echo-PT-d03r05-CTLFireability-05 3556134 m, 22247 m/sec, 30496419 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 Echo-PT-d03r05-CTLFireability-05 3668137 m, 22400 m/sec, 31606863 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 Echo-PT-d03r05-CTLFireability-05 3782282 m, 22829 m/sec, 32735064 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 Echo-PT-d03r05-CTLFireability-05 3896692 m, 22882 m/sec, 33839575 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 Echo-PT-d03r05-CTLFireability-05 4020568 m, 24775 m/sec, 34959335 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 Echo-PT-d03r05-CTLFireability-05 4135842 m, 23054 m/sec, 36076634 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-05 4246353 m, 22102 m/sec, 37170143 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-05 4356946 m, 22118 m/sec, 38263366 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 Echo-PT-d03r05-CTLFireability-05 4468160 m, 22242 m/sec, 39357087 t fired, . Pages in use: 32 Visible: 13 16 (type EXCL) for Echo-PT-d03r05-CTLFireability-05 (memory limit exceeded) VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 Visible: 13 (type EXCL) for 9 Echo-PT-d03r05-CTLFireability-03 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 Echo-PT-d03r05-CTLFireability-03 190735 m, 38147 m/sec, 1146062 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 Echo-PT-d03r05-CTLFireability-03 354941 m, 32841 m/sec, 2282215 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 Echo-PT-d03r05-CTLFireability-03 520137 m, 33039 m/sec, 3415498 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 Echo-PT-d03r05-CTLFireability-03 686530 m, 33278 m/sec, 4559219 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 Echo-PT-d03r05-CTLFireability-03 852546 m, 33203 m/sec, 5698868 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 Echo-PT-d03r05-CTLFireability-03 1005279 m, 30546 m/sec, 6828981 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 Echo-PT-d03r05-CTLFireability-03 1144520 m, 27848 m/sec, 7932118 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 Echo-PT-d03r05-CTLFireability-03 1288398 m, 28775 m/sec, 9060299 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 Echo-PT-d03r05-CTLFireability-03 1431265 m, 28573 m/sec, 10191369 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 Echo-PT-d03r05-CTLFireability-03 1579847 m, 29716 m/sec, 11324972 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 Echo-PT-d03r05-CTLFireability-03 1738574 m, 31745 m/sec, 12454926 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 Echo-PT-d03r05-CTLFireability-03 1881498 m, 28584 m/sec, 13584465 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 Echo-PT-d03r05-CTLFireability-03 2023261 m, 28352 m/sec, 14708945 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 Echo-PT-d03r05-CTLFireability-03 2167298 m, 28807 m/sec, 15837989 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 Echo-PT-d03r05-CTLFireability-03 2310169 m, 28574 m/sec, 16969125 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 Echo-PT-d03r05-CTLFireability-03 2470437 m, 32053 m/sec, 18102268 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 Echo-PT-d03r05-CTLFireability-03 2616614 m, 29235 m/sec, 19227085 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 Echo-PT-d03r05-CTLFireability-03 2756891 m, 28055 m/sec, 20335174 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 Echo-PT-d03r05-CTLFireability-03 2898307 m, 28283 m/sec, 21456691 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 Echo-PT-d03r05-CTLFireability-03 3042179 m, 28774 m/sec, 22585499 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 Echo-PT-d03r05-CTLFireability-03 3186589 m, 28882 m/sec, 23720927 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 Echo-PT-d03r05-CTLFireability-03 3320976 m, 26877 m/sec, 24845407 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 Echo-PT-d03r05-CTLFireability-03 3444139 m, 24632 m/sec, 25942752 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 Echo-PT-d03r05-CTLFireability-03 3568039 m, 24780 m/sec, 27048174 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 Echo-PT-d03r05-CTLFireability-03 3695414 m, 25475 m/sec, 28175906 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 Echo-PT-d03r05-CTLFireability-03 3823105 m, 25538 m/sec, 29309524 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 Echo-PT-d03r05-CTLFireability-03 3958891 m, 27157 m/sec, 30437282 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 Echo-PT-d03r05-CTLFireability-03 4092616 m, 26745 m/sec, 31550306 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-03 4215271 m, 24531 m/sec, 32644834 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-03 4338314 m, 24608 m/sec, 33740982 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 Echo-PT-d03r05-CTLFireability-03 4462252 m, 24787 m/sec, 34838316 t fired, . Pages in use: 32 Visible: 13 10 (type EXCL) for Echo-PT-d03r05-CTLFireability-03 (memory limit exceeded) VALUE PRODUCED BY DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 Visible: 13 (type EXCL) for 3 Echo-PT-d03r05-CTLFireability-01 4 (type EXCL) for Echo-PT-d03r05-CTLFireability-01 : false 251 254 0.000000 1 (type EXCL) for 0 Echo-PT-d03r05-CTLFireability-00 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 Echo-PT-d03r05-CTLFireability-00 189853 m, 37970 m/sec, 1139782 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 Echo-PT-d03r05-CTLFireability-00 352421 m, 32513 m/sec, 2264025 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 Echo-PT-d03r05-CTLFireability-00 521062 m, 33728 m/sec, 3421769 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 Echo-PT-d03r05-CTLFireability-00 688954 m, 33578 m/sec, 4575610 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 Echo-PT-d03r05-CTLFireability-00 857737 m, 33756 m/sec, 5734793 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 Echo-PT-d03r05-CTLFireability-00 1012079 m, 30868 m/sec, 6885140 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 Echo-PT-d03r05-CTLFireability-00 1153930 m, 28370 m/sec, 8003629 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 Echo-PT-d03r05-CTLFireability-00 1298986 m, 29011 m/sec, 9145364 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 Echo-PT-d03r05-CTLFireability-00 1442544 m, 28711 m/sec, 10282083 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 Echo-PT-d03r05-CTLFireability-00 1594516 m, 30394 m/sec, 11426555 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 Echo-PT-d03r05-CTLFireability-00 1752518 m, 31600 m/sec, 12565222 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 Echo-PT-d03r05-CTLFireability-00 1894455 m, 28387 m/sec, 13688660 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 Echo-PT-d03r05-CTLFireability-00 2036660 m, 28441 m/sec, 14807204 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 Echo-PT-d03r05-CTLFireability-00 2179061 m, 28480 m/sec, 15932738 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 Echo-PT-d03r05-CTLFireability-00 2320267 m, 28241 m/sec, 17049813 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 Echo-PT-d03r05-CTLFireability-00 2483292 m, 32605 m/sec, 18197658 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 Echo-PT-d03r05-CTLFireability-00 2629823 m, 29306 m/sec, 19330684 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 Echo-PT-d03r05-CTLFireability-00 2771191 m, 28273 m/sec, 20450462 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 Echo-PT-d03r05-CTLFireability-00 2915608 m, 28883 m/sec, 21585910 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 Echo-PT-d03r05-CTLFireability-00 3060533 m, 28985 m/sec, 22731992 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 Echo-PT-d03r05-CTLFireability-00 3204962 m, 28885 m/sec, 23871503 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 Echo-PT-d03r05-CTLFireability-00 3336623 m, 26332 m/sec, 24987064 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 Echo-PT-d03r05-CTLFireability-00 3459360 m, 24547 m/sec, 26080529 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 Echo-PT-d03r05-CTLFireability-00 3584902 m, 25108 m/sec, 27193362 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 Echo-PT-d03r05-CTLFireability-00 3711871 m, 25393 m/sec, 28320307 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 Echo-PT-d03r05-CTLFireability-00 3839614 m, 25548 m/sec, 29459015 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 Echo-PT-d03r05-CTLFireability-00 3977014 m, 27480 m/sec, 30585548 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 Echo-PT-d03r05-CTLFireability-00 4107738 m, 26144 m/sec, 31686508 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-00 4228901 m, 24232 m/sec, 32768193 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-00 4353422 m, 24904 m/sec, 33877731 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 Echo-PT-d03r05-CTLFireability-00 4479970 m, 25309 m/sec, 34994428 t fired, . Pages in use: 32 Visible: 13 1 (type EXCL) for Echo-PT-d03r05-CTLFireability-00 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 EFEG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 Visible: 13 (type EXCL) for 38 Echo-PT-d03r05-CTLFireability-12 39 (type EXCL) for Echo-PT-d03r05-CTLFireability-12 : true 250 249 0.000000 1 (type EXCL) for 6 Echo-PT-d03r05-CTLFireability-02 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 Echo-PT-d03r05-CTLFireability-02 375922 m, 75184 m/sec, 750276 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 Echo-PT-d03r05-CTLFireability-02 704953 m, 65806 m/sec, 1521886 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 Echo-PT-d03r05-CTLFireability-02 1027042 m, 64417 m/sec, 2292146 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 Echo-PT-d03r05-CTLFireability-02 1343758 m, 63343 m/sec, 3053764 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 Echo-PT-d03r05-CTLFireability-02 1663644 m, 63977 m/sec, 3838384 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 Echo-PT-d03r05-CTLFireability-02 1951671 m, 57605 m/sec, 4624450 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 Echo-PT-d03r05-CTLFireability-02 2226698 m, 55005 m/sec, 5410204 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 Echo-PT-d03r05-CTLFireability-02 2505203 m, 55701 m/sec, 6189785 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 Echo-PT-d03r05-CTLFireability-02 2788535 m, 56666 m/sec, 6963948 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 Echo-PT-d03r05-CTLFireability-02 3072787 m, 56850 m/sec, 7746439 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 Echo-PT-d03r05-CTLFireability-02 3359401 m, 57322 m/sec, 8523058 t fired, . Pages in use: 32 Visible: 13 47 (type EXCL) for Echo-PT-d03r05-CTLFireability-02 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 Visible: 13 (type EXCL) for 18 Echo-PT-d03r05-CTLFireability-06 19 (type EXCL) for Echo-PT-d03r05-CTLFireability-06 : true 250 249 0.000000 1 (type EXCL) for 44 Echo-PT-d03r05-CTLFireability-15 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 Echo-PT-d03r05-CTLFireability-15 147874 m, 29574 m/sec, 1172302 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 Echo-PT-d03r05-CTLFireability-15 280637 m, 26552 m/sec, 2328527 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 Echo-PT-d03r05-CTLFireability-15 410031 m, 25878 m/sec, 3476362 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 Echo-PT-d03r05-CTLFireability-15 540495 m, 26092 m/sec, 4638825 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 Echo-PT-d03r05-CTLFireability-15 670415 m, 25984 m/sec, 5796938 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 Echo-PT-d03r05-CTLFireability-15 802354 m, 26387 m/sec, 6953510 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 Echo-PT-d03r05-CTLFireability-15 931675 m, 25864 m/sec, 8130721 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 Echo-PT-d03r05-CTLFireability-15 1051789 m, 24022 m/sec, 9304052 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 Echo-PT-d03r05-CTLFireability-15 1169275 m, 23497 m/sec, 10459228 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 Echo-PT-d03r05-CTLFireability-15 1288632 m, 23871 m/sec, 11640449 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 Echo-PT-d03r05-CTLFireability-15 1406169 m, 23507 m/sec, 12803460 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 Echo-PT-d03r05-CTLFireability-15 1523296 m, 23425 m/sec, 13964574 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 Echo-PT-d03r05-CTLFireability-15 1650669 m, 25474 m/sec, 15126417 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 Echo-PT-d03r05-CTLFireability-15 1773283 m, 24522 m/sec, 16278873 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 Echo-PT-d03r05-CTLFireability-15 1888341 m, 23011 m/sec, 17418723 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 Echo-PT-d03r05-CTLFireability-15 2003305 m, 22992 m/sec, 18557420 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 Echo-PT-d03r05-CTLFireability-15 2118426 m, 23024 m/sec, 19695955 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 Echo-PT-d03r05-CTLFireability-15 2232329 m, 22780 m/sec, 20820808 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 Echo-PT-d03r05-CTLFireability-15 2347495 m, 23033 m/sec, 21930596 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 Echo-PT-d03r05-CTLFireability-15 2475616 m, 25624 m/sec, 23094018 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 Echo-PT-d03r05-CTLFireability-15 2592652 m, 23407 m/sec, 24231230 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 Echo-PT-d03r05-CTLFireability-15 2705958 m, 22661 m/sec, 25350285 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 Echo-PT-d03r05-CTLFireability-15 2821089 m, 23026 m/sec, 26484485 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 Echo-PT-d03r05-CTLFireability-15 2933439 m, 22470 m/sec, 27595829 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 Echo-PT-d03r05-CTLFireability-15 3047013 m, 22714 m/sec, 28719124 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 Echo-PT-d03r05-CTLFireability-15 3161361 m, 22869 m/sec, 29843648 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 Echo-PT-d03r05-CTLFireability-15 3270648 m, 21857 m/sec, 30953290 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 Echo-PT-d03r05-CTLFireability-15 3370380 m, 19946 m/sec, 32033742 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 Echo-PT-d03r05-CTLFireability-15 3468107 m, 19545 m/sec, 33097642 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 Echo-PT-d03r05-CTLFireability-15 3567554 m, 19889 m/sec, 34181746 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 Echo-PT-d03r05-CTLFireability-15 3668908 m, 20270 m/sec, 35285227 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 Echo-PT-d03r05-CTLFireability-15 3770336 m, 20285 m/sec, 36389415 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 Echo-PT-d03r05-CTLFireability-15 3871531 m, 20239 m/sec, 37491923 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 Echo-PT-d03r05-CTLFireability-15 3983457 m, 22385 m/sec, 38604798 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 Echo-PT-d03r05-CTLFireability-15 4088588 m, 21026 m/sec, 39694026 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 Echo-PT-d03r05-CTLFireability-15 4188444 m, 19971 m/sec, 40781445 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 Echo-PT-d03r05-CTLFireability-15 4287011 m, 19713 m/sec, 41855117 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 Echo-PT-d03r05-CTLFireability-15 4386966 m, 19991 m/sec, 42944217 t fired, . Pages in use: 32 Visible: 13 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 Echo-PT-d03r05-CTLFireability-15 4487426 m, 20092 m/sec, 44038384 t fired, . Pages in use: 32 Visible: 13 45 (type EXCL) for Echo-PT-d03r05-CTLFireability-15 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker DISJ false DISJ CTL false CTL model checker EFEG true state space /EFEG EXEF true state space /EXEF IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 Visible: 13 no open tasks 13 VALUE PRODUCED BY CTL unknown AGGR CTL false CTL model checker SP ACTL unknown AGGR CTL unknown AGGR CTL unknown AGGR CTL unknown AGGR CTL true CTL model checker DISJ false DISJ CTL false CTL model checker CTL unknown AGGR EFEG true state space /EFEG EXEF true state space /EXEF CTL unknown AGGR Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Echo-PT-d03r05"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Echo-PT-d03r05, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852500090"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Echo-PT-d03r05.tgz
mv Echo-PT-d03r05 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;