Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852400042.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ERK-PT-100000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852400042
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 404K
-rw-r--r-- 1 mcc users 5.1K Feb 26 16:46 CTLCardinality.txt
-rw-r--r-- 1 mcc users 44K Feb 26 16:46 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 26 16:45 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 16:45 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.7K Feb 26 16:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 86K Feb 26 16:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.6K Feb 26 16:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 26 16:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 6.7K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ERK-PT-100000-CTLFireability-00
FORMULA_NAME ERK-PT-100000-CTLFireability-01
FORMULA_NAME ERK-PT-100000-CTLFireability-02
FORMULA_NAME ERK-PT-100000-CTLFireability-03
FORMULA_NAME ERK-PT-100000-CTLFireability-04
FORMULA_NAME ERK-PT-100000-CTLFireability-05
FORMULA_NAME ERK-PT-100000-CTLFireability-06
FORMULA_NAME ERK-PT-100000-CTLFireability-07
FORMULA_NAME ERK-PT-100000-CTLFireability-08
FORMULA_NAME ERK-PT-100000-CTLFireability-09
FORMULA_NAME ERK-PT-100000-CTLFireability-10
FORMULA_NAME ERK-PT-100000-CTLFireability-11
FORMULA_NAME ERK-PT-100000-CTLFireability-12
FORMULA_NAME ERK-PT-100000-CTLFireability-13
FORMULA_NAME ERK-PT-100000-CTLFireability-14
FORMULA_NAME ERK-PT-100000-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678433429134

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ERK-PT-100000
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 07:30:30] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 07:30:30] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 07:30:30] [INFO ] Load time of PNML (sax parser for PT used): 19 ms
[2023-03-10 07:30:30] [INFO ] Transformed 11 places.
[2023-03-10 07:30:30] [INFO ] Transformed 11 transitions.
[2023-03-10 07:30:30] [INFO ] Parsed PT model containing 11 places and 11 transitions and 34 arcs in 73 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Initial state reduction rules removed 3 formulas.
FORMULA ERK-PT-100000-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ERK-PT-100000-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ERK-PT-100000-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 11 out of 11 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 8 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
// Phase 1: matrix 11 rows 11 cols
[2023-03-10 07:30:30] [INFO ] Computed 5 place invariants in 5 ms
[2023-03-10 07:30:31] [INFO ] Implicit Places using invariants in 567 ms returned []
[2023-03-10 07:30:31] [INFO ] Invariant cache hit.
[2023-03-10 07:30:31] [INFO ] Implicit Places using invariants and state equation in 33 ms returned []
Implicit Place search using SMT with State Equation took 623 ms to find 0 implicit places.
[2023-03-10 07:30:31] [INFO ] Invariant cache hit.
[2023-03-10 07:30:31] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 660 ms. Remains : 11/11 places, 11/11 transitions.
Support contains 11 out of 11 places after structural reductions.
[2023-03-10 07:30:31] [INFO ] Flatten gal took : 12 ms
[2023-03-10 07:30:31] [INFO ] Flatten gal took : 4 ms
[2023-03-10 07:30:31] [INFO ] Input system was already deterministic with 11 transitions.
Incomplete random walk after 100001 steps, including 0 resets, run finished after 60 ms. (steps per millisecond=1666 ) properties (out of 15) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 88 ms. (steps per millisecond=113 ) properties (out of 13) seen :9
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 73 ms. (steps per millisecond=137 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-10 07:30:31] [INFO ] Invariant cache hit.
[2023-03-10 07:30:31] [INFO ] [Real]Absence check using 5 positive place invariants in 10 ms returned sat
[2023-03-10 07:30:31] [INFO ] After 62ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-10 07:30:32] [INFO ] [Nat]Absence check using 5 positive place invariants in 1 ms returned sat
[2023-03-10 07:30:32] [INFO ] After 17ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-10 07:30:32] [INFO ] After 37ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 10 ms.
[2023-03-10 07:30:32] [INFO ] After 102ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Fused 4 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 6001 ms.
Support contains 10 out of 11 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 11 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 11 ms. Remains : 11/11 places, 11/11 transitions.
Incomplete random walk after 100001 steps, including 0 resets, run finished after 18 ms. (steps per millisecond=5555 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 4) seen :0
Interrupted probabilistic random walk after 330881 steps, run timeout after 3001 ms. (steps per millisecond=110 ) properties seen :{}
Probabilistic random walk after 330881 steps, saw 221010 distinct states, run finished after 3002 ms. (steps per millisecond=110 ) properties seen :0
Running SMT prover for 4 properties.
[2023-03-10 07:30:41] [INFO ] Invariant cache hit.
[2023-03-10 07:30:41] [INFO ] [Real]Absence check using 5 positive place invariants in 1 ms returned sat
[2023-03-10 07:30:41] [INFO ] After 31ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-10 07:30:41] [INFO ] [Nat]Absence check using 5 positive place invariants in 1 ms returned sat
[2023-03-10 07:30:41] [INFO ] After 12ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-10 07:30:41] [INFO ] After 23ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 8 ms.
[2023-03-10 07:30:41] [INFO ] After 63ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Fused 4 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 6000 ms.
Support contains 10 out of 11 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 1 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
[2023-03-10 07:30:47] [INFO ] Invariant cache hit.
[2023-03-10 07:30:47] [INFO ] Implicit Places using invariants in 19 ms returned []
[2023-03-10 07:30:47] [INFO ] Invariant cache hit.
[2023-03-10 07:30:47] [INFO ] Implicit Places using invariants and state equation in 21 ms returned []
Implicit Place search using SMT with State Equation took 42 ms to find 0 implicit places.
[2023-03-10 07:30:47] [INFO ] Redundant transitions in 0 ms returned []
[2023-03-10 07:30:47] [INFO ] Invariant cache hit.
[2023-03-10 07:30:47] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 81 ms. Remains : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 1 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Running SMT prover for 4 properties.
[2023-03-10 07:30:47] [INFO ] Invariant cache hit.
[2023-03-10 07:30:47] [INFO ] [Real]Absence check using 5 positive place invariants in 1 ms returned sat
[2023-03-10 07:30:47] [INFO ] After 25ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-10 07:30:47] [INFO ] [Nat]Absence check using 5 positive place invariants in 2 ms returned sat
[2023-03-10 07:30:47] [INFO ] After 12ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-10 07:30:47] [INFO ] After 23ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 9 ms.
[2023-03-10 07:30:47] [INFO ] After 84ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 4 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 6 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 2 Pre rules applied. Total rules applied 0 place count 11 transition count 9
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 6 place count 7 transition count 9
Applied a total of 6 rules in 4 ms. Remains 7 /11 variables (removed 4) and now considering 9/11 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 7/11 places, 9/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 2 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 1 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 1 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 11 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 9 transition count 10
Applied a total of 3 rules in 1 ms. Remains 9 /11 variables (removed 2) and now considering 10/11 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 9/11 places, 10/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 11 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 9 transition count 10
Applied a total of 3 rules in 1 ms. Remains 9 /11 variables (removed 2) and now considering 10/11 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/11 places, 10/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 0 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 0 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 2 Pre rules applied. Total rules applied 0 place count 11 transition count 9
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 6 place count 7 transition count 9
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 7 place count 7 transition count 9
Applied a total of 7 rules in 2 ms. Remains 7 /11 variables (removed 4) and now considering 9/11 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 7/11 places, 9/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 6 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 0 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Input system was already deterministic with 11 transitions.
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:30:47] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 1 ms.
[2023-03-10 07:30:47] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 11 places, 11 transitions and 34 arcs took 0 ms.
Total runtime 17186 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ERK-PT-100000
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA ERK-PT-100000-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ERK-PT-100000-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ERK-PT-100000-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ERK-PT-100000-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ERK-PT-100000-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678433534043

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: FINISHED task # 28 (type EXCL) for ERK-PT-100000-CTLFireability-11
lola: result : true
lola: markings : 200009
lola: fired transitions : 600024
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 ERK-PT-100000-CTLFireability-08
lola: time limit : 1772 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-100000-CTLFireability-01: CTL false CTL model checker
ERK-PT-100000-CTLFireability-03: CTL true CTL model checker
ERK-PT-100000-CTLFireability-11: EGEF true CTL model checker
ERK-PT-100000-CTLFireability-12: CONJ false CONJ
ERK-PT-100000-CTLFireability-13: DISJ false DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-100000-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ERK-PT-100000-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ERK-PT-100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 4/1772 12/32 ERK-PT-100000-CTLFireability-08 2895468 m, 579093 m/sec, 9364391 t fired, .

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ERK-PT-100000-CTLFireability-01: CTL false CTL model checker
ERK-PT-100000-CTLFireability-03: CTL true CTL model checker
ERK-PT-100000-CTLFireability-11: EGEF true CTL model checker
ERK-PT-100000-CTLFireability-12: CONJ false CONJ
ERK-PT-100000-CTLFireability-13: DISJ false DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-100000-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ERK-PT-100000-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
ERK-PT-100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 9/1772 23/32 ERK-PT-100000-CTLFireability-08 5634543 m, 547815 m/sec, 18942585 t fired, .

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ERK-PT-100000-CTLFireability-01: CTL false CTL model checker
ERK-PT-100000-CTLFireability-03: CTL true CTL model checker
ERK-PT-100000-CTLFireability-11: EGEF true CTL model checker
ERK-PT-100000-CTLFireability-12: CONJ false CONJ
ERK-PT-100000-CTLFireability-13: DISJ false DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-100000-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ERK-PT-100000-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 22 (type EXCL) for 21 ERK-PT-100000-CTLFireability-07
lola: time limit : 3530 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-100000-CTLFireability-01: CTL false CTL model checker
ERK-PT-100000-CTLFireability-03: CTL true CTL model checker
ERK-PT-100000-CTLFireability-11: EGEF true CTL model checker
ERK-PT-100000-CTLFireability-12: CONJ false CONJ
ERK-PT-100000-CTLFireability-13: DISJ false DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-100000-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
ERK-PT-100000-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/3530 13/32 ERK-PT-100000-CTLFireability-07 3039202 m, 607840 m/sec, 11392581 t fired, .

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ERK-PT-100000-CTLFireability-01: CTL false CTL model checker
ERK-PT-100000-CTLFireability-03: CTL true CTL model checker
ERK-PT-100000-CTLFireability-11: EGEF true CTL model checker
ERK-PT-100000-CTLFireability-12: CONJ false CONJ
ERK-PT-100000-CTLFireability-13: DISJ false DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-100000-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
ERK-PT-100000-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/3530 25/32 ERK-PT-100000-CTLFireability-07 6020319 m, 596223 m/sec, 21828554 t fired, .

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lola: CANCELED task # 22 (type EXCL) for ERK-PT-100000-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-100000-CTLFireability-01: CTL false CTL model checker
ERK-PT-100000-CTLFireability-03: CTL true CTL model checker
ERK-PT-100000-CTLFireability-11: EGEF true CTL model checker
ERK-PT-100000-CTLFireability-12: CONJ false CONJ
ERK-PT-100000-CTLFireability-13: DISJ false DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-100000-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
ERK-PT-100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-100000-CTLFireability-00: EFAG unknown AGGR
ERK-PT-100000-CTLFireability-01: CTL false CTL model checker
ERK-PT-100000-CTLFireability-02: CTL unknown AGGR
ERK-PT-100000-CTLFireability-03: CTL true CTL model checker
ERK-PT-100000-CTLFireability-04: CTL unknown AGGR
ERK-PT-100000-CTLFireability-05: CTL unknown AGGR
ERK-PT-100000-CTLFireability-06: CTL unknown AGGR
ERK-PT-100000-CTLFireability-07: CTL unknown AGGR
ERK-PT-100000-CTLFireability-08: CTL unknown AGGR
ERK-PT-100000-CTLFireability-11: EGEF true CTL model checker
ERK-PT-100000-CTLFireability-12: CONJ false CONJ
ERK-PT-100000-CTLFireability-13: DISJ false DISJ
ERK-PT-100000-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ERK-PT-100000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ERK-PT-100000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852400042"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ERK-PT-100000.tgz
mv ERK-PT-100000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;