About the Execution of LoLa+red for ERK-PT-010000
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
4550.592 | 75066.00 | 71474.00 | 602.50 | ??F???TTT?FFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852400034.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ERK-PT-010000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852400034
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 588K
-rw-r--r-- 1 mcc users 9.7K Feb 26 16:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 103K Feb 26 16:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.3K Feb 26 16:44 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K Feb 26 16:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 19K Feb 26 16:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 189K Feb 26 16:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 16:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 100K Feb 26 16:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 6.7K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ERK-PT-010000-CTLFireability-00
FORMULA_NAME ERK-PT-010000-CTLFireability-01
FORMULA_NAME ERK-PT-010000-CTLFireability-02
FORMULA_NAME ERK-PT-010000-CTLFireability-03
FORMULA_NAME ERK-PT-010000-CTLFireability-04
FORMULA_NAME ERK-PT-010000-CTLFireability-05
FORMULA_NAME ERK-PT-010000-CTLFireability-06
FORMULA_NAME ERK-PT-010000-CTLFireability-07
FORMULA_NAME ERK-PT-010000-CTLFireability-08
FORMULA_NAME ERK-PT-010000-CTLFireability-09
FORMULA_NAME ERK-PT-010000-CTLFireability-10
FORMULA_NAME ERK-PT-010000-CTLFireability-11
FORMULA_NAME ERK-PT-010000-CTLFireability-12
FORMULA_NAME ERK-PT-010000-CTLFireability-13
FORMULA_NAME ERK-PT-010000-CTLFireability-14
FORMULA_NAME ERK-PT-010000-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678433321072
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ERK-PT-010000
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 07:28:42] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 07:28:42] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 07:28:42] [INFO ] Load time of PNML (sax parser for PT used): 19 ms
[2023-03-10 07:28:42] [INFO ] Transformed 11 places.
[2023-03-10 07:28:42] [INFO ] Transformed 11 transitions.
[2023-03-10 07:28:42] [INFO ] Parsed PT model containing 11 places and 11 transitions and 34 arcs in 72 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Initial state reduction rules removed 3 formulas.
FORMULA ERK-PT-010000-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ERK-PT-010000-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ERK-PT-010000-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 11 out of 11 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 8 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
// Phase 1: matrix 11 rows 11 cols
[2023-03-10 07:28:42] [INFO ] Computed 5 place invariants in 5 ms
[2023-03-10 07:28:42] [INFO ] Implicit Places using invariants in 127 ms returned []
[2023-03-10 07:28:42] [INFO ] Invariant cache hit.
[2023-03-10 07:28:42] [INFO ] Implicit Places using invariants and state equation in 57 ms returned []
Implicit Place search using SMT with State Equation took 207 ms to find 0 implicit places.
[2023-03-10 07:28:42] [INFO ] Invariant cache hit.
[2023-03-10 07:28:42] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 245 ms. Remains : 11/11 places, 11/11 transitions.
Support contains 11 out of 11 places after structural reductions.
[2023-03-10 07:28:43] [INFO ] Flatten gal took : 12 ms
[2023-03-10 07:28:43] [INFO ] Flatten gal took : 3 ms
[2023-03-10 07:28:43] [INFO ] Input system was already deterministic with 11 transitions.
Incomplete random walk after 10001 steps, including 0 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 20) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 19) seen :12
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-10 07:28:43] [INFO ] Invariant cache hit.
[2023-03-10 07:28:43] [INFO ] [Real]Absence check using 5 positive place invariants in 1 ms returned sat
[2023-03-10 07:28:43] [INFO ] After 57ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:7
[2023-03-10 07:28:43] [INFO ] [Nat]Absence check using 5 positive place invariants in 1 ms returned sat
[2023-03-10 07:28:43] [INFO ] After 20ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :7
[2023-03-10 07:28:43] [INFO ] After 36ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :7
Attempting to minimize the solution found.
Minimization took 18 ms.
[2023-03-10 07:28:43] [INFO ] After 102ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :7
Fused 7 Parikh solutions to 6 different solutions.
Finished Parikh walk after 40002 steps, including 0 resets, run visited all 1 properties in 70 ms. (steps per millisecond=571 )
Parikh walk visited 7 properties in 1171 ms.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 1 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 1 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 1 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 11 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 9 transition count 10
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 9 transition count 10
Applied a total of 4 rules in 6 ms. Remains 9 /11 variables (removed 2) and now considering 10/11 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 9/11 places, 10/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 0 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 11 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 9 transition count 10
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 9 transition count 10
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 5 place count 9 transition count 9
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 5 place count 9 transition count 8
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 7 place count 8 transition count 8
Applied a total of 7 rules in 2 ms. Remains 8 /11 variables (removed 3) and now considering 8/11 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 8/11 places, 8/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 0 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 0 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 1 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 2 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 0 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 0 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 11 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 9 transition count 10
Applied a total of 3 rules in 1 ms. Remains 9 /11 variables (removed 2) and now considering 10/11 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/11 places, 10/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 1 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 11/11 places, 11/11 transitions.
Applied a total of 0 rules in 0 ms. Remains 11 /11 variables (removed 0) and now considering 11/11 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 11/11 places, 11/11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Input system was already deterministic with 11 transitions.
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Flatten gal took : 1 ms
[2023-03-10 07:28:44] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-10 07:28:44] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 11 places, 11 transitions and 34 arcs took 1 ms.
Total runtime 2485 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ERK-PT-010000
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA ERK-PT-010000-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ERK-PT-010000-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ERK-PT-010000-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ERK-PT-010000-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ERK-PT-010000-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ERK-PT-010000-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ERK-PT-010000-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678433396138
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 7 (type EXCL) for 6 ERK-PT-010000-CTLFireability-02
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 7 (type EXCL) for ERK-PT-010000-CTLFireability-02
lola: result : false
lola: markings : 59999
lola: fired transitions : 89997
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 ERK-PT-010000-CTLFireability-13
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for ERK-PT-010000-CTLFireability-13
lola: result : false
lola: markings : 30004
lola: fired transitions : 30003
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 ERK-PT-010000-CTLFireability-08
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for ERK-PT-010000-CTLFireability-08
lola: result : true
lola: markings : 30003
lola: fired transitions : 30005
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 ERK-PT-010000-CTLFireability-07
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for ERK-PT-010000-CTLFireability-07
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 ERK-PT-010000-CTLFireability-05
lola: time limit : 399 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 4/399 13/32 ERK-PT-010000-CTLFireability-05 3077642 m, 615528 m/sec, 8700276 t fired, .
Time elapsed: 5 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 9/399 25/32 ERK-PT-010000-CTLFireability-05 6099256 m, 604322 m/sec, 17258275 t fired, .
Time elapsed: 10 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 16 (type EXCL) for ERK-PT-010000-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 13 (type EXCL) for 12 ERK-PT-010000-CTLFireability-04
lola: time limit : 448 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/448 19/32 ERK-PT-010000-CTLFireability-04 4534951 m, 906990 m/sec, 11326317 t fired, .
Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 13 (type EXCL) for ERK-PT-010000-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 4 (type EXCL) for 3 ERK-PT-010000-CTLFireability-01
lola: time limit : 510 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/510 17/32 ERK-PT-010000-CTLFireability-01 4182921 m, 836584 m/sec, 10445842 t fired, .
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 4 (type EXCL) for ERK-PT-010000-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 1 (type EXCL) for 0 ERK-PT-010000-CTLFireability-00
lola: time limit : 594 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ERK-PT-010000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/594 13/32 ERK-PT-010000-CTLFireability-00 3114358 m, 622871 m/sec, 10927990 t fired, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ERK-PT-010000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/594 24/32 ERK-PT-010000-CTLFireability-00 5945744 m, 566277 m/sec, 20836883 t fired, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 1 (type EXCL) for ERK-PT-010000-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-06: EG 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ERK-PT-010000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 19 (type EXCL) for 18 ERK-PT-010000-CTLFireability-06
lola: time limit : 710 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for ERK-PT-010000-CTLFireability-06
lola: result : true
lola: markings : 10004
lola: fired transitions : 10004
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 ERK-PT-010000-CTLFireability-15
lola: time limit : 887 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for ERK-PT-010000-CTLFireability-15
lola: result : true
lola: markings : 99995
lola: fired transitions : 219991
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 ERK-PT-010000-CTLFireability-12
lola: time limit : 1183 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for ERK-PT-010000-CTLFireability-12
lola: result : false
lola: markings : 20002
lola: fired transitions : 40007
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 ERK-PT-010000-CTLFireability-03
lola: time limit : 1774 sec
lola: memory limit: 32 pages
lola: CANCELED task # 10 (type EXCL) for ERK-PT-010000-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-06: EG true state space / EG
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-12: CTL false CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
ERK-PT-010000-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 28 (type EXCL) for 27 ERK-PT-010000-CTLFireability-09
lola: time limit : 3545 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-06: EG true state space / EG
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-12: CTL false CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
ERK-PT-010000-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/3545 16/32 ERK-PT-010000-CTLFireability-09 3925651 m, 785130 m/sec, 11087642 t fired, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-06: EG true state space / EG
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-12: CTL false CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
ERK-PT-010000-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/3545 31/32 ERK-PT-010000-CTLFireability-09 7677696 m, 750409 m/sec, 21715208 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 28 (type EXCL) for ERK-PT-010000-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-06: EG true state space / EG
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-12: CTL false CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
ERK-PT-010000-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ERK-PT-010000-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ERK-PT-010000-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: Portfolio finished: no open tasks 13
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ERK-PT-010000-CTLFireability-00: CTL unknown AGGR
ERK-PT-010000-CTLFireability-01: CTL unknown AGGR
ERK-PT-010000-CTLFireability-02: CTL false CTL model checker
ERK-PT-010000-CTLFireability-03: CTL unknown AGGR
ERK-PT-010000-CTLFireability-04: CTL unknown AGGR
ERK-PT-010000-CTLFireability-05: CTL unknown AGGR
ERK-PT-010000-CTLFireability-06: EG true state space / EG
ERK-PT-010000-CTLFireability-07: CTL true CTL model checker
ERK-PT-010000-CTLFireability-08: CTL true CTL model checker
ERK-PT-010000-CTLFireability-09: CTL unknown AGGR
ERK-PT-010000-CTLFireability-12: CTL false CTL model checker
ERK-PT-010000-CTLFireability-13: CTL false CTL model checker
ERK-PT-010000-CTLFireability-15: CTL true CTL model checker
Time elapsed: 70 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ERK-PT-010000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ERK-PT-010000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852400034"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ERK-PT-010000.tgz
mv ERK-PT-010000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;