About the Execution of LoLA for FamilyReunion-PT-L00020M0002C001P001G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4762.508 | 988797.00 | 990568.00 | 3003.90 | ?F??TTF?FFF???FT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851700404.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is FamilyReunion-PT-L00020M0002C001P001G001, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851700404
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.1M
-rw-r--r-- 1 mcc users 29K Feb 26 11:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 214K Feb 26 11:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 74K Feb 26 11:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 290K Feb 26 11:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 16K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 32K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 100K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 62K Feb 26 11:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 423K Feb 26 11:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113K Feb 26 11:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 417K Feb 26 11:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 9.3K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.3M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-00
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-01
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-02
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-03
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-04
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-05
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-06
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-07
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-08
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-09
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-10
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-11
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-12
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-13
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-14
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1678463176816
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-PT-L00020M0002C001P001G001
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT FamilyReunion-PT-L00020M0002C001P001G001
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678464165613
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 52 (type SKEL/SRCH) for 3 FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: FINISHED task # 52 (type SKEL/SRCH) for FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-01
lola: result : false
lola: markings : 1214
lola: fired transitions : 1214
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 1 (type EXCL) for 0 FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-00
lola: time limit : 208 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-01: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-04: LTL true LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-05: LTL true LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-08: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-09: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-10: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-15: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-00: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 LTL EXCL 395/752 32/32 FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-11 3782107 m, 8566 m/sec, 29259834 t fired, .
Time elapsed: 984 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 38 (type EXCL) for FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-01: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-04: LTL true LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-05: LTL true LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-08: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-09: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-10: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-15: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-00: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-02: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-12: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 989 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 47 (type EXCL) for 46 FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-14
lola: time limit : 870 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-14
lola: result : false
lola: markings : 457
lola: fired transitions : 457
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 18 FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-06
lola: time limit : 1305 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-06
lola: result : false
lola: markings : 519
lola: fired transitions : 519
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-00: LTL unknown AGGR
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-01: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-02: LTL unknown AGGR
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-03: LTL unknown AGGR
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-04: LTL true LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-05: LTL true LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-06: CONJ false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-07: LTL unknown AGGR
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-08: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-09: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-10: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-11: LTL unknown AGGR
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-12: LTL unknown AGGR
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-13: LTL unknown AGGR
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-14: LTL false LTL model checker
FamilyReunion-PT-L00020M0002C001P001G001-LTLFireability-15: LTL true LTL model checker
Time elapsed: 989 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00020M0002C001P001G001"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is FamilyReunion-PT-L00020M0002C001P001G001, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851700404"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00020M0002C001P001G001.tgz
mv FamilyReunion-PT-L00020M0002C001P001G001 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;