About the Execution of LoLA for FamilyReunion-COL-L00100M0010C005P005G002
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16223.747 | 1014540.00 | 2361011.00 | 22116.40 | TFF????FF?TF???F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851500323.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is FamilyReunion-COL-L00100M0010C005P005G002, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851500323
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 640K
-rw-r--r-- 1 mcc users 7.0K Feb 26 13:10 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 26 13:10 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 26 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 15:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 126K Feb 26 15:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 15K Feb 26 14:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 98K Feb 26 14:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 140K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-12
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-13
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-14
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1678442408034
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L00100M0010C005P005G002
Not applying reductions.
Model is COL
LTLCardinality PT
[2023-03-10 10:00:09] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, LTLCardinality, --reduce-single, STATESPACE]
[2023-03-10 10:00:09] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-10 10:00:09] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 10:00:09] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 10:00:10] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 711 ms
[2023-03-10 10:00:10] [INFO ] Detected 5 constant HL places corresponding to 31 PT places.
[2023-03-10 10:00:10] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 40706 PT places and 36972.0 transition bindings in 29 ms.
Parsed 16 properties from file ./LTLCardinality.xml in 11 ms.
[2023-03-10 10:00:10] [INFO ] Unfolded HLPN to a Petri net with 40706 places and 36871 transitions 105658 arcs in 190 ms.
[2023-03-10 10:00:10] [INFO ] Unfolded 16 HLPN properties in 4 ms.
Initial state reduction rules removed 3 formulas.
Reduce places removed 101 places and 0 transitions.
[2023-03-10 10:00:10] [INFO ] Export to MCC of 16 properties in file ./LTLCardinality.STATESPACE.xml took 29 ms.
[2023-03-10 10:00:10] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 40605 places, 36871 transitions and 105658 arcs took 176 ms.
Total runtime 1610 ms.
starting LoLA
BK_INPUT FamilyReunion-COL-L00100M0010C005P005G002
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfLTLCardinality
LTLCardinality
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678443422574
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfLTLCardinality/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfLTLCardinality/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfLTLCardinality/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 68 (type SKEL/SRCH) for 0 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 68 (type SKEL/SRCH) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 69 (type SKEL/SRCH) for 10 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 69 (type SKEL/SRCH) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02
lola: result : false
lola: markings : 5957
lola: fired transitions : 6006
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00: LTL true skeleton: LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: CONJ 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: INITIAL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-15: INITIAL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: CONJ 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: INITIAL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-15: INITIAL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: CONJ 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: INITIAL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-15: INITIAL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01: CONJ 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: CONJ 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: INITIAL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: INITIAL 0 0 0 0 0 0 0 0
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70 LTL SRCH 15/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 1474458 m, 71580 m/sec, 4231233 t fired, .
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70 LTL SRCH 20/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 1827927 m, 70693 m/sec, 5365776 t fired, .
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70 LTL SRCH 25/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 2219876 m, 78389 m/sec, 6581304 t fired, .
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70 LTL SRCH 30/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 2607248 m, 77474 m/sec, 7783333 t fired, .
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70 LTL SRCH 35/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 2988232 m, 76196 m/sec, 8967959 t fired, .
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70 LTL SRCH 40/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 3360621 m, 74477 m/sec, 10126662 t fired, .
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70 LTL SRCH 45/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 3735609 m, 74997 m/sec, 11269632 t fired, .
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70 LTL SRCH 50/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 4104685 m, 73815 m/sec, 12397935 t fired, .
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70 LTL SRCH 65/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 5311584 m, 75593 m/sec, 16082153 t fired, .
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70 LTL SRCH 70/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 5630959 m, 63875 m/sec, 17242877 t fired, .
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70 LTL SRCH 75/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 5944521 m, 62712 m/sec, 18359611 t fired, .
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70 LTL SRCH 80/3015 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 6234953 m, 58086 m/sec, 19440775 t fired, .
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70 LTL SRCH 120/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 8769589 m, 71290 m/sec, 28325069 t fired, .
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70 LTL SRCH 125/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 9107434 m, 67569 m/sec, 29399018 t fired, .
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70 LTL SRCH 130/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 9415920 m, 61697 m/sec, 30516842 t fired, .
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70 LTL SRCH 135/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 9734313 m, 63678 m/sec, 31657309 t fired, .
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70 LTL SRCH 140/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 10057142 m, 64565 m/sec, 32814901 t fired, .
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70 LTL SRCH 145/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 10367968 m, 62165 m/sec, 33934851 t fired, .
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70 LTL SRCH 150/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 10665604 m, 59527 m/sec, 35003803 t fired, .
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70 LTL SRCH 175/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 12339293 m, 72214 m/sec, 40673374 t fired, .
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70 LTL SRCH 180/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 12643378 m, 60817 m/sec, 41798643 t fired, .
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70 LTL SRCH 185/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 12955413 m, 62407 m/sec, 42921058 t fired, .
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70 LTL SRCH 190/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 13219397 m, 52796 m/sec, 43865142 t fired, .
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70 LTL SRCH 195/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 13486861 m, 53492 m/sec, 44821913 t fired, .
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70 LTL SRCH 200/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 13773856 m, 57399 m/sec, 45831835 t fired, .
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70 LTL SRCH 205/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 14048426 m, 54914 m/sec, 46801111 t fired, .
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70 LTL SRCH 210/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 14367243 m, 63763 m/sec, 47913635 t fired, .
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70 LTL SRCH 225/3015 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 15334247 m, 57487 m/sec, 51148026 t fired, .
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70 LTL SRCH 230/3015 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 15614333 m, 56017 m/sec, 52153996 t fired, .
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70 LTL SRCH 235/3015 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 15914982 m, 60129 m/sec, 53232586 t fired, .
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70 LTL SRCH 240/3015 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 16203990 m, 57801 m/sec, 54251832 t fired, .
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70 LTL SRCH 245/3015 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 16534893 m, 66180 m/sec, 55403068 t fired, .
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70 LTL SRCH 250/3015 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02 16890579 m, 71137 m/sec, 56538257 t fired, .
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FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: CONJ false state space
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: INITIAL true preprocessing
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FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ false LTL model checker
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL false LTL model checker
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: CONJ false state space
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: INITIAL true preprocessing
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: INITIAL false preprocessing
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FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL false LTL model checker
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: CONJ false state space
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: INITIAL true preprocessing
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FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ false LTL model checker
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL false LTL model checker
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: CONJ false state space
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: INITIAL true preprocessing
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: INITIAL false preprocessing
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FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: CONJ false state space
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: INITIAL true preprocessing
FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: INITIAL false preprocessing
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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 431 Killed lola --conf=$BIN_DIR/configfiles/ltlcardinalityconf --formula=$DIR/LTLCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
sara: place or transition ordering is non-deterministic
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00100M0010C005P005G002"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00100M0010C005P005G002, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851500323"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00100M0010C005P005G002.tgz
mv FamilyReunion-COL-L00100M0010C005P005G002 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;