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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r166-tall-167838851500306
Last Updated
May 14, 2023

About the Execution of LoLA for FamilyReunion-COL-L00020M0002C001P001G001

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16009.523 1529969.00 1542840.00 3994.00 ??FF???FF?T????T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851500306.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is FamilyReunion-COL-L00020M0002C001P001G001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851500306
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 560K
-rw-r--r-- 1 mcc users 7.4K Feb 26 11:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K Feb 26 11:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Feb 26 11:36 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K Feb 26 11:36 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.9K Feb 26 11:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 26 11:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 11:45 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 65K Feb 26 11:45 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 135K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-00
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678438307986

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L00020M0002C001P001G001
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-10 08:51:49] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-10 08:51:49] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-10 08:51:49] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 08:51:49] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 08:51:50] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 703 ms
[2023-03-10 08:51:50] [INFO ] Detected 5 constant HL places corresponding to 11 PT places.
[2023-03-10 08:51:50] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 3292 PT places and 2774.0 transition bindings in 26 ms.
Parsed 16 properties from file ./CTLFireability.xml in 12 ms.
[2023-03-10 08:51:50] [INFO ] Unfolded HLPN to a Petri net with 3292 places and 2753 transitions 7900 arcs in 49 ms.
[2023-03-10 08:51:50] [INFO ] Unfolded 16 HLPN properties in 2 ms.
[2023-03-10 08:51:50] [INFO ] Reduced 21 identical enabling conditions.
[2023-03-10 08:51:50] [INFO ] Reduced 42 identical enabling conditions.
[2023-03-10 08:51:50] [INFO ] Reduced 42 identical enabling conditions.
[2023-03-10 08:51:50] [INFO ] Reduced 21 identical enabling conditions.
[2023-03-10 08:51:50] [INFO ] Reduced 42 identical enabling conditions.
[2023-03-10 08:51:50] [INFO ] Reduced 21 identical enabling conditions.
[2023-03-10 08:51:50] [INFO ] Reduced 21 identical enabling conditions.
[2023-03-10 08:51:50] [INFO ] Reduced 21 identical enabling conditions.
[2023-03-10 08:51:50] [INFO ] Reduced 42 identical enabling conditions.
Reduce places removed 21 places and 0 transitions.
[2023-03-10 08:51:50] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 42 ms.
[2023-03-10 08:51:50] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 3271 places, 2753 transitions and 7900 arcs took 15 ms.
Total runtime 1012 ms.
starting LoLA
BK_INPUT FamilyReunion-COL-L00020M0002C001P001G001
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfCTLFireability

FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678439837955

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfCTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfCTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfCTLFireability/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 84 (type SKEL/SRCH) for 9 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 84 (type SKEL/SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 85 (type SKEL/SRCH) for 9 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type SKEL/SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03
lola: result : false
lola: time used : 1.000000
lola: memory pages used : 1
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 86 (type SKEL/SRCH) for 9 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 86 (type SKEL/SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 87 (type EXCL) for 55 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09
lola: time limit : 108 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
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sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-89.sara.
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87 EG EXCL 1/130 1/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 20165 m, 4033 m/sec, 119031 t fired, .

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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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87 EG EXCL 6/162 1/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 116730 m, 19313 m/sec, 792875 t fired, .

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87 EG EXCL 11/162 2/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 204816 m, 17617 m/sec, 1478248 t fired, .

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87 EG EXCL 16/162 2/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 291922 m, 17421 m/sec, 2165849 t fired, .

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87 EG EXCL 21/162 2/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 377257 m, 17067 m/sec, 2853458 t fired, .

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87 EG EXCL 26/162 3/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 459013 m, 16351 m/sec, 3545152 t fired, .

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87 EG EXCL 31/162 3/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 531354 m, 14468 m/sec, 4245702 t fired, .

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87 EG EXCL 151/162 12/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 2412469 m, 14985 m/sec, 20850538 t fired, .

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87 EG EXCL 156/162 13/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 2482599 m, 14026 m/sec, 21528369 t fired, .

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87 EG EXCL 161/162 13/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 2550790 m, 13638 m/sec, 22208723 t fired, .

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87 EG EXCL 5/162 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 99269 m, -490304 m/sec, 672155 t fired, .

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87 EG EXCL 10/162 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09 187984 m, 17743 m/sec, 1362625 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ 0 0 0 0 7 0 1 1
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/539 23/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01 1174187 m, 23738 m/sec, 3098342 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03: CONJ false CONJ
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15: CTL true CTL model checker

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ 0 0 0 0 7 0 1 1
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 50/539 25/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01 1292869 m, 23736 m/sec, 3442949 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03: CONJ false CONJ
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15: CTL true CTL model checker

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ 0 0 0 0 7 0 1 1
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 55/539 27/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01 1410244 m, 23475 m/sec, 3787084 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15: CTL true CTL model checker

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ 0 0 0 0 7 0 1 1
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 60/539 29/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01 1524363 m, 22823 m/sec, 4132045 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03: CONJ false CONJ
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ 0 0 0 0 7 0 1 1
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 65/539 31/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01 1633387 m, 21804 m/sec, 4477502 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03: CONJ false CONJ
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15: CTL true CTL model checker

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ 0 0 0 0 7 0 1 1
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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lola: LAUNCH task # 50 (type EXCL) for 49 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07
lola: time limit : 696 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07
lola: result : false
lola: markings : 3
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-00
lola: time limit : 1044 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03: CONJ false CONJ
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ 0 0 0 0 7 0 1 1
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/1044 11/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-00 516096 m, 103219 m/sec, 578267 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03: CONJ false CONJ
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ 0 0 0 0 7 0 1 1
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/1044 22/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-00 1025919 m, 101964 m/sec, 1150834 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03: CONJ false CONJ
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15: CTL true CTL model checker

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FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ 0 0 0 0 7 0 1 1
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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lola: FINISHED task # 7 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02
lola: result : false
lola: markings : 72
lola: fired transitions : 147
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-00: CTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-01: CTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-02: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-03: CONJ false CONJ
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-04: CTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-05: CTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-06: CTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-07: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-09: DISJ unknown DISJ
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-11: CTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-12: CTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-13: CTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-14: CTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00020M0002C001P001G001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00020M0002C001P001G001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851500306"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00020M0002C001P001G001.tgz
mv FamilyReunion-COL-L00020M0002C001P001G001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;