fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r166-tall-167838851200114
Last Updated
May 14, 2023

About the Execution of LoLA for Echo-PT-d05r03

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3737.871 1378603.00 1374530.00 2243.30 ????TFT?T??F??T? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851200114.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is Echo-PT-d05r03, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851200114
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.8M
-rw-r--r-- 1 mcc users 6.0K Feb 25 14:08 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K Feb 25 14:08 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 25 14:07 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 14:07 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 14:12 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 173K Feb 25 14:12 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.7K Feb 25 14:10 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K Feb 25 14:10 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 2.3M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Echo-PT-d05r03-CTLFireability-00
FORMULA_NAME Echo-PT-d05r03-CTLFireability-01
FORMULA_NAME Echo-PT-d05r03-CTLFireability-02
FORMULA_NAME Echo-PT-d05r03-CTLFireability-03
FORMULA_NAME Echo-PT-d05r03-CTLFireability-04
FORMULA_NAME Echo-PT-d05r03-CTLFireability-05
FORMULA_NAME Echo-PT-d05r03-CTLFireability-06
FORMULA_NAME Echo-PT-d05r03-CTLFireability-07
FORMULA_NAME Echo-PT-d05r03-CTLFireability-08
FORMULA_NAME Echo-PT-d05r03-CTLFireability-09
FORMULA_NAME Echo-PT-d05r03-CTLFireability-10
FORMULA_NAME Echo-PT-d05r03-CTLFireability-11
FORMULA_NAME Echo-PT-d05r03-CTLFireability-12
FORMULA_NAME Echo-PT-d05r03-CTLFireability-13
FORMULA_NAME Echo-PT-d05r03-CTLFireability-14
FORMULA_NAME Echo-PT-d05r03-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678418899084

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Echo-PT-d05r03
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT Echo-PT-d05r03
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA Echo-PT-d05r03-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d05r03-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d05r03-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d05r03-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d05r03-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d05r03-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678420277687

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type SKEL/FNDP) for 28 Echo-PT-d05r03-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/EQUN) for 28 Echo-PT-d05r03-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 55 (type SKEL/SRCH) for 28 Echo-PT-d05r03-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SKEL/SRCH) for 28 Echo-PT-d05r03-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type SKEL/SRCH) for Echo-PT-d05r03-CTLFireability-08
lola: result : true
lola: markings : 6
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 53 (type FNDP) for Echo-PT-d05r03-CTLFireability-08 (obsolete)
lola: CANCELED task # 54 (type EQUN) for Echo-PT-d05r03-CTLFireability-08 (obsolete)
lola: CANCELED task # 56 (type SRCH) for Echo-PT-d05r03-CTLFireability-08 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 53 (type SKEL/FNDP) for Echo-PT-d05r03-CTLFireability-08
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/CTLFireability-54.sara.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.

lola: FINISHED task # 54 (type SKEL/EQUN) for Echo-PT-d05r03-CTLFireability-08
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 58 (type SKEL/SRCH) for 15 Echo-PT-d05r03-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 58 (type SKEL/SRCH) for Echo-PT-d05r03-CTLFireability-05
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-05: CONJ 0 0 0 0 2 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-08: EF 0 0 0 0 3 0 0 1
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 27 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 59 (type EXCL) for 15 Echo-PT-d05r03-CTLFireability-05
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 59 (type EXCL) for Echo-PT-d05r03-CTLFireability-05
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 44 (type EXCL) for 43 Echo-PT-d05r03-CTLFireability-13
lola: time limit : 238 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 61 (type FNDP) for 28 Echo-PT-d05r03-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 28 Echo-PT-d05r03-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 28 Echo-PT-d05r03-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 64 (type SRCH) for Echo-PT-d05r03-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 61 (type FNDP) for Echo-PT-d05r03-CTLFireability-08
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 62 (type EQUN) for Echo-PT-d05r03-CTLFireability-08 (obsolete)
sara: try reading problem file /home/mcc/execution/CTLFireability-62.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 3/255 2/32 Echo-PT-d05r03-CTLFireability-13 159991 m, 31998 m/sec, 590115 t fired, .

Time elapsed: 32 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16

lola: FINISHED task # 62 (type EQUN) for Echo-PT-d05r03-CTLFireability-08
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 8/255 4/32 Echo-PT-d05r03-CTLFireability-13 418747 m, 51751 m/sec, 1649775 t fired, .

Time elapsed: 37 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 13/255 6/32 Echo-PT-d05r03-CTLFireability-13 671312 m, 50513 m/sec, 2724384 t fired, .

Time elapsed: 42 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 18/255 8/32 Echo-PT-d05r03-CTLFireability-13 925097 m, 50757 m/sec, 3805199 t fired, .

Time elapsed: 47 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 23/255 10/32 Echo-PT-d05r03-CTLFireability-13 1178701 m, 50720 m/sec, 4884635 t fired, .

Time elapsed: 52 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 28/255 12/32 Echo-PT-d05r03-CTLFireability-13 1437080 m, 51675 m/sec, 5982269 t fired, .

Time elapsed: 57 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 33/255 14/32 Echo-PT-d05r03-CTLFireability-13 1693904 m, 51364 m/sec, 7075864 t fired, .

Time elapsed: 62 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 38/255 16/32 Echo-PT-d05r03-CTLFireability-13 1931399 m, 47499 m/sec, 8181891 t fired, .

Time elapsed: 67 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 43/255 17/32 Echo-PT-d05r03-CTLFireability-13 2159549 m, 45630 m/sec, 9267854 t fired, .

Time elapsed: 72 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 48/255 19/32 Echo-PT-d05r03-CTLFireability-13 2389067 m, 45903 m/sec, 10354214 t fired, .

Time elapsed: 77 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 53/255 21/32 Echo-PT-d05r03-CTLFireability-13 2620109 m, 46208 m/sec, 11449213 t fired, .

Time elapsed: 82 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 58/255 23/32 Echo-PT-d05r03-CTLFireability-13 2850386 m, 46055 m/sec, 12546311 t fired, .

Time elapsed: 87 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 63/255 25/32 Echo-PT-d05r03-CTLFireability-13 3093034 m, 48529 m/sec, 13645741 t fired, .

Time elapsed: 92 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 68/255 27/32 Echo-PT-d05r03-CTLFireability-13 3338591 m, 49111 m/sec, 14743066 t fired, .

Time elapsed: 97 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 73/255 28/32 Echo-PT-d05r03-CTLFireability-13 3570794 m, 46440 m/sec, 15842657 t fired, .

Time elapsed: 102 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 78/255 30/32 Echo-PT-d05r03-CTLFireability-13 3800490 m, 45939 m/sec, 16931010 t fired, .

Time elapsed: 107 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 83/255 32/32 Echo-PT-d05r03-CTLFireability-13 4030529 m, 46007 m/sec, 18032241 t fired, .

Time elapsed: 112 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 44 (type EXCL) for Echo-PT-d05r03-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-11: AXAF 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 117 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 60 (type EXCL) for 37 Echo-PT-d05r03-CTLFireability-11
lola: time limit : 267 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for Echo-PT-d05r03-CTLFireability-11
lola: result : true
lola: markings : 486
lola: fired transitions : 485
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 49 Echo-PT-d05r03-CTLFireability-15
lola: time limit : 290 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 4/290 4/32 Echo-PT-d05r03-CTLFireability-15 400109 m, 80021 m/sec, 588913 t fired, .

Time elapsed: 122 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 9/290 9/32 Echo-PT-d05r03-CTLFireability-15 1055838 m, 131145 m/sec, 1591012 t fired, .

Time elapsed: 127 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 14/290 14/32 Echo-PT-d05r03-CTLFireability-15 1707310 m, 130294 m/sec, 2586547 t fired, .

Time elapsed: 132 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 19/290 19/32 Echo-PT-d05r03-CTLFireability-15 2319808 m, 122499 m/sec, 3581530 t fired, .

Time elapsed: 137 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 24/290 24/32 Echo-PT-d05r03-CTLFireability-15 2934827 m, 123003 m/sec, 4582148 t fired, .

Time elapsed: 142 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 29/290 29/32 Echo-PT-d05r03-CTLFireability-15 3556466 m, 124327 m/sec, 5571678 t fired, .

Time elapsed: 147 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 50 (type EXCL) for Echo-PT-d05r03-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 152 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 47 (type EXCL) for 46 Echo-PT-d05r03-CTLFireability-14
lola: time limit : 313 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for Echo-PT-d05r03-CTLFireability-14
lola: result : true
lola: markings : 487
lola: fired transitions : 486
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 Echo-PT-d05r03-CTLFireability-12
lola: time limit : 344 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/344 2/32 Echo-PT-d05r03-CTLFireability-12 165417 m, 33083 m/sec, 1077038 t fired, .

Time elapsed: 157 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/344 3/32 Echo-PT-d05r03-CTLFireability-12 317611 m, 30438 m/sec, 2176012 t fired, .

Time elapsed: 162 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/344 4/32 Echo-PT-d05r03-CTLFireability-12 462515 m, 28980 m/sec, 3275205 t fired, .

Time elapsed: 167 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/344 5/32 Echo-PT-d05r03-CTLFireability-12 608195 m, 29136 m/sec, 4373314 t fired, .

Time elapsed: 172 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/344 6/32 Echo-PT-d05r03-CTLFireability-12 753225 m, 29006 m/sec, 5476791 t fired, .

Time elapsed: 177 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/344 8/32 Echo-PT-d05r03-CTLFireability-12 898048 m, 28964 m/sec, 6588942 t fired, .

Time elapsed: 182 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 35/344 9/32 Echo-PT-d05r03-CTLFireability-12 1042681 m, 28926 m/sec, 7702520 t fired, .

Time elapsed: 187 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 40/344 10/32 Echo-PT-d05r03-CTLFireability-12 1189472 m, 29358 m/sec, 8798342 t fired, .

Time elapsed: 192 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 45/344 11/32 Echo-PT-d05r03-CTLFireability-12 1326816 m, 27468 m/sec, 9900365 t fired, .

Time elapsed: 197 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 50/344 12/32 Echo-PT-d05r03-CTLFireability-12 1454715 m, 25579 m/sec, 11009536 t fired, .

Time elapsed: 202 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 55/344 13/32 Echo-PT-d05r03-CTLFireability-12 1580928 m, 25242 m/sec, 12109652 t fired, .

Time elapsed: 207 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 60/344 14/32 Echo-PT-d05r03-CTLFireability-12 1711375 m, 26089 m/sec, 13221951 t fired, .

Time elapsed: 212 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 65/344 15/32 Echo-PT-d05r03-CTLFireability-12 1841308 m, 25986 m/sec, 14329597 t fired, .

Time elapsed: 217 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 70/344 16/32 Echo-PT-d05r03-CTLFireability-12 1971411 m, 26020 m/sec, 15436046 t fired, .

Time elapsed: 222 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 75/344 17/32 Echo-PT-d05r03-CTLFireability-12 2098180 m, 25353 m/sec, 16545886 t fired, .

Time elapsed: 227 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 80/344 18/32 Echo-PT-d05r03-CTLFireability-12 2241379 m, 28639 m/sec, 17628269 t fired, .

Time elapsed: 232 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 85/344 19/32 Echo-PT-d05r03-CTLFireability-12 2377938 m, 27311 m/sec, 18726329 t fired, .

Time elapsed: 237 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 90/344 20/32 Echo-PT-d05r03-CTLFireability-12 2506037 m, 25619 m/sec, 19831808 t fired, .

Time elapsed: 242 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 95/344 21/32 Echo-PT-d05r03-CTLFireability-12 2631622 m, 25117 m/sec, 20930234 t fired, .

Time elapsed: 247 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 100/344 22/32 Echo-PT-d05r03-CTLFireability-12 2761790 m, 26033 m/sec, 22039225 t fired, .

Time elapsed: 252 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 105/344 23/32 Echo-PT-d05r03-CTLFireability-12 2885924 m, 24826 m/sec, 23095900 t fired, .

Time elapsed: 257 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 110/344 24/32 Echo-PT-d05r03-CTLFireability-12 3004450 m, 23705 m/sec, 24115211 t fired, .

Time elapsed: 262 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 115/344 25/32 Echo-PT-d05r03-CTLFireability-12 3125609 m, 24231 m/sec, 25175542 t fired, .

Time elapsed: 267 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 120/344 26/32 Echo-PT-d05r03-CTLFireability-12 3264183 m, 27714 m/sec, 26215172 t fired, .

Time elapsed: 272 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 125/344 27/32 Echo-PT-d05r03-CTLFireability-12 3396273 m, 26418 m/sec, 27263167 t fired, .

Time elapsed: 277 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 130/344 28/32 Echo-PT-d05r03-CTLFireability-12 3516329 m, 24011 m/sec, 28322545 t fired, .

Time elapsed: 282 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 135/344 29/32 Echo-PT-d05r03-CTLFireability-12 3637133 m, 24160 m/sec, 29350682 t fired, .

Time elapsed: 287 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 140/344 30/32 Echo-PT-d05r03-CTLFireability-12 3757952 m, 24163 m/sec, 30377913 t fired, .

Time elapsed: 292 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 145/344 31/32 Echo-PT-d05r03-CTLFireability-12 3879989 m, 24407 m/sec, 31430965 t fired, .

Time elapsed: 297 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 150/344 32/32 Echo-PT-d05r03-CTLFireability-12 4000716 m, 24145 m/sec, 32479818 t fired, .

Time elapsed: 302 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 41 (type EXCL) for Echo-PT-d05r03-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 307 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 35 (type EXCL) for 34 Echo-PT-d05r03-CTLFireability-10
lola: time limit : 365 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 5/365 2/32 Echo-PT-d05r03-CTLFireability-10 153825 m, 30765 m/sec, 998963 t fired, .

Time elapsed: 312 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 10/365 3/32 Echo-PT-d05r03-CTLFireability-10 297444 m, 28723 m/sec, 2022562 t fired, .

Time elapsed: 317 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 15/365 4/32 Echo-PT-d05r03-CTLFireability-10 437366 m, 27984 m/sec, 3075188 t fired, .

Time elapsed: 322 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 20/365 5/32 Echo-PT-d05r03-CTLFireability-10 574676 m, 27462 m/sec, 4130901 t fired, .

Time elapsed: 327 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 25/365 6/32 Echo-PT-d05r03-CTLFireability-10 712164 m, 27497 m/sec, 5193450 t fired, .

Time elapsed: 332 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 30/365 7/32 Echo-PT-d05r03-CTLFireability-10 852212 m, 28009 m/sec, 6247284 t fired, .

Time elapsed: 337 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 35/365 8/32 Echo-PT-d05r03-CTLFireability-10 992329 m, 28023 m/sec, 7309834 t fired, .

Time elapsed: 342 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 40/365 9/32 Echo-PT-d05r03-CTLFireability-10 1134685 m, 28471 m/sec, 8366401 t fired, .

Time elapsed: 347 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 45/365 10/32 Echo-PT-d05r03-CTLFireability-10 1268091 m, 26681 m/sec, 9418323 t fired, .

Time elapsed: 352 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 50/365 11/32 Echo-PT-d05r03-CTLFireability-10 1393668 m, 25115 m/sec, 10490338 t fired, .

Time elapsed: 357 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 55/365 12/32 Echo-PT-d05r03-CTLFireability-10 1518462 m, 24958 m/sec, 11552961 t fired, .

Time elapsed: 362 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 60/365 13/32 Echo-PT-d05r03-CTLFireability-10 1643368 m, 24981 m/sec, 12616246 t fired, .

Time elapsed: 367 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 65/365 14/32 Echo-PT-d05r03-CTLFireability-10 1765094 m, 24345 m/sec, 13691008 t fired, .

Time elapsed: 372 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 70/365 15/32 Echo-PT-d05r03-CTLFireability-10 1889763 m, 24933 m/sec, 14754884 t fired, .

Time elapsed: 377 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 75/365 16/32 Echo-PT-d05r03-CTLFireability-10 2015494 m, 25146 m/sec, 15824871 t fired, .

Time elapsed: 382 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 80/365 17/32 Echo-PT-d05r03-CTLFireability-10 2145914 m, 26084 m/sec, 16884499 t fired, .

Time elapsed: 387 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 85/365 18/32 Echo-PT-d05r03-CTLFireability-10 2280819 m, 26981 m/sec, 17935012 t fired, .

Time elapsed: 392 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 90/365 19/32 Echo-PT-d05r03-CTLFireability-10 2409423 m, 25720 m/sec, 19002152 t fired, .

Time elapsed: 397 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 95/365 20/32 Echo-PT-d05r03-CTLFireability-10 2534507 m, 25016 m/sec, 20067006 t fired, .

Time elapsed: 402 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 100/365 21/32 Echo-PT-d05r03-CTLFireability-10 2655894 m, 24277 m/sec, 21127775 t fired, .

Time elapsed: 407 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 105/365 22/32 Echo-PT-d05r03-CTLFireability-10 2780924 m, 25006 m/sec, 22205053 t fired, .

Time elapsed: 412 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 110/365 23/32 Echo-PT-d05r03-CTLFireability-10 2905551 m, 24925 m/sec, 23266005 t fired, .

Time elapsed: 417 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 115/365 24/32 Echo-PT-d05r03-CTLFireability-10 3030459 m, 24981 m/sec, 24329496 t fired, .

Time elapsed: 422 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 120/365 25/32 Echo-PT-d05r03-CTLFireability-10 3154680 m, 24844 m/sec, 25396441 t fired, .

Time elapsed: 427 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 125/365 26/32 Echo-PT-d05r03-CTLFireability-10 3292902 m, 27644 m/sec, 26451086 t fired, .

Time elapsed: 432 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 130/365 27/32 Echo-PT-d05r03-CTLFireability-10 3424680 m, 26355 m/sec, 27512307 t fired, .

Time elapsed: 437 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 135/365 28/32 Echo-PT-d05r03-CTLFireability-10 3548030 m, 24670 m/sec, 28578903 t fired, .

Time elapsed: 442 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 140/365 29/32 Echo-PT-d05r03-CTLFireability-10 3669958 m, 24385 m/sec, 29637984 t fired, .

Time elapsed: 447 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 145/365 30/32 Echo-PT-d05r03-CTLFireability-10 3795532 m, 25114 m/sec, 30708249 t fired, .

Time elapsed: 452 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 150/365 31/32 Echo-PT-d05r03-CTLFireability-10 3920601 m, 25013 m/sec, 31773826 t fired, .

Time elapsed: 457 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 155/365 32/32 Echo-PT-d05r03-CTLFireability-10 4043154 m, 24510 m/sec, 32834105 t fired, .

Time elapsed: 462 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 35 (type EXCL) for Echo-PT-d05r03-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 468 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 32 (type EXCL) for 31 Echo-PT-d05r03-CTLFireability-09
lola: time limit : 391 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/391 2/32 Echo-PT-d05r03-CTLFireability-09 165028 m, 33005 m/sec, 1039385 t fired, .

Time elapsed: 473 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/391 3/32 Echo-PT-d05r03-CTLFireability-09 315828 m, 30160 m/sec, 2089656 t fired, .

Time elapsed: 478 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/391 4/32 Echo-PT-d05r03-CTLFireability-09 452769 m, 27388 m/sec, 3158595 t fired, .

Time elapsed: 483 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 20/391 5/32 Echo-PT-d05r03-CTLFireability-09 593086 m, 28063 m/sec, 4211409 t fired, .

Time elapsed: 488 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 25/391 6/32 Echo-PT-d05r03-CTLFireability-09 732789 m, 27940 m/sec, 5266623 t fired, .

Time elapsed: 493 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 30/391 7/32 Echo-PT-d05r03-CTLFireability-09 868094 m, 27061 m/sec, 6335364 t fired, .

Time elapsed: 498 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 35/391 8/32 Echo-PT-d05r03-CTLFireability-09 1009299 m, 28241 m/sec, 7392665 t fired, .

Time elapsed: 503 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 40/391 10/32 Echo-PT-d05r03-CTLFireability-09 1150270 m, 28194 m/sec, 8450677 t fired, .

Time elapsed: 508 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 45/391 11/32 Echo-PT-d05r03-CTLFireability-09 1284685 m, 26883 m/sec, 9517202 t fired, .

Time elapsed: 513 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 50/391 12/32 Echo-PT-d05r03-CTLFireability-09 1426590 m, 28381 m/sec, 10569367 t fired, .

Time elapsed: 518 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 55/391 13/32 Echo-PT-d05r03-CTLFireability-09 1559159 m, 26513 m/sec, 11620621 t fired, .

Time elapsed: 523 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 60/391 14/32 Echo-PT-d05r03-CTLFireability-09 1686652 m, 25498 m/sec, 12694586 t fired, .

Time elapsed: 528 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 65/391 15/32 Echo-PT-d05r03-CTLFireability-09 1814428 m, 25555 m/sec, 13786985 t fired, .

Time elapsed: 533 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 70/391 16/32 Echo-PT-d05r03-CTLFireability-09 1932785 m, 23671 m/sec, 14829666 t fired, .

Time elapsed: 538 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 75/391 17/32 Echo-PT-d05r03-CTLFireability-09 2054445 m, 24332 m/sec, 15863881 t fired, .

Time elapsed: 543 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 80/391 18/32 Echo-PT-d05r03-CTLFireability-09 2171356 m, 23382 m/sec, 16903033 t fired, .

Time elapsed: 548 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 85/391 19/32 Echo-PT-d05r03-CTLFireability-09 2293614 m, 24451 m/sec, 17933284 t fired, .

Time elapsed: 553 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 90/391 19/32 Echo-PT-d05r03-CTLFireability-09 2416144 m, 24506 m/sec, 18992901 t fired, .

Time elapsed: 558 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 95/391 20/32 Echo-PT-d05r03-CTLFireability-09 2536281 m, 24027 m/sec, 20040227 t fired, .

Time elapsed: 563 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 100/391 21/32 Echo-PT-d05r03-CTLFireability-09 2669999 m, 26743 m/sec, 21070691 t fired, .

Time elapsed: 568 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 105/391 22/32 Echo-PT-d05r03-CTLFireability-09 2799719 m, 25944 m/sec, 22098837 t fired, .

Time elapsed: 573 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 110/391 23/32 Echo-PT-d05r03-CTLFireability-09 2927550 m, 25566 m/sec, 23136628 t fired, .

Time elapsed: 578 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 115/391 24/32 Echo-PT-d05r03-CTLFireability-09 3044576 m, 23405 m/sec, 24180879 t fired, .

Time elapsed: 583 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 120/391 25/32 Echo-PT-d05r03-CTLFireability-09 3167414 m, 24567 m/sec, 25214183 t fired, .

Time elapsed: 588 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 125/391 26/32 Echo-PT-d05r03-CTLFireability-09 3285943 m, 23705 m/sec, 26247580 t fired, .

Time elapsed: 593 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 130/391 27/32 Echo-PT-d05r03-CTLFireability-09 3406595 m, 24130 m/sec, 27294707 t fired, .

Time elapsed: 598 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 135/391 28/32 Echo-PT-d05r03-CTLFireability-09 3529923 m, 24665 m/sec, 28334526 t fired, .

Time elapsed: 603 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 140/391 29/32 Echo-PT-d05r03-CTLFireability-09 3646463 m, 23308 m/sec, 29372313 t fired, .

Time elapsed: 608 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 145/391 30/32 Echo-PT-d05r03-CTLFireability-09 3769234 m, 24554 m/sec, 30414513 t fired, .

Time elapsed: 613 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 150/391 31/32 Echo-PT-d05r03-CTLFireability-09 3890473 m, 24247 m/sec, 31455181 t fired, .

Time elapsed: 618 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 155/391 32/32 Echo-PT-d05r03-CTLFireability-09 4027211 m, 27347 m/sec, 32481519 t fired, .

Time elapsed: 623 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 32 (type EXCL) for Echo-PT-d05r03-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 628 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 25 Echo-PT-d05r03-CTLFireability-07
lola: time limit : 424 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/424 2/32 Echo-PT-d05r03-CTLFireability-07 156512 m, 31302 m/sec, 1016548 t fired, .

Time elapsed: 633 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 10/424 3/32 Echo-PT-d05r03-CTLFireability-07 300771 m, 28851 m/sec, 2047358 t fired, .

Time elapsed: 638 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 15/424 4/32 Echo-PT-d05r03-CTLFireability-07 438355 m, 27516 m/sec, 3081581 t fired, .

Time elapsed: 643 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 20/424 5/32 Echo-PT-d05r03-CTLFireability-07 572378 m, 26804 m/sec, 4112194 t fired, .

Time elapsed: 648 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 25/424 6/32 Echo-PT-d05r03-CTLFireability-07 707240 m, 26972 m/sec, 5154005 t fired, .

Time elapsed: 653 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 30/424 7/32 Echo-PT-d05r03-CTLFireability-07 844417 m, 27435 m/sec, 6183442 t fired, .

Time elapsed: 658 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 35/424 8/32 Echo-PT-d05r03-CTLFireability-07 981433 m, 27403 m/sec, 7219055 t fired, .

Time elapsed: 663 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 40/424 9/32 Echo-PT-d05r03-CTLFireability-07 1120394 m, 27792 m/sec, 8248590 t fired, .

Time elapsed: 668 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 45/424 10/32 Echo-PT-d05r03-CTLFireability-07 1249575 m, 25836 m/sec, 9277024 t fired, .

Time elapsed: 673 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 50/424 11/32 Echo-PT-d05r03-CTLFireability-07 1373868 m, 24858 m/sec, 10319776 t fired, .

Time elapsed: 678 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 55/424 12/32 Echo-PT-d05r03-CTLFireability-07 1495902 m, 24406 m/sec, 11356313 t fired, .

Time elapsed: 683 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 60/424 13/32 Echo-PT-d05r03-CTLFireability-07 1615180 m, 23855 m/sec, 12391085 t fired, .

Time elapsed: 688 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 65/424 14/32 Echo-PT-d05r03-CTLFireability-07 1736361 m, 24236 m/sec, 13438650 t fired, .

Time elapsed: 693 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 70/424 15/32 Echo-PT-d05r03-CTLFireability-07 1858294 m, 24386 m/sec, 14475756 t fired, .

Time elapsed: 698 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 75/424 16/32 Echo-PT-d05r03-CTLFireability-07 1980409 m, 24423 m/sec, 15514058 t fired, .

Time elapsed: 703 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 80/424 17/32 Echo-PT-d05r03-CTLFireability-07 2099498 m, 23817 m/sec, 16553682 t fired, .

Time elapsed: 708 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 85/424 18/32 Echo-PT-d05r03-CTLFireability-07 2235814 m, 27263 m/sec, 17579769 t fired, .

Time elapsed: 713 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 90/424 19/32 Echo-PT-d05r03-CTLFireability-07 2365457 m, 25928 m/sec, 18612426 t fired, .

Time elapsed: 718 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 95/424 20/32 Echo-PT-d05r03-CTLFireability-07 2484320 m, 23772 m/sec, 19654736 t fired, .

Time elapsed: 723 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 100/424 21/32 Echo-PT-d05r03-CTLFireability-07 2604493 m, 24034 m/sec, 20685279 t fired, .

Time elapsed: 728 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 105/424 22/32 Echo-PT-d05r03-CTLFireability-07 2726522 m, 24405 m/sec, 21725416 t fired, .

Time elapsed: 733 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 110/424 23/32 Echo-PT-d05r03-CTLFireability-07 2848482 m, 24392 m/sec, 22765559 t fired, .

Time elapsed: 738 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 115/424 24/32 Echo-PT-d05r03-CTLFireability-07 2965530 m, 23409 m/sec, 23799842 t fired, .

Time elapsed: 743 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 120/424 25/32 Echo-PT-d05r03-CTLFireability-07 3088088 m, 24511 m/sec, 24843591 t fired, .

Time elapsed: 748 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 125/424 26/32 Echo-PT-d05r03-CTLFireability-07 3220623 m, 26507 m/sec, 25873127 t fired, .

Time elapsed: 753 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 130/424 27/32 Echo-PT-d05r03-CTLFireability-07 3349668 m, 25809 m/sec, 26898081 t fired, .

Time elapsed: 758 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 135/424 28/32 Echo-PT-d05r03-CTLFireability-07 3473357 m, 24737 m/sec, 27942061 t fired, .

Time elapsed: 763 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 140/424 29/32 Echo-PT-d05r03-CTLFireability-07 3595119 m, 24352 m/sec, 28978745 t fired, .

Time elapsed: 768 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 145/424 30/32 Echo-PT-d05r03-CTLFireability-07 3715025 m, 23981 m/sec, 30012662 t fired, .

Time elapsed: 773 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 150/424 31/32 Echo-PT-d05r03-CTLFireability-07 3835294 m, 24053 m/sec, 31058131 t fired, .

Time elapsed: 778 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 155/424 31/32 Echo-PT-d05r03-CTLFireability-07 3957029 m, 24347 m/sec, 32093573 t fired, .

Time elapsed: 783 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 160/424 32/32 Echo-PT-d05r03-CTLFireability-07 4078908 m, 24375 m/sec, 33128840 t fired, .

Time elapsed: 788 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 26 (type EXCL) for Echo-PT-d05r03-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 793 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 23 (type EXCL) for 22 Echo-PT-d05r03-CTLFireability-06
lola: time limit : 467 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for Echo-PT-d05r03-CTLFireability-06
lola: result : true
lola: markings : 487
lola: fired transitions : 2432
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 Echo-PT-d05r03-CTLFireability-04
lola: time limit : 561 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for Echo-PT-d05r03-CTLFireability-04
lola: result : true
lola: markings : 487
lola: fired transitions : 973
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 Echo-PT-d05r03-CTLFireability-03
lola: time limit : 701 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/701 6/32 Echo-PT-d05r03-CTLFireability-03 546400 m, 109280 m/sec, 880658 t fired, .

Time elapsed: 798 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/701 9/32 Echo-PT-d05r03-CTLFireability-03 953837 m, 81487 m/sec, 1751747 t fired, .

Time elapsed: 803 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/701 13/32 Echo-PT-d05r03-CTLFireability-03 1367405 m, 82713 m/sec, 2622221 t fired, .

Time elapsed: 808 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/701 16/32 Echo-PT-d05r03-CTLFireability-03 1744675 m, 75454 m/sec, 3490387 t fired, .

Time elapsed: 813 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/701 19/32 Echo-PT-d05r03-CTLFireability-03 2136793 m, 78423 m/sec, 4356842 t fired, .

Time elapsed: 818 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/701 22/32 Echo-PT-d05r03-CTLFireability-03 2512361 m, 75113 m/sec, 5224926 t fired, .

Time elapsed: 823 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 35/701 25/32 Echo-PT-d05r03-CTLFireability-03 2899657 m, 77459 m/sec, 6085460 t fired, .

Time elapsed: 828 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 40/701 28/32 Echo-PT-d05r03-CTLFireability-03 3273929 m, 74854 m/sec, 6944519 t fired, .

Time elapsed: 833 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 45/701 31/32 Echo-PT-d05r03-CTLFireability-03 3655925 m, 76399 m/sec, 7800771 t fired, .

Time elapsed: 838 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for Echo-PT-d05r03-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 843 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 Echo-PT-d05r03-CTLFireability-02
lola: time limit : 919 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/919 1/32 Echo-PT-d05r03-CTLFireability-02 117828 m, 23565 m/sec, 980164 t fired, .

Time elapsed: 848 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/919 2/32 Echo-PT-d05r03-CTLFireability-02 228885 m, 22211 m/sec, 1967198 t fired, .

Time elapsed: 853 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/919 3/32 Echo-PT-d05r03-CTLFireability-02 333704 m, 20963 m/sec, 2973456 t fired, .

Time elapsed: 858 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/919 4/32 Echo-PT-d05r03-CTLFireability-02 439568 m, 21172 m/sec, 3970172 t fired, .

Time elapsed: 863 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/919 5/32 Echo-PT-d05r03-CTLFireability-02 540144 m, 20115 m/sec, 4964731 t fired, .

Time elapsed: 868 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/919 6/32 Echo-PT-d05r03-CTLFireability-02 646678 m, 21306 m/sec, 5967728 t fired, .

Time elapsed: 873 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/919 6/32 Echo-PT-d05r03-CTLFireability-02 751501 m, 20964 m/sec, 6968203 t fired, .

Time elapsed: 878 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/919 7/32 Echo-PT-d05r03-CTLFireability-02 854366 m, 20573 m/sec, 7971085 t fired, .

Time elapsed: 883 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/919 8/32 Echo-PT-d05r03-CTLFireability-02 959595 m, 21045 m/sec, 8969776 t fired, .

Time elapsed: 888 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/919 9/32 Echo-PT-d05r03-CTLFireability-02 1063299 m, 20740 m/sec, 9968606 t fired, .

Time elapsed: 893 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 55/919 10/32 Echo-PT-d05r03-CTLFireability-02 1168550 m, 21050 m/sec, 10967103 t fired, .

Time elapsed: 898 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 60/919 10/32 Echo-PT-d05r03-CTLFireability-02 1269382 m, 20166 m/sec, 11965545 t fired, .

Time elapsed: 903 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 65/919 11/32 Echo-PT-d05r03-CTLFireability-02 1366090 m, 19341 m/sec, 12980730 t fired, .

Time elapsed: 908 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 70/919 12/32 Echo-PT-d05r03-CTLFireability-02 1461745 m, 19131 m/sec, 13989382 t fired, .

Time elapsed: 913 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 75/919 13/32 Echo-PT-d05r03-CTLFireability-02 1555471 m, 18745 m/sec, 14993651 t fired, .

Time elapsed: 918 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 80/919 13/32 Echo-PT-d05r03-CTLFireability-02 1652622 m, 19430 m/sec, 16003085 t fired, .

Time elapsed: 923 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 85/919 14/32 Echo-PT-d05r03-CTLFireability-02 1745941 m, 18663 m/sec, 17019202 t fired, .

Time elapsed: 928 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 90/919 15/32 Echo-PT-d05r03-CTLFireability-02 1842626 m, 19337 m/sec, 18025897 t fired, .

Time elapsed: 933 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 95/919 16/32 Echo-PT-d05r03-CTLFireability-02 1936903 m, 18855 m/sec, 19034437 t fired, .

Time elapsed: 938 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 100/919 16/32 Echo-PT-d05r03-CTLFireability-02 2033049 m, 19229 m/sec, 20047873 t fired, .

Time elapsed: 943 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 105/919 17/32 Echo-PT-d05r03-CTLFireability-02 2132050 m, 19800 m/sec, 21050497 t fired, .

Time elapsed: 948 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 110/919 18/32 Echo-PT-d05r03-CTLFireability-02 2235068 m, 20603 m/sec, 22043636 t fired, .

Time elapsed: 953 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 115/919 19/32 Echo-PT-d05r03-CTLFireability-02 2337855 m, 20557 m/sec, 23063771 t fired, .

Time elapsed: 958 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 120/919 20/32 Echo-PT-d05r03-CTLFireability-02 2432388 m, 18906 m/sec, 24073288 t fired, .

Time elapsed: 963 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 125/919 20/32 Echo-PT-d05r03-CTLFireability-02 2528953 m, 19313 m/sec, 25073577 t fired, .

Time elapsed: 968 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 130/919 21/32 Echo-PT-d05r03-CTLFireability-02 2620949 m, 18399 m/sec, 26073890 t fired, .

Time elapsed: 973 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 135/919 22/32 Echo-PT-d05r03-CTLFireability-02 2717340 m, 19278 m/sec, 27080735 t fired, .

Time elapsed: 978 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 140/919 23/32 Echo-PT-d05r03-CTLFireability-02 2810846 m, 18701 m/sec, 28089376 t fired, .

Time elapsed: 983 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 145/919 23/32 Echo-PT-d05r03-CTLFireability-02 2906853 m, 19201 m/sec, 29090620 t fired, .

Time elapsed: 988 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 150/919 24/32 Echo-PT-d05r03-CTLFireability-02 3001094 m, 18848 m/sec, 30091054 t fired, .

Time elapsed: 993 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 155/919 25/32 Echo-PT-d05r03-CTLFireability-02 3095376 m, 18856 m/sec, 31097797 t fired, .

Time elapsed: 998 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 160/919 26/32 Echo-PT-d05r03-CTLFireability-02 3197284 m, 20381 m/sec, 32093812 t fired, .

Time elapsed: 1003 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 165/919 26/32 Echo-PT-d05r03-CTLFireability-02 3298180 m, 20179 m/sec, 33088229 t fired, .

Time elapsed: 1008 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 170/919 27/32 Echo-PT-d05r03-CTLFireability-02 3399190 m, 20202 m/sec, 34084267 t fired, .

Time elapsed: 1013 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 175/919 28/32 Echo-PT-d05r03-CTLFireability-02 3493179 m, 18797 m/sec, 35099041 t fired, .

Time elapsed: 1018 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 180/919 29/32 Echo-PT-d05r03-CTLFireability-02 3588851 m, 19134 m/sec, 36098800 t fired, .

Time elapsed: 1023 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 185/919 29/32 Echo-PT-d05r03-CTLFireability-02 3680729 m, 18375 m/sec, 37096354 t fired, .

Time elapsed: 1028 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 190/919 30/32 Echo-PT-d05r03-CTLFireability-02 3777797 m, 19413 m/sec, 38102758 t fired, .

Time elapsed: 1033 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 195/919 31/32 Echo-PT-d05r03-CTLFireability-02 3871979 m, 18836 m/sec, 39108818 t fired, .

Time elapsed: 1038 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 200/919 32/32 Echo-PT-d05r03-CTLFireability-02 3966139 m, 18832 m/sec, 40110368 t fired, .

Time elapsed: 1043 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 205/919 32/32 Echo-PT-d05r03-CTLFireability-02 4062094 m, 19191 m/sec, 41108171 t fired, .

Time elapsed: 1048 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for Echo-PT-d05r03-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1053 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 Echo-PT-d05r03-CTLFireability-00
lola: time limit : 1273 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/1273 2/32 Echo-PT-d05r03-CTLFireability-00 157734 m, 31546 m/sec, 1019736 t fired, .

Time elapsed: 1058 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/1273 3/32 Echo-PT-d05r03-CTLFireability-00 302116 m, 28876 m/sec, 2051826 t fired, .

Time elapsed: 1063 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/1273 4/32 Echo-PT-d05r03-CTLFireability-00 442260 m, 28028 m/sec, 3106014 t fired, .

Time elapsed: 1068 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/1273 5/32 Echo-PT-d05r03-CTLFireability-00 576404 m, 26828 m/sec, 4136860 t fired, .

Time elapsed: 1073 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/1273 6/32 Echo-PT-d05r03-CTLFireability-00 711236 m, 26966 m/sec, 5178994 t fired, .

Time elapsed: 1078 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/1273 7/32 Echo-PT-d05r03-CTLFireability-00 848679 m, 27488 m/sec, 6210000 t fired, .

Time elapsed: 1083 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/1273 8/32 Echo-PT-d05r03-CTLFireability-00 985797 m, 27423 m/sec, 7247403 t fired, .

Time elapsed: 1088 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/1273 9/32 Echo-PT-d05r03-CTLFireability-00 1124747 m, 27790 m/sec, 8278884 t fired, .

Time elapsed: 1093 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/1273 10/32 Echo-PT-d05r03-CTLFireability-00 1254532 m, 25957 m/sec, 9308661 t fired, .

Time elapsed: 1098 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/1273 11/32 Echo-PT-d05r03-CTLFireability-00 1378258 m, 24745 m/sec, 10352197 t fired, .

Time elapsed: 1103 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/1273 12/32 Echo-PT-d05r03-CTLFireability-00 1500113 m, 24371 m/sec, 11388934 t fired, .

Time elapsed: 1108 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 60/1273 13/32 Echo-PT-d05r03-CTLFireability-00 1620083 m, 23994 m/sec, 12423653 t fired, .

Time elapsed: 1113 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 65/1273 14/32 Echo-PT-d05r03-CTLFireability-00 1740700 m, 24123 m/sec, 13471516 t fired, .

Time elapsed: 1118 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 70/1273 15/32 Echo-PT-d05r03-CTLFireability-00 1862807 m, 24421 m/sec, 14509234 t fired, .

Time elapsed: 1123 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 75/1273 16/32 Echo-PT-d05r03-CTLFireability-00 1985002 m, 24439 m/sec, 15547943 t fired, .

Time elapsed: 1128 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 80/1273 17/32 Echo-PT-d05r03-CTLFireability-00 2105555 m, 24110 m/sec, 16589055 t fired, .

Time elapsed: 1133 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 85/1273 18/32 Echo-PT-d05r03-CTLFireability-00 2240864 m, 27061 m/sec, 17616471 t fired, .

Time elapsed: 1138 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 90/1273 19/32 Echo-PT-d05r03-CTLFireability-00 2370475 m, 25922 m/sec, 18649997 t fired, .

Time elapsed: 1143 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 95/1273 20/32 Echo-PT-d05r03-CTLFireability-00 2489314 m, 23767 m/sec, 19689241 t fired, .

Time elapsed: 1148 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 100/1273 21/32 Echo-PT-d05r03-CTLFireability-00 2609555 m, 24048 m/sec, 20721243 t fired, .

Time elapsed: 1153 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 105/1273 22/32 Echo-PT-d05r03-CTLFireability-00 2731809 m, 24450 m/sec, 21762052 t fired, .

Time elapsed: 1158 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 110/1273 23/32 Echo-PT-d05r03-CTLFireability-00 2853917 m, 24421 m/sec, 22801551 t fired, .

Time elapsed: 1163 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 115/1273 24/32 Echo-PT-d05r03-CTLFireability-00 2970263 m, 23269 m/sec, 23834567 t fired, .

Time elapsed: 1168 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 120/1273 25/32 Echo-PT-d05r03-CTLFireability-00 3092590 m, 24465 m/sec, 24875560 t fired, .

Time elapsed: 1173 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 125/1273 26/32 Echo-PT-d05r03-CTLFireability-00 3225269 m, 26535 m/sec, 25905492 t fired, .

Time elapsed: 1178 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 130/1273 27/32 Echo-PT-d05r03-CTLFireability-00 3354528 m, 25851 m/sec, 26929561 t fired, .

Time elapsed: 1183 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 135/1273 28/32 Echo-PT-d05r03-CTLFireability-00 3477348 m, 24564 m/sec, 27970593 t fired, .

Time elapsed: 1188 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 140/1273 29/32 Echo-PT-d05r03-CTLFireability-00 3598901 m, 24310 m/sec, 29004007 t fired, .

Time elapsed: 1193 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 145/1273 30/32 Echo-PT-d05r03-CTLFireability-00 3718518 m, 23923 m/sec, 30035323 t fired, .

Time elapsed: 1198 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 150/1273 31/32 Echo-PT-d05r03-CTLFireability-00 3838258 m, 23948 m/sec, 31078553 t fired, .

Time elapsed: 1203 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 155/1273 32/32 Echo-PT-d05r03-CTLFireability-00 3959949 m, 24338 m/sec, 32112075 t fired, .

Time elapsed: 1208 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 160/1273 32/32 Echo-PT-d05r03-CTLFireability-00 4082409 m, 24492 m/sec, 33154023 t fired, .

Time elapsed: 1213 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for Echo-PT-d05r03-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1218 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 Echo-PT-d05r03-CTLFireability-01
lola: time limit : 2382 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/2382 2/32 Echo-PT-d05r03-CTLFireability-01 161061 m, 32212 m/sec, 1047503 t fired, .

Time elapsed: 1223 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/2382 3/32 Echo-PT-d05r03-CTLFireability-01 309389 m, 29665 m/sec, 2109636 t fired, .

Time elapsed: 1228 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/2382 4/32 Echo-PT-d05r03-CTLFireability-01 449785 m, 28079 m/sec, 3174991 t fired, .

Time elapsed: 1233 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/2382 5/32 Echo-PT-d05r03-CTLFireability-01 590099 m, 28062 m/sec, 4235322 t fired, .

Time elapsed: 1238 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/2382 6/32 Echo-PT-d05r03-CTLFireability-01 728805 m, 27741 m/sec, 5305617 t fired, .

Time elapsed: 1243 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/2382 7/32 Echo-PT-d05r03-CTLFireability-01 866855 m, 27610 m/sec, 6365861 t fired, .

Time elapsed: 1248 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/2382 8/32 Echo-PT-d05r03-CTLFireability-01 1008803 m, 28389 m/sec, 7432761 t fired, .

Time elapsed: 1253 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/2382 10/32 Echo-PT-d05r03-CTLFireability-01 1150586 m, 28356 m/sec, 8494329 t fired, .

Time elapsed: 1258 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/2382 11/32 Echo-PT-d05r03-CTLFireability-01 1285351 m, 26953 m/sec, 9554437 t fired, .

Time elapsed: 1263 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 50/2382 12/32 Echo-PT-d05r03-CTLFireability-01 1409222 m, 24774 m/sec, 10629282 t fired, .

Time elapsed: 1268 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 55/2382 13/32 Echo-PT-d05r03-CTLFireability-01 1534433 m, 25042 m/sec, 11695378 t fired, .

Time elapsed: 1273 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 60/2382 14/32 Echo-PT-d05r03-CTLFireability-01 1660093 m, 25132 m/sec, 12765745 t fired, .

Time elapsed: 1278 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 65/2382 14/32 Echo-PT-d05r03-CTLFireability-01 1783966 m, 24774 m/sec, 13839440 t fired, .

Time elapsed: 1283 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 70/2382 15/32 Echo-PT-d05r03-CTLFireability-01 1906266 m, 24460 m/sec, 14901456 t fired, .

Time elapsed: 1288 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 75/2382 16/32 Echo-PT-d05r03-CTLFireability-01 2032292 m, 25205 m/sec, 15975022 t fired, .

Time elapsed: 1293 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 80/2382 17/32 Echo-PT-d05r03-CTLFireability-01 2167505 m, 27042 m/sec, 17036407 t fired, .

Time elapsed: 1298 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 85/2382 19/32 Echo-PT-d05r03-CTLFireability-01 2300482 m, 26595 m/sec, 18093244 t fired, .

Time elapsed: 1303 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 90/2382 20/32 Echo-PT-d05r03-CTLFireability-01 2427290 m, 25361 m/sec, 19163394 t fired, .

Time elapsed: 1308 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 95/2382 20/32 Echo-PT-d05r03-CTLFireability-01 2552034 m, 24948 m/sec, 20225581 t fired, .

Time elapsed: 1313 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 100/2382 21/32 Echo-PT-d05r03-CTLFireability-01 2675957 m, 24784 m/sec, 21288451 t fired, .

Time elapsed: 1318 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 105/2382 22/32 Echo-PT-d05r03-CTLFireability-01 2798332 m, 24475 m/sec, 22363017 t fired, .

Time elapsed: 1323 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 110/2382 23/32 Echo-PT-d05r03-CTLFireability-01 2923541 m, 25041 m/sec, 23428676 t fired, .

Time elapsed: 1328 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 115/2382 24/32 Echo-PT-d05r03-CTLFireability-01 3049299 m, 25151 m/sec, 24499656 t fired, .

Time elapsed: 1333 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 120/2382 25/32 Echo-PT-d05r03-CTLFireability-01 3178079 m, 25756 m/sec, 25565595 t fired, .

Time elapsed: 1338 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 125/2382 26/32 Echo-PT-d05r03-CTLFireability-01 3315423 m, 27468 m/sec, 26619602 t fired, .

Time elapsed: 1343 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 130/2382 27/32 Echo-PT-d05r03-CTLFireability-01 3445243 m, 25964 m/sec, 27688341 t fired, .

Time elapsed: 1348 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 135/2382 28/32 Echo-PT-d05r03-CTLFireability-01 3570665 m, 25084 m/sec, 28756416 t fired, .

Time elapsed: 1353 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 140/2382 29/32 Echo-PT-d05r03-CTLFireability-01 3690516 m, 23970 m/sec, 29818350 t fired, .

Time elapsed: 1358 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 145/2382 30/32 Echo-PT-d05r03-CTLFireability-01 3816888 m, 25274 m/sec, 30893974 t fired, .

Time elapsed: 1363 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 150/2382 31/32 Echo-PT-d05r03-CTLFireability-01 3942315 m, 25085 m/sec, 31960943 t fired, .

Time elapsed: 1368 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 155/2382 32/32 Echo-PT-d05r03-CTLFireability-01 4067208 m, 24978 m/sec, 33024123 t fired, .

Time elapsed: 1373 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for Echo-PT-d05r03-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d05r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Echo-PT-d05r03-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1378 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d05r03-CTLFireability-00: CTL unknown AGGR
Echo-PT-d05r03-CTLFireability-01: CTL unknown AGGR
Echo-PT-d05r03-CTLFireability-02: CTL unknown AGGR
Echo-PT-d05r03-CTLFireability-03: CTL unknown AGGR
Echo-PT-d05r03-CTLFireability-04: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-05: CONJ false state space /EXEF
Echo-PT-d05r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-07: CTL unknown AGGR
Echo-PT-d05r03-CTLFireability-08: EF true findpath
Echo-PT-d05r03-CTLFireability-09: CTL unknown AGGR
Echo-PT-d05r03-CTLFireability-10: CTL unknown AGGR
Echo-PT-d05r03-CTLFireability-11: AXAF false state space /EXEG
Echo-PT-d05r03-CTLFireability-12: CTL unknown AGGR
Echo-PT-d05r03-CTLFireability-13: CTL unknown AGGR
Echo-PT-d05r03-CTLFireability-14: CTL true CTL model checker
Echo-PT-d05r03-CTLFireability-15: CTL unknown AGGR


Time elapsed: 1378 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Echo-PT-d05r03"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is Echo-PT-d05r03, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851200114"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Echo-PT-d05r03.tgz
mv Echo-PT-d05r03 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;