About the Execution of LoLa+red for DoubleLock-PT-p3s1
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4999.415 | 176967.00 | 332965.00 | 1075.30 | TFF?T?FF??TT?F?T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r135-smll-167819414700546.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DoubleLock-PT-p3s1, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819414700546
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 404K
-rw-r--r-- 1 mcc users 6.7K Feb 25 14:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 14:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 14:21 CTLFireability.txt
-rw-r--r-- 1 mcc users 28K Feb 25 14:21 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 14:23 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 112K Feb 25 14:23 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 14:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 14:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 39K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678404028302
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p3s1
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 23:20:31] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 23:20:31] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 23:20:31] [INFO ] Load time of PNML (sax parser for PT used): 59 ms
[2023-03-09 23:20:31] [INFO ] Transformed 46 places.
[2023-03-09 23:20:31] [INFO ] Transformed 80 transitions.
[2023-03-09 23:20:31] [INFO ] Parsed PT model containing 46 places and 80 transitions and 324 arcs in 187 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Deduced a syphon composed of 6 places in 2 ms
Reduce places removed 6 places and 4 transitions.
FORMULA DoubleLock-PT-p3s1-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 29 out of 40 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 40/40 places, 76/76 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 37 transition count 76
Applied a total of 3 rules in 18 ms. Remains 37 /40 variables (removed 3) and now considering 76/76 (removed 0) transitions.
[2023-03-09 23:20:31] [INFO ] Flow matrix only has 61 transitions (discarded 15 similar events)
// Phase 1: matrix 61 rows 37 cols
[2023-03-09 23:20:31] [INFO ] Computed 2 place invariants in 9 ms
[2023-03-09 23:20:31] [INFO ] Implicit Places using invariants in 212 ms returned []
[2023-03-09 23:20:31] [INFO ] Flow matrix only has 61 transitions (discarded 15 similar events)
[2023-03-09 23:20:31] [INFO ] Invariant cache hit.
[2023-03-09 23:20:32] [INFO ] State equation strengthened by 12 read => feed constraints.
[2023-03-09 23:20:32] [INFO ] Implicit Places using invariants and state equation in 149 ms returned []
Implicit Place search using SMT with State Equation took 402 ms to find 0 implicit places.
[2023-03-09 23:20:32] [INFO ] Flow matrix only has 61 transitions (discarded 15 similar events)
[2023-03-09 23:20:32] [INFO ] Invariant cache hit.
[2023-03-09 23:20:32] [INFO ] Dead Transitions using invariants and state equation in 98 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 37/40 places, 76/76 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 522 ms. Remains : 37/40 places, 76/76 transitions.
Support contains 29 out of 37 places after structural reductions.
[2023-03-09 23:20:32] [INFO ] Flatten gal took : 38 ms
[2023-03-09 23:20:32] [INFO ] Flatten gal took : 19 ms
[2023-03-09 23:20:32] [INFO ] Input system was already deterministic with 76 transitions.
Incomplete random walk after 10000 steps, including 61 resets, run finished after 387 ms. (steps per millisecond=25 ) properties (out of 40) seen :38
Incomplete Best-First random walk after 10001 steps, including 10 resets, run finished after 91 ms. (steps per millisecond=109 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 94 ms. (steps per millisecond=106 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-09 23:20:33] [INFO ] Flow matrix only has 61 transitions (discarded 15 similar events)
[2023-03-09 23:20:33] [INFO ] Invariant cache hit.
[2023-03-09 23:20:33] [INFO ] [Real]Absence check using 1 positive place invariants in 8 ms returned sat
[2023-03-09 23:20:33] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-09 23:20:33] [INFO ] After 111ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 15 simplifications.
[2023-03-09 23:20:33] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 11 ms
FORMULA DoubleLock-PT-p3s1-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DoubleLock-PT-p3s1-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 12 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Computed a total of 3 stabilizing places and 8 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 14 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 7 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 8 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 7 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 7 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 6 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 7 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 2 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 5 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 5 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 5 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Finished random walk after 203 steps, including 2 resets, run visited all 1 properties in 1 ms. (steps per millisecond=203 )
FORMULA DoubleLock-PT-p3s1-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 5 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 5 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 5 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 5 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 2 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 5 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 2 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 5 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 2 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 4 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 76/76 transitions.
Applied a total of 0 rules in 5 ms. Remains 37 /37 variables (removed 0) and now considering 76/76 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 37/37 places, 76/76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 5 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Input system was already deterministic with 76 transitions.
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 6 ms
[2023-03-09 23:20:33] [INFO ] Flatten gal took : 5 ms
[2023-03-09 23:20:33] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-09 23:20:33] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 37 places, 76 transitions and 304 arcs took 1 ms.
Total runtime 2449 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DoubleLock-PT-p3s1
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA DoubleLock-PT-p3s1-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s1-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s1-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s1-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s1-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s1-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678404205269
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 50 (type EXCL) for 6 DoubleLock-PT-p3s1-CTLFireability-02
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 50 (type EXCL) for DoubleLock-PT-p3s1-CTLFireability-02
lola: result : true
lola: markings : 24
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 DoubleLock-PT-p3s1-CTLFireability-03
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 48 (type FNDP) for 0 DoubleLock-PT-p3s1-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 0 DoubleLock-PT-p3s1-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SRCH) for 0 DoubleLock-PT-p3s1-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 52 (type SRCH) for DoubleLock-PT-p3s1-CTLFireability-00
lola: result : true
lola: markings : 42
lola: fired transitions : 42
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 48 (type FNDP) for DoubleLock-PT-p3s1-CTLFireability-00 (obsolete)
lola: CANCELED task # 49 (type EQUN) for DoubleLock-PT-p3s1-CTLFireability-00 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/375/CTLFireability-49.sara.
lola: FINISHED task # 48 (type FNDP) for DoubleLock-PT-p3s1-CTLFireability-00
lola: result : true
lola: fired transitions : 151
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:714
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
DoubleLock-PT-p3s1-CTLFireability-02: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DoubleLock-PT-p3s1-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s1-CTLFireability-13: AGEF 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/276 8/32 DoubleLock-PT-p3s1-CTLFireability-03 1715057 m, 343011 m/sec, 2130822 t fired, .
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10 CTL EXCL 10/276 15/32 DoubleLock-PT-p3s1-CTLFireability-03 3476884 m, 352365 m/sec, 4319759 t fired, .
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10 CTL EXCL 15/276 22/32 DoubleLock-PT-p3s1-CTLFireability-03 5257036 m, 356030 m/sec, 6531463 t fired, .
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10 CTL EXCL 20/276 29/32 DoubleLock-PT-p3s1-CTLFireability-03 6982852 m, 345163 m/sec, 8675659 t fired, .
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DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
DoubleLock-PT-p3s1-CTLFireability-02: F false state space / EG
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
DoubleLock-PT-p3s1-CTLFireability-02: F false state space / EG
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DoubleLock-PT-p3s1-CTLFireability-13: AGEF 0 1 0 0 1 0 0 0
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DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
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lola: result : true
lola: markings : 607
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DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
DoubleLock-PT-p3s1-CTLFireability-02: F false state space / EG
DoubleLock-PT-p3s1-CTLFireability-10: CTL true CTL model checker
DoubleLock-PT-p3s1-CTLFireability-11: CONJ true CONJ
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DoubleLock-PT-p3s1-CTLFireability-10: CTL true CTL model checker
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16 CTL EXCL 10/507 12/32 DoubleLock-PT-p3s1-CTLFireability-08 2706818 m, 259111 m/sec, 6069826 t fired, .
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DoubleLock-PT-p3s1-CTLFireability-10: CTL true CTL model checker
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16 CTL EXCL 20/507 22/32 DoubleLock-PT-p3s1-CTLFireability-08 5234202 m, 251316 m/sec, 11737295 t fired, .
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lola: LAUNCH task # 4 (type EXCL) for 3 DoubleLock-PT-p3s1-CTLFireability-01
lola: time limit : 1724 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for DoubleLock-PT-p3s1-CTLFireability-01
lola: result : false
lola: markings : 19
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 DoubleLock-PT-p3s1-CTLFireability-14
lola: time limit : 3449 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
DoubleLock-PT-p3s1-CTLFireability-01: CTL false CTL model checker
DoubleLock-PT-p3s1-CTLFireability-02: F false state space / EG
DoubleLock-PT-p3s1-CTLFireability-10: CTL true CTL model checker
DoubleLock-PT-p3s1-CTLFireability-11: CONJ true CONJ
DoubleLock-PT-p3s1-CTLFireability-13: AGEF false tscc_search
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
DoubleLock-PT-p3s1-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/3449 9/32 DoubleLock-PT-p3s1-CTLFireability-14 2127083 m, 425416 m/sec, 2707189 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
DoubleLock-PT-p3s1-CTLFireability-01: CTL false CTL model checker
DoubleLock-PT-p3s1-CTLFireability-02: F false state space / EG
DoubleLock-PT-p3s1-CTLFireability-10: CTL true CTL model checker
DoubleLock-PT-p3s1-CTLFireability-11: CONJ true CONJ
DoubleLock-PT-p3s1-CTLFireability-13: AGEF false tscc_search
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
DoubleLock-PT-p3s1-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/3449 17/32 DoubleLock-PT-p3s1-CTLFireability-14 4065802 m, 387743 m/sec, 5174650 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
DoubleLock-PT-p3s1-CTLFireability-01: CTL false CTL model checker
DoubleLock-PT-p3s1-CTLFireability-02: F false state space / EG
DoubleLock-PT-p3s1-CTLFireability-10: CTL true CTL model checker
DoubleLock-PT-p3s1-CTLFireability-11: CONJ true CONJ
DoubleLock-PT-p3s1-CTLFireability-13: AGEF false tscc_search
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
DoubleLock-PT-p3s1-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/3449 25/32 DoubleLock-PT-p3s1-CTLFireability-14 5986376 m, 384114 m/sec, 7619019 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
DoubleLock-PT-p3s1-CTLFireability-01: CTL false CTL model checker
DoubleLock-PT-p3s1-CTLFireability-02: F false state space / EG
DoubleLock-PT-p3s1-CTLFireability-10: CTL true CTL model checker
DoubleLock-PT-p3s1-CTLFireability-11: CONJ true CONJ
DoubleLock-PT-p3s1-CTLFireability-13: AGEF false tscc_search
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s1-CTLFireability-12: DISJ 0 0 0 0 2 0 2 0
DoubleLock-PT-p3s1-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s1-CTLFireability-00: EF true search / frozen tokens
DoubleLock-PT-p3s1-CTLFireability-01: CTL false CTL model checker
DoubleLock-PT-p3s1-CTLFireability-02: F false state space / EG
DoubleLock-PT-p3s1-CTLFireability-03: CTL unknown AGGR
DoubleLock-PT-p3s1-CTLFireability-05: CTL unknown AGGR
DoubleLock-PT-p3s1-CTLFireability-08: CTL unknown AGGR
DoubleLock-PT-p3s1-CTLFireability-09: CTL unknown AGGR
DoubleLock-PT-p3s1-CTLFireability-10: CTL true CTL model checker
DoubleLock-PT-p3s1-CTLFireability-11: CONJ true CONJ
DoubleLock-PT-p3s1-CTLFireability-12: DISJ unknown DISJ
DoubleLock-PT-p3s1-CTLFireability-13: AGEF false tscc_search
DoubleLock-PT-p3s1-CTLFireability-14: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p3s1"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DoubleLock-PT-p3s1, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819414700546"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p3s1.tgz
mv DoubleLock-PT-p3s1 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;