Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r135-smll-167819414700538.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DoubleLock-PT-p2s2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819414700538
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.3K Feb 25 14:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 14:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 14:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 14:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.0K Feb 25 14:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 67K Feb 25 14:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 25 14:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 25 14:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 813K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678399664453

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p2s2
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 22:07:46] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 22:07:46] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 22:07:47] [INFO ] Load time of PNML (sax parser for PT used): 277 ms
[2023-03-09 22:07:47] [INFO ] Transformed 184 places.
[2023-03-09 22:07:47] [INFO ] Transformed 1832 transitions.
[2023-03-09 22:07:47] [INFO ] Parsed PT model containing 184 places and 1832 transitions and 7424 arcs in 408 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 15 ms.
Deduced a syphon composed of 36 places in 10 ms
Reduce places removed 36 places and 64 transitions.
FORMULA DoubleLock-PT-p2s2-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 89 out of 148 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 148/148 places, 1768/1768 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 144 transition count 1768
Applied a total of 4 rules in 41 ms. Remains 144 /148 variables (removed 4) and now considering 1768/1768 (removed 0) transitions.
[2023-03-09 22:07:47] [INFO ] Flow matrix only has 1225 transitions (discarded 543 similar events)
// Phase 1: matrix 1225 rows 144 cols
[2023-03-09 22:07:47] [INFO ] Computed 2 place invariants in 53 ms
[2023-03-09 22:07:47] [INFO ] Implicit Places using invariants in 428 ms returned []
[2023-03-09 22:07:47] [INFO ] Flow matrix only has 1225 transitions (discarded 543 similar events)
[2023-03-09 22:07:47] [INFO ] Invariant cache hit.
[2023-03-09 22:07:48] [INFO ] State equation strengthened by 116 read => feed constraints.
[2023-03-09 22:07:49] [INFO ] Implicit Places using invariants and state equation in 1197 ms returned []
Implicit Place search using SMT with State Equation took 1665 ms to find 0 implicit places.
[2023-03-09 22:07:49] [INFO ] Flow matrix only has 1225 transitions (discarded 543 similar events)
[2023-03-09 22:07:49] [INFO ] Invariant cache hit.
[2023-03-09 22:07:50] [INFO ] Dead Transitions using invariants and state equation in 868 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 144/148 places, 1768/1768 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2581 ms. Remains : 144/148 places, 1768/1768 transitions.
Support contains 89 out of 144 places after structural reductions.
[2023-03-09 22:07:50] [INFO ] Flatten gal took : 296 ms
[2023-03-09 22:07:50] [INFO ] Flatten gal took : 170 ms
[2023-03-09 22:07:51] [INFO ] Input system was already deterministic with 1768 transitions.
Incomplete random walk after 10007 steps, including 100 resets, run finished after 408 ms. (steps per millisecond=24 ) properties (out of 71) seen :25
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 46) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 46) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 45) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 44) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 42) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 40) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 40) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 40) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 40) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 40) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 40) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 40) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 39) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 38) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 37) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 36) seen :0
Running SMT prover for 36 properties.
[2023-03-09 22:07:51] [INFO ] Flow matrix only has 1225 transitions (discarded 543 similar events)
[2023-03-09 22:07:51] [INFO ] Invariant cache hit.
[2023-03-09 22:07:52] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:07:52] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-09 22:07:53] [INFO ] After 1173ms SMT Verify possible using all constraints in real domain returned unsat :6 sat :0 real:30
[2023-03-09 22:07:53] [INFO ] [Nat]Absence check using 1 positive place invariants in 2 ms returned sat
[2023-03-09 22:07:53] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:07:55] [INFO ] After 1768ms SMT Verify possible using state equation in natural domain returned unsat :13 sat :23
[2023-03-09 22:07:55] [INFO ] State equation strengthened by 116 read => feed constraints.
[2023-03-09 22:07:57] [INFO ] After 1953ms SMT Verify possible using 116 Read/Feed constraints in natural domain returned unsat :13 sat :23
[2023-03-09 22:07:59] [INFO ] After 3701ms SMT Verify possible using trap constraints in natural domain returned unsat :13 sat :23
Attempting to minimize the solution found.
Minimization took 1459 ms.
[2023-03-09 22:08:00] [INFO ] After 7253ms SMT Verify possible using all constraints in natural domain returned unsat :13 sat :23
Fused 36 Parikh solutions to 23 different solutions.
Parikh walk visited 0 properties in 328 ms.
Support contains 32 out of 144 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Drop transitions removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 144 transition count 1758
Applied a total of 10 rules in 94 ms. Remains 144 /144 variables (removed 0) and now considering 1758/1768 (removed 10) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 95 ms. Remains : 144/144 places, 1758/1768 transitions.
Incomplete random walk after 10000 steps, including 102 resets, run finished after 203 ms. (steps per millisecond=49 ) properties (out of 23) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 22) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 21) seen :0
Interrupted probabilistic random walk after 99297 steps, run timeout after 3001 ms. (steps per millisecond=33 ) properties seen :{3=1, 7=1, 17=1}
Probabilistic random walk after 99297 steps, saw 70505 distinct states, run finished after 3002 ms. (steps per millisecond=33 ) properties seen :3
Running SMT prover for 18 properties.
[2023-03-09 22:08:04] [INFO ] Flow matrix only has 1215 transitions (discarded 543 similar events)
// Phase 1: matrix 1215 rows 144 cols
[2023-03-09 22:08:04] [INFO ] Computed 2 place invariants in 25 ms
[2023-03-09 22:08:04] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:04] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-09 22:08:05] [INFO ] After 733ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:18
[2023-03-09 22:08:05] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:05] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:08:06] [INFO ] After 1394ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :18
[2023-03-09 22:08:06] [INFO ] State equation strengthened by 116 read => feed constraints.
[2023-03-09 22:08:08] [INFO ] After 1630ms SMT Verify possible using 116 Read/Feed constraints in natural domain returned unsat :0 sat :18
[2023-03-09 22:08:09] [INFO ] After 2929ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :18
Attempting to minimize the solution found.
Minimization took 1032 ms.
[2023-03-09 22:08:10] [INFO ] After 5550ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :18
Parikh walk visited 0 properties in 192 ms.
Support contains 26 out of 144 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 144/144 places, 1758/1758 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 144 transition count 1756
Applied a total of 2 rules in 63 ms. Remains 144 /144 variables (removed 0) and now considering 1756/1758 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 63 ms. Remains : 144/144 places, 1756/1758 transitions.
Incomplete random walk after 10009 steps, including 106 resets, run finished after 252 ms. (steps per millisecond=39 ) properties (out of 18) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0
Interrupted probabilistic random walk after 101699 steps, run timeout after 3001 ms. (steps per millisecond=33 ) properties seen :{}
Probabilistic random walk after 101699 steps, saw 72217 distinct states, run finished after 3002 ms. (steps per millisecond=33 ) properties seen :0
Running SMT prover for 17 properties.
[2023-03-09 22:08:14] [INFO ] Flow matrix only has 1213 transitions (discarded 543 similar events)
// Phase 1: matrix 1213 rows 144 cols
[2023-03-09 22:08:14] [INFO ] Computed 2 place invariants in 15 ms
[2023-03-09 22:08:14] [INFO ] [Real]Absence check using 1 positive place invariants in 0 ms returned sat
[2023-03-09 22:08:14] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:08:15] [INFO ] After 747ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:17
[2023-03-09 22:08:15] [INFO ] [Nat]Absence check using 1 positive place invariants in 2 ms returned sat
[2023-03-09 22:08:15] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-09 22:08:16] [INFO ] After 1641ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :17
[2023-03-09 22:08:16] [INFO ] State equation strengthened by 116 read => feed constraints.
[2023-03-09 22:08:18] [INFO ] After 1464ms SMT Verify possible using 116 Read/Feed constraints in natural domain returned unsat :0 sat :17
[2023-03-09 22:08:19] [INFO ] After 2752ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :17
Attempting to minimize the solution found.
Minimization took 1171 ms.
[2023-03-09 22:08:20] [INFO ] After 5775ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :17
Parikh walk visited 0 properties in 174 ms.
Support contains 24 out of 144 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 144/144 places, 1756/1756 transitions.
Applied a total of 0 rules in 63 ms. Remains 144 /144 variables (removed 0) and now considering 1756/1756 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 63 ms. Remains : 144/144 places, 1756/1756 transitions.
Incomplete random walk after 10001 steps, including 103 resets, run finished after 248 ms. (steps per millisecond=40 ) properties (out of 17) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Interrupted probabilistic random walk after 103678 steps, run timeout after 3001 ms. (steps per millisecond=34 ) properties seen :{}
Probabilistic random walk after 103678 steps, saw 73630 distinct states, run finished after 3001 ms. (steps per millisecond=34 ) properties seen :0
Running SMT prover for 16 properties.
[2023-03-09 22:08:24] [INFO ] Flow matrix only has 1213 transitions (discarded 543 similar events)
[2023-03-09 22:08:24] [INFO ] Invariant cache hit.
[2023-03-09 22:08:24] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:24] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:08:25] [INFO ] After 735ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:16
[2023-03-09 22:08:25] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:25] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:08:26] [INFO ] After 1252ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :16
[2023-03-09 22:08:26] [INFO ] State equation strengthened by 116 read => feed constraints.
[2023-03-09 22:08:28] [INFO ] After 1373ms SMT Verify possible using 116 Read/Feed constraints in natural domain returned unsat :0 sat :16
[2023-03-09 22:08:29] [INFO ] After 2491ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :16
Attempting to minimize the solution found.
Minimization took 991 ms.
[2023-03-09 22:08:30] [INFO ] After 4901ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :16
Parikh walk visited 0 properties in 141 ms.
Support contains 23 out of 144 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 144/144 places, 1756/1756 transitions.
Applied a total of 0 rules in 49 ms. Remains 144 /144 variables (removed 0) and now considering 1756/1756 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 49 ms. Remains : 144/144 places, 1756/1756 transitions.
Incomplete random walk after 10002 steps, including 99 resets, run finished after 177 ms. (steps per millisecond=56 ) properties (out of 16) seen :2
Incomplete Best-First random walk after 10000 steps, including 18 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10000 steps, including 18 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 22 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 18 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10000 steps, including 17 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 20 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 14 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 14) seen :1
Incomplete Best-First random walk after 10001 steps, including 16 resets, run finished after 64 ms. (steps per millisecond=156 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 16 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 18 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 13) seen :1
Incomplete Best-First random walk after 10001 steps, including 17 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 12) seen :2
Running SMT prover for 10 properties.
[2023-03-09 22:08:31] [INFO ] Flow matrix only has 1213 transitions (discarded 543 similar events)
[2023-03-09 22:08:31] [INFO ] Invariant cache hit.
[2023-03-09 22:08:31] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:31] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:08:31] [INFO ] After 591ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:10
[2023-03-09 22:08:31] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:31] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:08:32] [INFO ] After 773ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :10
[2023-03-09 22:08:32] [INFO ] State equation strengthened by 116 read => feed constraints.
[2023-03-09 22:08:33] [INFO ] After 1145ms SMT Verify possible using 116 Read/Feed constraints in natural domain returned unsat :0 sat :10
[2023-03-09 22:08:34] [INFO ] After 1789ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :10
Attempting to minimize the solution found.
Minimization took 480 ms.
[2023-03-09 22:08:35] [INFO ] After 3158ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :10
Parikh walk visited 0 properties in 62 ms.
Support contains 15 out of 144 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 144/144 places, 1756/1756 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 144 transition count 1754
Applied a total of 2 rules in 36 ms. Remains 144 /144 variables (removed 0) and now considering 1754/1756 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 37 ms. Remains : 144/144 places, 1754/1756 transitions.
Incomplete random walk after 10001 steps, including 100 resets, run finished after 104 ms. (steps per millisecond=96 ) properties (out of 10) seen :1
Incomplete Best-First random walk after 10001 steps, including 17 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 19 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 20 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 19 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 17 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 17 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 18 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 19 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 19 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 9) seen :1
Running SMT prover for 8 properties.
[2023-03-09 22:08:35] [INFO ] Flow matrix only has 1211 transitions (discarded 543 similar events)
// Phase 1: matrix 1211 rows 144 cols
[2023-03-09 22:08:35] [INFO ] Computed 2 place invariants in 7 ms
[2023-03-09 22:08:35] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:35] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:08:36] [INFO ] After 767ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:8
[2023-03-09 22:08:36] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:36] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:08:37] [INFO ] After 664ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :8
[2023-03-09 22:08:37] [INFO ] State equation strengthened by 116 read => feed constraints.
[2023-03-09 22:08:38] [INFO ] After 1080ms SMT Verify possible using 116 Read/Feed constraints in natural domain returned unsat :0 sat :8
[2023-03-09 22:08:38] [INFO ] After 1624ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :8
Attempting to minimize the solution found.
Minimization took 526 ms.
[2023-03-09 22:08:39] [INFO ] After 2911ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :8
Parikh walk visited 0 properties in 87 ms.
Support contains 12 out of 144 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 144/144 places, 1754/1754 transitions.
Applied a total of 0 rules in 33 ms. Remains 144 /144 variables (removed 0) and now considering 1754/1754 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 33 ms. Remains : 144/144 places, 1754/1754 transitions.
Incomplete random walk after 10006 steps, including 106 resets, run finished after 139 ms. (steps per millisecond=71 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 17 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 18 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10000 steps, including 21 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10000 steps, including 19 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 18 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 18 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 8) seen :0
Interrupted probabilistic random walk after 162202 steps, run timeout after 3001 ms. (steps per millisecond=54 ) properties seen :{}
Probabilistic random walk after 162202 steps, saw 112937 distinct states, run finished after 3001 ms. (steps per millisecond=54 ) properties seen :0
Running SMT prover for 8 properties.
[2023-03-09 22:08:42] [INFO ] Flow matrix only has 1211 transitions (discarded 543 similar events)
[2023-03-09 22:08:42] [INFO ] Invariant cache hit.
[2023-03-09 22:08:42] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:42] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-09 22:08:43] [INFO ] After 732ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:8
[2023-03-09 22:08:43] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:43] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-09 22:08:44] [INFO ] After 668ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :8
[2023-03-09 22:08:44] [INFO ] State equation strengthened by 116 read => feed constraints.
[2023-03-09 22:08:45] [INFO ] After 1023ms SMT Verify possible using 116 Read/Feed constraints in natural domain returned unsat :0 sat :8
[2023-03-09 22:08:45] [INFO ] After 1562ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :8
Attempting to minimize the solution found.
Minimization took 520 ms.
[2023-03-09 22:08:46] [INFO ] After 2848ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :8
Parikh walk visited 0 properties in 50 ms.
Support contains 12 out of 144 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 144/144 places, 1754/1754 transitions.
Applied a total of 0 rules in 29 ms. Remains 144 /144 variables (removed 0) and now considering 1754/1754 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 29 ms. Remains : 144/144 places, 1754/1754 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 144/144 places, 1754/1754 transitions.
Applied a total of 0 rules in 27 ms. Remains 144 /144 variables (removed 0) and now considering 1754/1754 (removed 0) transitions.
[2023-03-09 22:08:46] [INFO ] Flow matrix only has 1211 transitions (discarded 543 similar events)
[2023-03-09 22:08:46] [INFO ] Invariant cache hit.
[2023-03-09 22:08:46] [INFO ] Implicit Places using invariants in 221 ms returned []
[2023-03-09 22:08:46] [INFO ] Flow matrix only has 1211 transitions (discarded 543 similar events)
[2023-03-09 22:08:46] [INFO ] Invariant cache hit.
[2023-03-09 22:08:46] [INFO ] State equation strengthened by 116 read => feed constraints.
[2023-03-09 22:08:47] [INFO ] Implicit Places using invariants and state equation in 1110 ms returned []
Implicit Place search using SMT with State Equation took 1354 ms to find 0 implicit places.
[2023-03-09 22:08:47] [INFO ] Redundant transitions in 134 ms returned []
[2023-03-09 22:08:47] [INFO ] Flow matrix only has 1211 transitions (discarded 543 similar events)
[2023-03-09 22:08:47] [INFO ] Invariant cache hit.
[2023-03-09 22:08:48] [INFO ] Dead Transitions using invariants and state equation in 903 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2427 ms. Remains : 144/144 places, 1754/1754 transitions.
Ensure Unique test removed 543 transitions
Reduce isomorphic transitions removed 543 transitions.
Iterating post reduction 0 with 543 rules applied. Total rules applied 543 place count 144 transition count 1211
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 1 with 7 Pre rules applied. Total rules applied 543 place count 144 transition count 1204
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 1 with 14 rules applied. Total rules applied 557 place count 137 transition count 1204
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 1 with 4 rules applied. Total rules applied 561 place count 135 transition count 1202
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 562 place count 134 transition count 1170
Iterating global reduction 1 with 1 rules applied. Total rules applied 563 place count 134 transition count 1170
Applied a total of 563 rules in 55 ms. Remains 134 /144 variables (removed 10) and now considering 1170/1754 (removed 584) transitions.
Running SMT prover for 8 properties.
// Phase 1: matrix 1170 rows 134 cols
[2023-03-09 22:08:48] [INFO ] Computed 2 place invariants in 7 ms
[2023-03-09 22:08:49] [INFO ] [Real]Absence check using 1 positive place invariants in 0 ms returned sat
[2023-03-09 22:08:49] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 22:08:49] [INFO ] After 673ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:8
[2023-03-09 22:08:49] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 22:08:49] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 4 ms returned sat
[2023-03-09 22:08:50] [INFO ] After 605ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :8
[2023-03-09 22:08:50] [INFO ] After 1032ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :8
Attempting to minimize the solution found.
Minimization took 286 ms.
[2023-03-09 22:08:51] [INFO ] After 1408ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :8
Successfully simplified 13 atomic propositions for a total of 15 simplifications.
[2023-03-09 22:08:51] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 22:08:51] [INFO ] Flatten gal took : 127 ms
FORMULA DoubleLock-PT-p2s2-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 22:08:51] [INFO ] Flatten gal took : 86 ms
[2023-03-09 22:08:51] [INFO ] Input system was already deterministic with 1768 transitions.
Support contains 71 out of 144 places (down from 72) after GAL structural reductions.
Computed a total of 8 stabilizing places and 416 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Applied a total of 0 rules in 5 ms. Remains 144 /144 variables (removed 0) and now considering 1768/1768 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 144/144 places, 1768/1768 transitions.
[2023-03-09 22:08:51] [INFO ] Flatten gal took : 61 ms
[2023-03-09 22:08:51] [INFO ] Flatten gal took : 67 ms
[2023-03-09 22:08:51] [INFO ] Input system was already deterministic with 1768 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 68 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 69 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:51] [INFO ] Flatten gal took : 57 ms
[2023-03-09 22:08:52] [INFO ] Flatten gal took : 64 ms
[2023-03-09 22:08:52] [INFO ] Input system was already deterministic with 1736 transitions.
Incomplete random walk after 10005 steps, including 103 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 1) seen :0
Finished Best-First random walk after 3379 steps, including 5 resets, run visited all 1 properties in 4 ms. (steps per millisecond=844 )
FORMULA DoubleLock-PT-p2s2-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 13 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:52] [INFO ] Flatten gal took : 58 ms
[2023-03-09 22:08:52] [INFO ] Flatten gal took : 70 ms
[2023-03-09 22:08:52] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 12 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:52] [INFO ] Flatten gal took : 52 ms
[2023-03-09 22:08:52] [INFO ] Flatten gal took : 61 ms
[2023-03-09 22:08:52] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 11 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:52] [INFO ] Flatten gal took : 49 ms
[2023-03-09 22:08:52] [INFO ] Flatten gal took : 58 ms
[2023-03-09 22:08:53] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Applied a total of 0 rules in 5 ms. Remains 144 /144 variables (removed 0) and now considering 1768/1768 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 144/144 places, 1768/1768 transitions.
[2023-03-09 22:08:53] [INFO ] Flatten gal took : 48 ms
[2023-03-09 22:08:53] [INFO ] Flatten gal took : 57 ms
[2023-03-09 22:08:53] [INFO ] Input system was already deterministic with 1768 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 11 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:53] [INFO ] Flatten gal took : 41 ms
[2023-03-09 22:08:53] [INFO ] Flatten gal took : 49 ms
[2023-03-09 22:08:53] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 10 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:53] [INFO ] Flatten gal took : 42 ms
[2023-03-09 22:08:53] [INFO ] Flatten gal took : 49 ms
[2023-03-09 22:08:53] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 10 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:53] [INFO ] Flatten gal took : 41 ms
[2023-03-09 22:08:53] [INFO ] Flatten gal took : 45 ms
[2023-03-09 22:08:53] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 10 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 41 ms
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 48 ms
[2023-03-09 22:08:54] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 11 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 39 ms
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 48 ms
[2023-03-09 22:08:54] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 9 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 39 ms
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 47 ms
[2023-03-09 22:08:54] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 143 transition count 1736
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 143 transition count 1736
Applied a total of 2 rules in 8 ms. Remains 143 /144 variables (removed 1) and now considering 1736/1768 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 143/144 places, 1736/1768 transitions.
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 40 ms
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 46 ms
[2023-03-09 22:08:54] [INFO ] Input system was already deterministic with 1736 transitions.
Starting structural reductions in LTL mode, iteration 0 : 144/144 places, 1768/1768 transitions.
Applied a total of 0 rules in 4 ms. Remains 144 /144 variables (removed 0) and now considering 1768/1768 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 144/144 places, 1768/1768 transitions.
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 39 ms
[2023-03-09 22:08:54] [INFO ] Flatten gal took : 47 ms
[2023-03-09 22:08:55] [INFO ] Input system was already deterministic with 1768 transitions.
[2023-03-09 22:08:55] [INFO ] Flatten gal took : 45 ms
[2023-03-09 22:08:55] [INFO ] Flatten gal took : 47 ms
[2023-03-09 22:08:55] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-09 22:08:55] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 144 places, 1768 transitions and 7040 arcs took 13 ms.
Total runtime 68241 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DoubleLock-PT-p2s2
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA DoubleLock-PT-p2s2-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p2s2-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p2s2-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p2s2-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p2s2-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p2s2-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p2s2-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p2s2-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p2s2-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678399891954

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 51 (type EXCL) for 3 DoubleLock-PT-p2s2-CTLFireability-02
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 51 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-02
lola: result : true
lola: markings : 63
lola: fired transitions : 62
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 DoubleLock-PT-p2s2-CTLFireability-15
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-15
lola: result : true
lola: markings : 33
lola: fired transitions : 67
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 DoubleLock-PT-p2s2-CTLFireability-14
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 53 (type FNDP) for 18 DoubleLock-PT-p2s2-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 18 DoubleLock-PT-p2s2-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type SRCH) for 18 DoubleLock-PT-p2s2-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: try reading problem file /home/mcc/execution/373/CTLFireability-54.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 4/257 4/32 DoubleLock-PT-p2s2-CTLFireability-14 632970 m, 126594 m/sec, 769751 t fired, .
53 EF FNDP 4/1198 0/5 DoubleLock-PT-p2s2-CTLFireability-08 38058 t fired, 471 attempts, .
54 EF STEQ 4/1198 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
56 EF SRCH 4/1198 1/5 DoubleLock-PT-p2s2-CTLFireability-08 58708 m, 11741 m/sec, 58794 t fired, .

Time elapsed: 5 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 9/257 9/32 DoubleLock-PT-p2s2-CTLFireability-14 1439548 m, 161315 m/sec, 1750725 t fired, .
53 EF FNDP 9/1195 0/5 DoubleLock-PT-p2s2-CTLFireability-08 87352 t fired, 1124 attempts, .
54 EF STEQ 9/1195 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
56 EF SRCH 9/1195 1/5 DoubleLock-PT-p2s2-CTLFireability-08 133565 m, 14971 m/sec, 133651 t fired, .

Time elapsed: 10 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 14/257 14/32 DoubleLock-PT-p2s2-CTLFireability-14 2242395 m, 160569 m/sec, 2727160 t fired, .
53 EF FNDP 14/1190 0/5 DoubleLock-PT-p2s2-CTLFireability-08 136830 t fired, 1877 attempts, .
54 EF STEQ 14/1190 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
56 EF SRCH 14/1190 2/5 DoubleLock-PT-p2s2-CTLFireability-08 207999 m, 14886 m/sec, 208085 t fired, .

Time elapsed: 15 secs. Pages in use: 16
# running tasks: 4 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 19/257 19/32 DoubleLock-PT-p2s2-CTLFireability-14 3041652 m, 159851 m/sec, 3699229 t fired, .
53 EF FNDP 19/1185 0/5 DoubleLock-PT-p2s2-CTLFireability-08 186675 t fired, 2708 attempts, .
54 EF STEQ 19/1185 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
56 EF SRCH 19/1185 2/5 DoubleLock-PT-p2s2-CTLFireability-08 282350 m, 14870 m/sec, 282436 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 24/257 24/32 DoubleLock-PT-p2s2-CTLFireability-14 3836687 m, 159007 m/sec, 4666164 t fired, .
53 EF FNDP 24/1180 0/5 DoubleLock-PT-p2s2-CTLFireability-08 236113 t fired, 3464 attempts, .
54 EF STEQ 24/1180 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
56 EF SRCH 24/1180 3/5 DoubleLock-PT-p2s2-CTLFireability-08 356639 m, 14857 m/sec, 356725 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 29/257 29/32 DoubleLock-PT-p2s2-CTLFireability-14 4626680 m, 157998 m/sec, 5626968 t fired, .
53 EF FNDP 29/1175 0/5 DoubleLock-PT-p2s2-CTLFireability-08 285674 t fired, 4225 attempts, .
54 EF STEQ 29/1175 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
56 EF SRCH 29/1175 3/5 DoubleLock-PT-p2s2-CTLFireability-08 431254 m, 14923 m/sec, 431340 t fired, .

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lola: CANCELED task # 46 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-14 (memory limit exceeded)
lola: FINISHED task # 53 (type FNDP) for DoubleLock-PT-p2s2-CTLFireability-08
lola: result : true
lola: fired transitions : 335008
lola: tried executions : 5019
lola: time used : 34.000000
lola: memory pages used : 0
lola: CANCELED task # 54 (type EQUN) for DoubleLock-PT-p2s2-CTLFireability-08 (obsolete)
lola: CANCELED task # 56 (type SRCH) for DoubleLock-PT-p2s2-CTLFireability-08 (obsolete)
lola: LAUNCH task # 43 (type EXCL) for 42 DoubleLock-PT-p2s2-CTLFireability-13
lola: time limit : 396 sec
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lola: LAUNCH task # 57 (type FNDP) for 33 DoubleLock-PT-p2s2-CTLFireability-09
lola: time limit : 32000000 sec
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lola: LAUNCH task # 59 (type EQUN) for 33 DoubleLock-PT-p2s2-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type SRCH) for 33 DoubleLock-PT-p2s2-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 54 (type EQUN) for DoubleLock-PT-p2s2-CTLFireability-08
lola: result : unknown
lola: FINISHED task # 43 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-13
lola: result : false
lola: markings : 37
lola: fired transitions : 38
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 DoubleLock-PT-p2s2-CTLFireability-12
lola: time limit : 445 sec
lola: memory limit: 32 pages
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 0/445 1/32 DoubleLock-PT-p2s2-CTLFireability-12 2643 m, 528 m/sec, 3145 t fired, .
57 EF FNDP 0/3565 0/5 DoubleLock-PT-p2s2-CTLFireability-09 16 t fired, 1 attempts, .
59 EF STEQ 0/3565 0/5 DoubleLock-PT-p2s2-CTLFireability-09 sara not yet started (preprocessing).
64 EF SRCH 0/3565 1/5 DoubleLock-PT-p2s2-CTLFireability-09 151 m, 30 m/sec, 151 t fired, .

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sara: try reading problem file /home/mcc/execution/373/CTLFireability-59.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 57 (type FNDP) for DoubleLock-PT-p2s2-CTLFireability-09
lola: result : true
lola: fired transitions : 26482
lola: tried executions : 438
lola: time used : 3.000000
lola: memory pages used : 0
lola: CANCELED task # 59 (type EQUN) for DoubleLock-PT-p2s2-CTLFireability-09 (obsolete)
lola: CANCELED task # 64 (type SRCH) for DoubleLock-PT-p2s2-CTLFireability-09 (obsolete)
lola: FINISHED task # 59 (type EQUN) for DoubleLock-PT-p2s2-CTLFireability-09
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/509 5/32 DoubleLock-PT-p2s2-CTLFireability-12 675835 m, 134638 m/sec, 821890 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/509 9/32 DoubleLock-PT-p2s2-CTLFireability-12 1369003 m, 138633 m/sec, 1664932 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/509 13/32 DoubleLock-PT-p2s2-CTLFireability-12 2058585 m, 137916 m/sec, 2503614 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/509 17/32 DoubleLock-PT-p2s2-CTLFireability-12 2747856 m, 137854 m/sec, 3341917 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/509 21/32 DoubleLock-PT-p2s2-CTLFireability-12 3431555 m, 136739 m/sec, 4173442 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 30/509 26/32 DoubleLock-PT-p2s2-CTLFireability-12 4115756 m, 136840 m/sec, 5005578 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 35/509 30/32 DoubleLock-PT-p2s2-CTLFireability-12 4796732 m, 136195 m/sec, 5833794 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 37 (type EXCL) for 36 DoubleLock-PT-p2s2-CTLFireability-11
lola: time limit : 587 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-11
lola: result : false
lola: markings : 33
lola: fired transitions : 34
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 DoubleLock-PT-p2s2-CTLFireability-05
lola: time limit : 705 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/705 6/32 DoubleLock-PT-p2s2-CTLFireability-05 827382 m, 165476 m/sec, 1006200 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/705 11/32 DoubleLock-PT-p2s2-CTLFireability-05 1667929 m, 168109 m/sec, 2028486 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/705 16/32 DoubleLock-PT-p2s2-CTLFireability-05 2493169 m, 165048 m/sec, 3032156 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/705 21/32 DoubleLock-PT-p2s2-CTLFireability-05 3315613 m, 164488 m/sec, 4032427 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/705 26/32 DoubleLock-PT-p2s2-CTLFireability-05 4136063 m, 164090 m/sec, 5030271 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/705 31/32 DoubleLock-PT-p2s2-CTLFireability-05 4952392 m, 163265 m/sec, 6023104 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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lola: FINISHED task # 10 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-04
lola: result : true
lola: markings : 37
lola: fired transitions : 75
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/1163 5/32 DoubleLock-PT-p2s2-CTLFireability-03 949378 m, 189875 m/sec, 1334925 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/1163 8/32 DoubleLock-PT-p2s2-CTLFireability-03 1890110 m, 188146 m/sec, 2640035 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/1163 12/32 DoubleLock-PT-p2s2-CTLFireability-03 2820602 m, 186098 m/sec, 3933832 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/1163 16/32 DoubleLock-PT-p2s2-CTLFireability-03 3749859 m, 185851 m/sec, 5213296 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/1163 20/32 DoubleLock-PT-p2s2-CTLFireability-03 4664499 m, 182928 m/sec, 6480156 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/1163 24/32 DoubleLock-PT-p2s2-CTLFireability-03 5566569 m, 180414 m/sec, 7736905 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/1163 28/32 DoubleLock-PT-p2s2-CTLFireability-03 6474514 m, 181589 m/sec, 8986642 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/1163 32/32 DoubleLock-PT-p2s2-CTLFireability-03 7377607 m, 180618 m/sec, 10240874 t fired, .

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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker

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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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lola: LAUNCH task # 1 (type EXCL) for 0 DoubleLock-PT-p2s2-CTLFireability-00
lola: time limit : 1722 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-00
lola: result : false
lola: markings : 33
lola: fired transitions : 132
lola: time used : 0.000000
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lola: LAUNCH task # 16 (type EXCL) for 15 DoubleLock-PT-p2s2-CTLFireability-06
lola: time limit : 3445 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-06
lola: result : true
lola: markings : 33
lola: fired transitions : 33
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 13

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-03: CTL unknown AGGR
DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-05: CTL unknown AGGR
DoubleLock-PT-p2s2-CTLFireability-06: EG true state space / EG
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-11: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-12: CTL unknown AGGR
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-14: CTL unknown AGGR
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p2s2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DoubleLock-PT-p2s2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819414700538"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p2s2.tgz
mv DoubleLock-PT-p2s2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;