About the Execution of LoLa+red for DoubleLock-PT-p1s2
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6602.588 | 991525.00 | 1021642.00 | 3278.70 | F?FFFT???F?FFT?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r135-smll-167819414600514.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DoubleLock-PT-p1s2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819414600514
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.8M
-rw-r--r-- 1 mcc users 7.1K Feb 25 14:26 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 14:26 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 14:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 25 14:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 14:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 184K Feb 25 14:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 14:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 14:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 3.4M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678379336103
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p1s2
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 16:28:59] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 16:28:59] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 16:29:00] [INFO ] Load time of PNML (sax parser for PT used): 747 ms
[2023-03-09 16:29:00] [INFO ] Transformed 570 places.
[2023-03-09 16:29:00] [INFO ] Transformed 7600 transitions.
[2023-03-09 16:29:00] [INFO ] Parsed PT model containing 570 places and 7600 transitions and 30784 arcs in 975 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 15 ms.
Deduced a syphon composed of 132 places in 28 ms
Reduce places removed 132 places and 256 transitions.
Support contains 106 out of 438 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 438/438 places, 7344/7344 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 434 transition count 7344
Applied a total of 4 rules in 151 ms. Remains 434 /438 variables (removed 4) and now considering 7344/7344 (removed 0) transitions.
[2023-03-09 16:29:00] [INFO ] Flow matrix only has 5003 transitions (discarded 2341 similar events)
// Phase 1: matrix 5003 rows 434 cols
[2023-03-09 16:29:00] [INFO ] Computed 2 place invariants in 99 ms
[2023-03-09 16:29:01] [INFO ] Implicit Places using invariants in 1104 ms returned []
[2023-03-09 16:29:01] [INFO ] Flow matrix only has 5003 transitions (discarded 2341 similar events)
[2023-03-09 16:29:01] [INFO ] Invariant cache hit.
[2023-03-09 16:29:03] [INFO ] Implicit Places using invariants and state equation in 1603 ms returned []
Implicit Place search using SMT with State Equation took 2754 ms to find 0 implicit places.
[2023-03-09 16:29:03] [INFO ] Flow matrix only has 5003 transitions (discarded 2341 similar events)
[2023-03-09 16:29:03] [INFO ] Invariant cache hit.
[2023-03-09 16:29:07] [INFO ] Dead Transitions using invariants and state equation in 3785 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 434/438 places, 7344/7344 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6700 ms. Remains : 434/438 places, 7344/7344 transitions.
Support contains 106 out of 434 places after structural reductions.
[2023-03-09 16:29:08] [INFO ] Flatten gal took : 728 ms
[2023-03-09 16:29:08] [INFO ] Flatten gal took : 347 ms
[2023-03-09 16:29:09] [INFO ] Input system was already deterministic with 7344 transitions.
Support contains 105 out of 434 places (down from 106) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 87 resets, run finished after 702 ms. (steps per millisecond=14 ) properties (out of 56) seen :17
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 39) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 39) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 38) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 38) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 37) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 36) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 35) seen :0
Running SMT prover for 35 properties.
[2023-03-09 16:29:10] [INFO ] Flow matrix only has 5003 transitions (discarded 2341 similar events)
[2023-03-09 16:29:10] [INFO ] Invariant cache hit.
[2023-03-09 16:29:11] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 16:29:11] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-09 16:29:29] [INFO ] After 17274ms SMT Verify possible using state equation in real domain returned unsat :3 sat :1 real:31
[2023-03-09 16:29:29] [INFO ] State equation strengthened by 400 read => feed constraints.
[2023-03-09 16:29:36] [INFO ] After 6901ms SMT Verify possible using 400 Read/Feed constraints in real domain returned unsat :3 sat :0 real:31
[2023-03-09 16:29:36] [INFO ] After 25015ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:31
[2023-03-09 16:29:36] [INFO ] [Nat]Absence check using 1 positive place invariants in 2 ms returned sat
[2023-03-09 16:29:36] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 3 ms returned sat
[2023-03-09 16:30:01] [INFO ] After 24193ms SMT Verify possible using state equation in natural domain returned unsat :8 sat :26
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-09 16:30:01] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-09 16:30:01] [INFO ] After 25031ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :0 real:31
Fused 35 Parikh solutions to 18 different solutions.
Parikh walk visited 0 properties in 1230 ms.
Support contains 53 out of 434 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Drop transitions removed 56 transitions
Reduce isomorphic transitions removed 56 transitions.
Iterating post reduction 0 with 56 rules applied. Total rules applied 56 place count 434 transition count 7288
Applied a total of 56 rules in 593 ms. Remains 434 /434 variables (removed 0) and now considering 7288/7344 (removed 56) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 595 ms. Remains : 434/434 places, 7288/7344 transitions.
Incomplete random walk after 10000 steps, including 90 resets, run finished after 330 ms. (steps per millisecond=30 ) properties (out of 27) seen :2
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 24) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 24) seen :0
Running SMT prover for 24 properties.
[2023-03-09 16:30:03] [INFO ] Flow matrix only has 4947 transitions (discarded 2341 similar events)
// Phase 1: matrix 4947 rows 434 cols
[2023-03-09 16:30:03] [INFO ] Computed 2 place invariants in 68 ms
[2023-03-09 16:30:04] [INFO ] [Real]Absence check using 1 positive place invariants in 2 ms returned sat
[2023-03-09 16:30:04] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-09 16:30:29] [INFO ] After 24360ms SMT Verify possible using state equation in real domain returned unsat :1 sat :1 real:21
[2023-03-09 16:30:29] [INFO ] State equation strengthened by 400 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-09 16:30:29] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-09 16:30:29] [INFO ] After 25067ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 24 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 42 out of 434 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 434/434 places, 7288/7288 transitions.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 434 transition count 7287
Applied a total of 1 rules in 414 ms. Remains 434 /434 variables (removed 0) and now considering 7287/7288 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 414 ms. Remains : 434/434 places, 7287/7288 transitions.
Incomplete random walk after 10000 steps, including 85 resets, run finished after 292 ms. (steps per millisecond=34 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 23) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 22) seen :0
Interrupted probabilistic random walk after 60827 steps, run timeout after 3001 ms. (steps per millisecond=20 ) properties seen :{}
Probabilistic random walk after 60827 steps, saw 47454 distinct states, run finished after 3003 ms. (steps per millisecond=20 ) properties seen :0
Running SMT prover for 22 properties.
[2023-03-09 16:30:33] [INFO ] Flow matrix only has 4946 transitions (discarded 2341 similar events)
// Phase 1: matrix 4946 rows 434 cols
[2023-03-09 16:30:33] [INFO ] Computed 2 place invariants in 35 ms
[2023-03-09 16:30:33] [INFO ] [Real]Absence check using 1 positive place invariants in 2 ms returned sat
[2023-03-09 16:30:33] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-09 16:30:58] [INFO ] After 24445ms SMT Verify possible using state equation in real domain returned unsat :0 sat :3 real:18
[2023-03-09 16:30:58] [INFO ] State equation strengthened by 400 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-09 16:30:58] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-09 16:30:58] [INFO ] After 25041ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 22 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 40 out of 434 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 434/434 places, 7287/7287 transitions.
Applied a total of 0 rules in 367 ms. Remains 434 /434 variables (removed 0) and now considering 7287/7287 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 367 ms. Remains : 434/434 places, 7287/7287 transitions.
Successfully simplified 9 atomic propositions for a total of 16 simplifications.
FORMULA DoubleLock-PT-p1s2-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DoubleLock-PT-p1s2-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 16:30:58] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 16:30:58] [INFO ] Flatten gal took : 246 ms
FORMULA DoubleLock-PT-p1s2-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 16:30:59] [INFO ] Flatten gal took : 289 ms
[2023-03-09 16:30:59] [INFO ] Input system was already deterministic with 7344 transitions.
Support contains 85 out of 434 places (down from 86) after GAL structural reductions.
Computed a total of 10 stabilizing places and 2176 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 209 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 212 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:00] [INFO ] Flatten gal took : 201 ms
[2023-03-09 16:31:00] [INFO ] Flatten gal took : 218 ms
[2023-03-09 16:31:00] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 452 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 454 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:01] [INFO ] Flatten gal took : 167 ms
[2023-03-09 16:31:01] [INFO ] Flatten gal took : 201 ms
[2023-03-09 16:31:02] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 59 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 60 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:02] [INFO ] Flatten gal took : 166 ms
[2023-03-09 16:31:02] [INFO ] Flatten gal took : 197 ms
[2023-03-09 16:31:02] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 49 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 50 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:03] [INFO ] Flatten gal took : 161 ms
[2023-03-09 16:31:03] [INFO ] Flatten gal took : 203 ms
[2023-03-09 16:31:03] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 55 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:04] [INFO ] Flatten gal took : 178 ms
[2023-03-09 16:31:04] [INFO ] Flatten gal took : 188 ms
[2023-03-09 16:31:04] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 51 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 52 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:04] [INFO ] Flatten gal took : 159 ms
[2023-03-09 16:31:04] [INFO ] Flatten gal took : 189 ms
[2023-03-09 16:31:05] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 256 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 257 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:05] [INFO ] Flatten gal took : 166 ms
[2023-03-09 16:31:05] [INFO ] Flatten gal took : 175 ms
[2023-03-09 16:31:06] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Applied a total of 0 rules in 257 ms. Remains 434 /434 variables (removed 0) and now considering 7344/7344 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 258 ms. Remains : 434/434 places, 7344/7344 transitions.
[2023-03-09 16:31:06] [INFO ] Flatten gal took : 166 ms
[2023-03-09 16:31:06] [INFO ] Flatten gal took : 190 ms
[2023-03-09 16:31:07] [INFO ] Input system was already deterministic with 7344 transitions.
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 44 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 46 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:07] [INFO ] Flatten gal took : 161 ms
[2023-03-09 16:31:07] [INFO ] Flatten gal took : 188 ms
[2023-03-09 16:31:08] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 46 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 46 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:08] [INFO ] Flatten gal took : 157 ms
[2023-03-09 16:31:08] [INFO ] Flatten gal took : 187 ms
[2023-03-09 16:31:08] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 43 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 43 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:09] [INFO ] Flatten gal took : 156 ms
[2023-03-09 16:31:09] [INFO ] Flatten gal took : 187 ms
[2023-03-09 16:31:09] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 45 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 47 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:09] [INFO ] Flatten gal took : 157 ms
[2023-03-09 16:31:10] [INFO ] Flatten gal took : 188 ms
[2023-03-09 16:31:10] [INFO ] Input system was already deterministic with 7216 transitions.
Starting structural reductions in LTL mode, iteration 0 : 434/434 places, 7344/7344 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 433 transition count 7216
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 433 transition count 7216
Applied a total of 2 rules in 44 ms. Remains 433 /434 variables (removed 1) and now considering 7216/7344 (removed 128) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 44 ms. Remains : 433/434 places, 7216/7344 transitions.
[2023-03-09 16:31:10] [INFO ] Flatten gal took : 157 ms
[2023-03-09 16:31:10] [INFO ] Flatten gal took : 187 ms
[2023-03-09 16:31:11] [INFO ] Input system was already deterministic with 7216 transitions.
[2023-03-09 16:31:11] [INFO ] Flatten gal took : 183 ms
[2023-03-09 16:31:11] [INFO ] Flatten gal took : 193 ms
[2023-03-09 16:31:11] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-09 16:31:11] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 434 places, 7344 transitions and 29248 arcs took 40 ms.
Total runtime 132197 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DoubleLock-PT-p1s2
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA DoubleLock-PT-p1s2-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s2-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s2-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s2-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s2-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s2-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678380327628
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 9 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 13
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 43 (type EXCL) for 6 DoubleLock-PT-p1s2-CTLFireability-02
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 43 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-02
lola: result : true
lola: markings : 53
lola: fired transitions : 52
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 0 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 1 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 14 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 13
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 26 (type EXCL) for 25 DoubleLock-PT-p1s2-CTLFireability-07
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 4/275 2/32 DoubleLock-PT-p1s2-CTLFireability-07 201462 m, 40292 m/sec, 201464 t fired, .
Time elapsed: 19 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 9/275 3/32 DoubleLock-PT-p1s2-CTLFireability-07 435305 m, 46768 m/sec, 435307 t fired, .
Time elapsed: 24 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 14/275 5/32 DoubleLock-PT-p1s2-CTLFireability-07 668942 m, 46727 m/sec, 668944 t fired, .
Time elapsed: 29 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 19/275 6/32 DoubleLock-PT-p1s2-CTLFireability-07 901709 m, 46553 m/sec, 901711 t fired, .
Time elapsed: 34 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 24/275 8/32 DoubleLock-PT-p1s2-CTLFireability-07 1134616 m, 46581 m/sec, 1134618 t fired, .
Time elapsed: 39 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 29/275 9/32 DoubleLock-PT-p1s2-CTLFireability-07 1367878 m, 46652 m/sec, 1367880 t fired, .
Time elapsed: 44 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 34/275 11/32 DoubleLock-PT-p1s2-CTLFireability-07 1600123 m, 46449 m/sec, 1600125 t fired, .
Time elapsed: 49 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 39/275 12/32 DoubleLock-PT-p1s2-CTLFireability-07 1832517 m, 46478 m/sec, 1832520 t fired, .
Time elapsed: 54 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 44/275 14/32 DoubleLock-PT-p1s2-CTLFireability-07 2065028 m, 46502 m/sec, 2065030 t fired, .
Time elapsed: 59 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 49/275 15/32 DoubleLock-PT-p1s2-CTLFireability-07 2297974 m, 46589 m/sec, 2297976 t fired, .
Time elapsed: 64 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 54/275 17/32 DoubleLock-PT-p1s2-CTLFireability-07 2530438 m, 46492 m/sec, 2530440 t fired, .
Time elapsed: 69 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 59/275 18/32 DoubleLock-PT-p1s2-CTLFireability-07 2762703 m, 46453 m/sec, 2762705 t fired, .
Time elapsed: 74 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 64/275 19/32 DoubleLock-PT-p1s2-CTLFireability-07 2994696 m, 46398 m/sec, 2994698 t fired, .
Time elapsed: 79 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 69/275 21/32 DoubleLock-PT-p1s2-CTLFireability-07 3226799 m, 46420 m/sec, 3226801 t fired, .
Time elapsed: 84 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 74/275 22/32 DoubleLock-PT-p1s2-CTLFireability-07 3458409 m, 46322 m/sec, 3458411 t fired, .
Time elapsed: 89 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 79/275 24/32 DoubleLock-PT-p1s2-CTLFireability-07 3690183 m, 46354 m/sec, 3690185 t fired, .
Time elapsed: 94 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 84/275 25/32 DoubleLock-PT-p1s2-CTLFireability-07 3922161 m, 46395 m/sec, 3922164 t fired, .
Time elapsed: 99 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 89/275 27/32 DoubleLock-PT-p1s2-CTLFireability-07 4154263 m, 46420 m/sec, 4154266 t fired, .
Time elapsed: 104 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 94/275 28/32 DoubleLock-PT-p1s2-CTLFireability-07 4386145 m, 46376 m/sec, 4386147 t fired, .
Time elapsed: 109 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 99/275 30/32 DoubleLock-PT-p1s2-CTLFireability-07 4617779 m, 46326 m/sec, 4617781 t fired, .
Time elapsed: 114 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 104/275 31/32 DoubleLock-PT-p1s2-CTLFireability-07 4850597 m, 46563 m/sec, 4850599 t fired, .
Time elapsed: 119 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 26 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 124 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 41 (type EXCL) for 40 DoubleLock-PT-p1s2-CTLFireability-15
lola: time limit : 289 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/289 2/32 DoubleLock-PT-p1s2-CTLFireability-15 238882 m, 47776 m/sec, 238881 t fired, .
Time elapsed: 129 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/289 4/32 DoubleLock-PT-p1s2-CTLFireability-15 494679 m, 51159 m/sec, 494678 t fired, .
Time elapsed: 134 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/289 5/32 DoubleLock-PT-p1s2-CTLFireability-15 749908 m, 51045 m/sec, 749907 t fired, .
Time elapsed: 139 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/289 7/32 DoubleLock-PT-p1s2-CTLFireability-15 1004678 m, 50954 m/sec, 1004677 t fired, .
Time elapsed: 144 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/289 8/32 DoubleLock-PT-p1s2-CTLFireability-15 1259573 m, 50979 m/sec, 1259572 t fired, .
Time elapsed: 149 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/289 10/32 DoubleLock-PT-p1s2-CTLFireability-15 1514327 m, 50950 m/sec, 1514326 t fired, .
Time elapsed: 154 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 35/289 12/32 DoubleLock-PT-p1s2-CTLFireability-15 1766707 m, 50476 m/sec, 1766707 t fired, .
Time elapsed: 159 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 40/289 13/32 DoubleLock-PT-p1s2-CTLFireability-15 2017065 m, 50071 m/sec, 2017064 t fired, .
Time elapsed: 164 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 45/289 15/32 DoubleLock-PT-p1s2-CTLFireability-15 2267240 m, 50035 m/sec, 2267239 t fired, .
Time elapsed: 169 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 50/289 16/32 DoubleLock-PT-p1s2-CTLFireability-15 2516995 m, 49951 m/sec, 2516994 t fired, .
Time elapsed: 174 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 55/289 18/32 DoubleLock-PT-p1s2-CTLFireability-15 2766645 m, 49930 m/sec, 2766644 t fired, .
Time elapsed: 179 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 60/289 20/32 DoubleLock-PT-p1s2-CTLFireability-15 3016246 m, 49920 m/sec, 3016245 t fired, .
Time elapsed: 184 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 65/289 21/32 DoubleLock-PT-p1s2-CTLFireability-15 3266145 m, 49979 m/sec, 3266144 t fired, .
Time elapsed: 189 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 70/289 23/32 DoubleLock-PT-p1s2-CTLFireability-15 3516157 m, 50002 m/sec, 3516156 t fired, .
Time elapsed: 194 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 75/289 24/32 DoubleLock-PT-p1s2-CTLFireability-15 3765862 m, 49941 m/sec, 3765861 t fired, .
Time elapsed: 199 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 80/289 26/32 DoubleLock-PT-p1s2-CTLFireability-15 4015922 m, 50012 m/sec, 4015921 t fired, .
Time elapsed: 204 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 85/289 28/32 DoubleLock-PT-p1s2-CTLFireability-15 4265566 m, 49928 m/sec, 4265565 t fired, .
Time elapsed: 209 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 90/289 29/32 DoubleLock-PT-p1s2-CTLFireability-15 4514851 m, 49857 m/sec, 4514850 t fired, .
Time elapsed: 214 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 95/289 31/32 DoubleLock-PT-p1s2-CTLFireability-15 4764080 m, 49845 m/sec, 4764079 t fired, .
Time elapsed: 219 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 100/289 32/32 DoubleLock-PT-p1s2-CTLFireability-15 5013388 m, 49861 m/sec, 5013387 t fired, .
Time elapsed: 224 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 41 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 229 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 38 (type EXCL) for 37 DoubleLock-PT-p1s2-CTLFireability-14
lola: time limit : 306 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/306 2/32 DoubleLock-PT-p1s2-CTLFireability-14 234305 m, 46861 m/sec, 234304 t fired, .
Time elapsed: 234 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 10/306 4/32 DoubleLock-PT-p1s2-CTLFireability-14 484526 m, 50044 m/sec, 484525 t fired, .
Time elapsed: 239 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 15/306 5/32 DoubleLock-PT-p1s2-CTLFireability-14 734742 m, 50043 m/sec, 734742 t fired, .
Time elapsed: 244 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 20/306 7/32 DoubleLock-PT-p1s2-CTLFireability-14 984616 m, 49974 m/sec, 984615 t fired, .
Time elapsed: 249 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 25/306 8/32 DoubleLock-PT-p1s2-CTLFireability-14 1234528 m, 49982 m/sec, 1234527 t fired, .
Time elapsed: 254 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 30/306 10/32 DoubleLock-PT-p1s2-CTLFireability-14 1484221 m, 49938 m/sec, 1484220 t fired, .
Time elapsed: 259 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 35/306 11/32 DoubleLock-PT-p1s2-CTLFireability-14 1732354 m, 49626 m/sec, 1732353 t fired, .
Time elapsed: 264 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 40/306 13/32 DoubleLock-PT-p1s2-CTLFireability-14 1977646 m, 49058 m/sec, 1977645 t fired, .
Time elapsed: 269 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 45/306 15/32 DoubleLock-PT-p1s2-CTLFireability-14 2222970 m, 49064 m/sec, 2222969 t fired, .
Time elapsed: 274 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 50/306 16/32 DoubleLock-PT-p1s2-CTLFireability-14 2467961 m, 48998 m/sec, 2467961 t fired, .
Time elapsed: 279 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 55/306 18/32 DoubleLock-PT-p1s2-CTLFireability-14 2712567 m, 48921 m/sec, 2712567 t fired, .
Time elapsed: 284 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 60/306 19/32 DoubleLock-PT-p1s2-CTLFireability-14 2957173 m, 48921 m/sec, 2957172 t fired, .
Time elapsed: 289 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 65/306 21/32 DoubleLock-PT-p1s2-CTLFireability-14 3201838 m, 48933 m/sec, 3201837 t fired, .
Time elapsed: 294 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 70/306 22/32 DoubleLock-PT-p1s2-CTLFireability-14 3446010 m, 48834 m/sec, 3446009 t fired, .
Time elapsed: 299 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 75/306 24/32 DoubleLock-PT-p1s2-CTLFireability-14 3690389 m, 48875 m/sec, 3690388 t fired, .
Time elapsed: 304 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 80/306 25/32 DoubleLock-PT-p1s2-CTLFireability-14 3934677 m, 48857 m/sec, 3934676 t fired, .
Time elapsed: 309 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 85/306 27/32 DoubleLock-PT-p1s2-CTLFireability-14 4179794 m, 49023 m/sec, 4179793 t fired, .
Time elapsed: 314 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 90/306 29/32 DoubleLock-PT-p1s2-CTLFireability-14 4424059 m, 48853 m/sec, 4424059 t fired, .
Time elapsed: 319 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 95/306 30/32 DoubleLock-PT-p1s2-CTLFireability-14 4668289 m, 48846 m/sec, 4668288 t fired, .
Time elapsed: 324 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 100/306 32/32 DoubleLock-PT-p1s2-CTLFireability-14 4912535 m, 48849 m/sec, 4912534 t fired, .
Time elapsed: 329 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 38 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 334 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 35 (type EXCL) for 34 DoubleLock-PT-p1s2-CTLFireability-10
lola: time limit : 326 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 5/326 2/32 DoubleLock-PT-p1s2-CTLFireability-10 180240 m, 36048 m/sec, 348471 t fired, .
Time elapsed: 339 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 10/326 3/32 DoubleLock-PT-p1s2-CTLFireability-10 371771 m, 38306 m/sec, 718763 t fired, .
Time elapsed: 344 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 15/326 4/32 DoubleLock-PT-p1s2-CTLFireability-10 562808 m, 38207 m/sec, 1088101 t fired, .
Time elapsed: 349 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 20/326 5/32 DoubleLock-PT-p1s2-CTLFireability-10 753579 m, 38154 m/sec, 1456925 t fired, .
Time elapsed: 354 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 25/326 6/32 DoubleLock-PT-p1s2-CTLFireability-10 944164 m, 38117 m/sec, 1825389 t fired, .
Time elapsed: 359 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 30/326 8/32 DoubleLock-PT-p1s2-CTLFireability-10 1135193 m, 38205 m/sec, 2194712 t fired, .
Time elapsed: 364 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 35/326 9/32 DoubleLock-PT-p1s2-CTLFireability-10 1324122 m, 37785 m/sec, 2559975 t fired, .
Time elapsed: 369 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 40/326 10/32 DoubleLock-PT-p1s2-CTLFireability-10 1511334 m, 37442 m/sec, 2921919 t fired, .
Time elapsed: 374 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 45/326 11/32 DoubleLock-PT-p1s2-CTLFireability-10 1698529 m, 37439 m/sec, 3283828 t fired, .
Time elapsed: 379 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 50/326 12/32 DoubleLock-PT-p1s2-CTLFireability-10 1885612 m, 37416 m/sec, 3645522 t fired, .
Time elapsed: 384 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 55/326 14/32 DoubleLock-PT-p1s2-CTLFireability-10 2072694 m, 37416 m/sec, 4007214 t fired, .
Time elapsed: 389 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 60/326 15/32 DoubleLock-PT-p1s2-CTLFireability-10 2259544 m, 37370 m/sec, 4368459 t fired, .
Time elapsed: 394 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 65/326 16/32 DoubleLock-PT-p1s2-CTLFireability-10 2445936 m, 37278 m/sec, 4728815 t fired, .
Time elapsed: 399 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 70/326 17/32 DoubleLock-PT-p1s2-CTLFireability-10 2632605 m, 37333 m/sec, 5089709 t fired, .
Time elapsed: 404 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 75/326 18/32 DoubleLock-PT-p1s2-CTLFireability-10 2819048 m, 37288 m/sec, 5450165 t fired, .
Time elapsed: 409 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 80/326 20/32 DoubleLock-PT-p1s2-CTLFireability-10 3005634 m, 37317 m/sec, 5810899 t fired, .
Time elapsed: 414 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 85/326 21/32 DoubleLock-PT-p1s2-CTLFireability-10 3192189 m, 37311 m/sec, 6171572 t fired, .
Time elapsed: 419 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 90/326 22/32 DoubleLock-PT-p1s2-CTLFireability-10 3378440 m, 37250 m/sec, 6531657 t fired, .
Time elapsed: 424 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 95/326 23/32 DoubleLock-PT-p1s2-CTLFireability-10 3564606 m, 37233 m/sec, 6891577 t fired, .
Time elapsed: 429 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 100/326 24/32 DoubleLock-PT-p1s2-CTLFireability-10 3750838 m, 37246 m/sec, 7251626 t fired, .
Time elapsed: 434 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 105/326 25/32 DoubleLock-PT-p1s2-CTLFireability-10 3936776 m, 37187 m/sec, 7611107 t fired, .
Time elapsed: 439 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 110/326 27/32 DoubleLock-PT-p1s2-CTLFireability-10 4122751 m, 37195 m/sec, 7970657 t fired, .
Time elapsed: 444 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 115/326 28/32 DoubleLock-PT-p1s2-CTLFireability-10 4308120 m, 37073 m/sec, 8329038 t fired, .
Time elapsed: 449 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 120/326 29/32 DoubleLock-PT-p1s2-CTLFireability-10 4493556 m, 37087 m/sec, 8687547 t fired, .
Time elapsed: 454 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 125/326 30/32 DoubleLock-PT-p1s2-CTLFireability-10 4678859 m, 37060 m/sec, 9045800 t fired, .
Time elapsed: 459 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 130/326 31/32 DoubleLock-PT-p1s2-CTLFireability-10 4864201 m, 37068 m/sec, 9404128 t fired, .
Time elapsed: 464 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 135/326 32/32 DoubleLock-PT-p1s2-CTLFireability-10 5049586 m, 37077 m/sec, 9762538 t fired, .
Time elapsed: 469 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 35 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 474 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 32 (type EXCL) for 31 DoubleLock-PT-p1s2-CTLFireability-09
lola: time limit : 347 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-09
lola: result : false
lola: markings : 131
lola: fired transitions : 261
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 DoubleLock-PT-p1s2-CTLFireability-08
lola: time limit : 390 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/390 2/32 DoubleLock-PT-p1s2-CTLFireability-08 210365 m, 42073 m/sec, 210365 t fired, .
Time elapsed: 479 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/390 3/32 DoubleLock-PT-p1s2-CTLFireability-08 433214 m, 44569 m/sec, 433214 t fired, .
Time elapsed: 484 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/390 5/32 DoubleLock-PT-p1s2-CTLFireability-08 656404 m, 44638 m/sec, 656404 t fired, .
Time elapsed: 489 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 20/390 6/32 DoubleLock-PT-p1s2-CTLFireability-08 879456 m, 44610 m/sec, 879456 t fired, .
Time elapsed: 494 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 25/390 7/32 DoubleLock-PT-p1s2-CTLFireability-08 1102795 m, 44667 m/sec, 1102795 t fired, .
Time elapsed: 499 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 30/390 9/32 DoubleLock-PT-p1s2-CTLFireability-08 1323845 m, 44210 m/sec, 1323845 t fired, .
Time elapsed: 504 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 35/390 10/32 DoubleLock-PT-p1s2-CTLFireability-08 1542656 m, 43762 m/sec, 1542657 t fired, .
Time elapsed: 509 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 40/390 12/32 DoubleLock-PT-p1s2-CTLFireability-08 1761417 m, 43752 m/sec, 1761418 t fired, .
Time elapsed: 514 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 45/390 13/32 DoubleLock-PT-p1s2-CTLFireability-08 1979963 m, 43709 m/sec, 1979963 t fired, .
Time elapsed: 519 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 50/390 14/32 DoubleLock-PT-p1s2-CTLFireability-08 2198696 m, 43746 m/sec, 2198696 t fired, .
Time elapsed: 524 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 55/390 16/32 DoubleLock-PT-p1s2-CTLFireability-08 2417055 m, 43671 m/sec, 2417056 t fired, .
Time elapsed: 529 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 60/390 17/32 DoubleLock-PT-p1s2-CTLFireability-08 2635255 m, 43640 m/sec, 2635255 t fired, .
Time elapsed: 534 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 65/390 19/32 DoubleLock-PT-p1s2-CTLFireability-08 2853310 m, 43611 m/sec, 2853311 t fired, .
Time elapsed: 539 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 70/390 20/32 DoubleLock-PT-p1s2-CTLFireability-08 3071554 m, 43648 m/sec, 3071554 t fired, .
Time elapsed: 544 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 75/390 21/32 DoubleLock-PT-p1s2-CTLFireability-08 3289746 m, 43638 m/sec, 3289746 t fired, .
Time elapsed: 549 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 80/390 23/32 DoubleLock-PT-p1s2-CTLFireability-08 3507683 m, 43587 m/sec, 3507683 t fired, .
Time elapsed: 554 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 85/390 24/32 DoubleLock-PT-p1s2-CTLFireability-08 3725742 m, 43611 m/sec, 3725742 t fired, .
Time elapsed: 559 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 90/390 25/32 DoubleLock-PT-p1s2-CTLFireability-08 3943698 m, 43591 m/sec, 3943698 t fired, .
Time elapsed: 564 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 96/390 27/32 DoubleLock-PT-p1s2-CTLFireability-08 4161936 m, 43647 m/sec, 4161936 t fired, .
Time elapsed: 570 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 101/390 28/32 DoubleLock-PT-p1s2-CTLFireability-08 4379922 m, 43597 m/sec, 4379922 t fired, .
Time elapsed: 575 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 106/390 30/32 DoubleLock-PT-p1s2-CTLFireability-08 4597920 m, 43599 m/sec, 4597920 t fired, .
Time elapsed: 580 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 111/390 31/32 DoubleLock-PT-p1s2-CTLFireability-08 4815868 m, 43589 m/sec, 4815868 t fired, .
Time elapsed: 585 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 116/390 32/32 DoubleLock-PT-p1s2-CTLFireability-08 5033799 m, 43586 m/sec, 5033799 t fired, .
Time elapsed: 590 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 29 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 595 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 20 (type EXCL) for 19 DoubleLock-PT-p1s2-CTLFireability-05
lola: time limit : 429 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-05
lola: result : true
lola: markings : 137
lola: fired transitions : 274
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 DoubleLock-PT-p1s2-CTLFireability-04
lola: time limit : 500 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-04
lola: result : false
lola: markings : 131
lola: fired transitions : 260
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 DoubleLock-PT-p1s2-CTLFireability-03
lola: time limit : 601 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-03
lola: result : false
lola: markings : 131
lola: fired transitions : 783
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DoubleLock-PT-p1s2-CTLFireability-00
lola: time limit : 751 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-00
lola: result : false
lola: markings : 131
lola: fired transitions : 130
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 DoubleLock-PT-p1s2-CTLFireability-06
lola: time limit : 1001 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/1001 2/32 DoubleLock-PT-p1s2-CTLFireability-06 182995 m, 36599 m/sec, 365989 t fired, .
Time elapsed: 600 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/1001 3/32 DoubleLock-PT-p1s2-CTLFireability-06 377397 m, 38880 m/sec, 754793 t fired, .
Time elapsed: 605 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/1001 4/32 DoubleLock-PT-p1s2-CTLFireability-06 571636 m, 38847 m/sec, 1143272 t fired, .
Time elapsed: 610 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 20/1001 5/32 DoubleLock-PT-p1s2-CTLFireability-06 765211 m, 38715 m/sec, 1530421 t fired, .
Time elapsed: 615 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 25/1001 7/32 DoubleLock-PT-p1s2-CTLFireability-06 959474 m, 38852 m/sec, 1918947 t fired, .
Time elapsed: 620 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 30/1001 8/32 DoubleLock-PT-p1s2-CTLFireability-06 1153284 m, 38762 m/sec, 2306567 t fired, .
Time elapsed: 625 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 35/1001 9/32 DoubleLock-PT-p1s2-CTLFireability-06 1346699 m, 38683 m/sec, 2693397 t fired, .
Time elapsed: 630 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 40/1001 10/32 DoubleLock-PT-p1s2-CTLFireability-06 1540217 m, 38703 m/sec, 3080433 t fired, .
Time elapsed: 635 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 45/1001 11/32 DoubleLock-PT-p1s2-CTLFireability-06 1732319 m, 38420 m/sec, 3464637 t fired, .
Time elapsed: 640 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 50/1001 13/32 DoubleLock-PT-p1s2-CTLFireability-06 1923736 m, 38283 m/sec, 3847471 t fired, .
Time elapsed: 645 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 55/1001 14/32 DoubleLock-PT-p1s2-CTLFireability-06 2115095 m, 38271 m/sec, 4230189 t fired, .
Time elapsed: 650 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 60/1001 15/32 DoubleLock-PT-p1s2-CTLFireability-06 2305646 m, 38110 m/sec, 4611292 t fired, .
Time elapsed: 655 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 65/1001 16/32 DoubleLock-PT-p1s2-CTLFireability-06 2495843 m, 38039 m/sec, 4991686 t fired, .
Time elapsed: 660 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 70/1001 18/32 DoubleLock-PT-p1s2-CTLFireability-06 2686708 m, 38173 m/sec, 5373416 t fired, .
Time elapsed: 665 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 75/1001 19/32 DoubleLock-PT-p1s2-CTLFireability-06 2877189 m, 38096 m/sec, 5754377 t fired, .
Time elapsed: 670 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 80/1001 20/32 DoubleLock-PT-p1s2-CTLFireability-06 3067985 m, 38159 m/sec, 6135969 t fired, .
Time elapsed: 675 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 85/1001 21/32 DoubleLock-PT-p1s2-CTLFireability-06 3258390 m, 38081 m/sec, 6516779 t fired, .
Time elapsed: 680 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 90/1001 22/32 DoubleLock-PT-p1s2-CTLFireability-06 3447799 m, 37881 m/sec, 6895597 t fired, .
Time elapsed: 685 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 95/1001 24/32 DoubleLock-PT-p1s2-CTLFireability-06 3637681 m, 37976 m/sec, 7275361 t fired, .
Time elapsed: 690 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 100/1001 25/32 DoubleLock-PT-p1s2-CTLFireability-06 3827694 m, 38002 m/sec, 7655387 t fired, .
Time elapsed: 695 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 105/1001 26/32 DoubleLock-PT-p1s2-CTLFireability-06 4017779 m, 38017 m/sec, 8035557 t fired, .
Time elapsed: 700 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 110/1001 27/32 DoubleLock-PT-p1s2-CTLFireability-06 4208144 m, 38073 m/sec, 8416287 t fired, .
Time elapsed: 705 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 115/1001 28/32 DoubleLock-PT-p1s2-CTLFireability-06 4398369 m, 38045 m/sec, 8796737 t fired, .
Time elapsed: 710 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 120/1001 30/32 DoubleLock-PT-p1s2-CTLFireability-06 4588732 m, 38072 m/sec, 9177463 t fired, .
Time elapsed: 715 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 125/1001 31/32 DoubleLock-PT-p1s2-CTLFireability-06 4778307 m, 37915 m/sec, 9556613 t fired, .
Time elapsed: 720 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 130/1001 32/32 DoubleLock-PT-p1s2-CTLFireability-06 4968297 m, 37998 m/sec, 9936593 t fired, .
Time elapsed: 725 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 23 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 730 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 9 (type EXCL) for 6 DoubleLock-PT-p1s2-CTLFireability-02
lola: time limit : 1435 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-02
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 DoubleLock-PT-p1s2-CTLFireability-01
lola: time limit : 2870 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/2870 2/32 DoubleLock-PT-p1s2-CTLFireability-01 205342 m, 41068 m/sec, 410684 t fired, .
Time elapsed: 735 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/2870 3/32 DoubleLock-PT-p1s2-CTLFireability-01 421362 m, 43204 m/sec, 842723 t fired, .
Time elapsed: 740 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/2870 5/32 DoubleLock-PT-p1s2-CTLFireability-01 637259 m, 43179 m/sec, 1274518 t fired, .
Time elapsed: 745 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/2870 6/32 DoubleLock-PT-p1s2-CTLFireability-01 852417 m, 43031 m/sec, 1704834 t fired, .
Time elapsed: 750 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/2870 7/32 DoubleLock-PT-p1s2-CTLFireability-01 1067350 m, 42986 m/sec, 2134701 t fired, .
Time elapsed: 755 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/2870 9/32 DoubleLock-PT-p1s2-CTLFireability-01 1263883 m, 39306 m/sec, 2527766 t fired, .
Time elapsed: 760 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/2870 10/32 DoubleLock-PT-p1s2-CTLFireability-01 1478023 m, 42828 m/sec, 2956047 t fired, .
Time elapsed: 765 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/2870 11/32 DoubleLock-PT-p1s2-CTLFireability-01 1691867 m, 42768 m/sec, 3383734 t fired, .
Time elapsed: 770 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/2870 12/32 DoubleLock-PT-p1s2-CTLFireability-01 1894336 m, 40493 m/sec, 3788673 t fired, .
Time elapsed: 775 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 50/2870 14/32 DoubleLock-PT-p1s2-CTLFireability-01 2105624 m, 42257 m/sec, 4211248 t fired, .
Time elapsed: 780 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 55/2870 15/32 DoubleLock-PT-p1s2-CTLFireability-01 2316611 m, 42197 m/sec, 4633223 t fired, .
Time elapsed: 785 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 60/2870 17/32 DoubleLock-PT-p1s2-CTLFireability-01 2526901 m, 42058 m/sec, 5053802 t fired, .
Time elapsed: 790 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 65/2870 18/32 DoubleLock-PT-p1s2-CTLFireability-01 2737374 m, 42094 m/sec, 5474748 t fired, .
Time elapsed: 795 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 70/2870 19/32 DoubleLock-PT-p1s2-CTLFireability-01 2947526 m, 42030 m/sec, 5895052 t fired, .
Time elapsed: 800 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 75/2870 21/32 DoubleLock-PT-p1s2-CTLFireability-01 3158461 m, 42187 m/sec, 6316922 t fired, .
Time elapsed: 805 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 80/2870 22/32 DoubleLock-PT-p1s2-CTLFireability-01 3368804 m, 42068 m/sec, 6737608 t fired, .
Time elapsed: 810 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 85/2870 23/32 DoubleLock-PT-p1s2-CTLFireability-01 3579107 m, 42060 m/sec, 7158215 t fired, .
Time elapsed: 815 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 90/2870 24/32 DoubleLock-PT-p1s2-CTLFireability-01 3789577 m, 42094 m/sec, 7579154 t fired, .
Time elapsed: 820 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 95/2870 26/32 DoubleLock-PT-p1s2-CTLFireability-01 3999819 m, 42048 m/sec, 7999638 t fired, .
Time elapsed: 825 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 100/2870 27/32 DoubleLock-PT-p1s2-CTLFireability-01 4210095 m, 42055 m/sec, 8420191 t fired, .
Time elapsed: 830 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 105/2870 28/32 DoubleLock-PT-p1s2-CTLFireability-01 4420169 m, 42014 m/sec, 8840338 t fired, .
Time elapsed: 835 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 110/2870 30/32 DoubleLock-PT-p1s2-CTLFireability-01 4629886 m, 41943 m/sec, 9259773 t fired, .
Time elapsed: 840 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 115/2870 31/32 DoubleLock-PT-p1s2-CTLFireability-01 4831943 m, 40411 m/sec, 9663885 t fired, .
Time elapsed: 845 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 120/2870 32/32 DoubleLock-PT-p1s2-CTLFireability-01 5042086 m, 42028 m/sec, 10084172 t fired, .
Time elapsed: 850 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 4 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 855 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: Portfolio finished: no open tasks 13
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-01: CTL unknown AGGR
DoubleLock-PT-p1s2-CTLFireability-02: DISJ false DISJ
DoubleLock-PT-p1s2-CTLFireability-03: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-04: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-05: CTL true CTL model checker
DoubleLock-PT-p1s2-CTLFireability-06: CTL unknown AGGR
DoubleLock-PT-p1s2-CTLFireability-07: CTL unknown AGGR
DoubleLock-PT-p1s2-CTLFireability-08: CTL unknown AGGR
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker
DoubleLock-PT-p1s2-CTLFireability-10: CTL unknown AGGR
DoubleLock-PT-p1s2-CTLFireability-14: CTL unknown AGGR
DoubleLock-PT-p1s2-CTLFireability-15: CTL unknown AGGR
Time elapsed: 855 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p1s2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DoubleLock-PT-p1s2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819414600514"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p1s2.tgz
mv DoubleLock-PT-p1s2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;