fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r135-smll-167819414500466
Last Updated
May 14, 2023

About the Execution of LoLa+red for DoubleExponent-PT-004

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
7344.296 3600000.00 3815532.00 14673.30 FF?TTF?FF?TT??TT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r135-smll-167819414500466.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DoubleExponent-PT-004, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819414500466
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 7.6K Feb 26 13:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 26 13:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4K Feb 26 13:28 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K Feb 26 13:28 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.6K Feb 26 13:30 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 88K Feb 26 13:30 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Feb 26 13:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 85K Feb 26 13:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 67K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-00
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-01
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-02
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-03
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-04
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-05
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-06
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-07
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-08
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-09
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-10
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-11
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-12
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-13
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-14
FORMULA_NAME DoubleExponent-PT-004-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678329901331

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleExponent-PT-004
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 02:45:04] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 02:45:04] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 02:45:05] [INFO ] Load time of PNML (sax parser for PT used): 110 ms
[2023-03-09 02:45:05] [INFO ] Transformed 216 places.
[2023-03-09 02:45:05] [INFO ] Transformed 198 transitions.
[2023-03-09 02:45:05] [INFO ] Parsed PT model containing 216 places and 198 transitions and 558 arcs in 262 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 19 ms.
Support contains 91 out of 216 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 216/216 places, 198/198 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 212 transition count 198
Applied a total of 4 rules in 46 ms. Remains 212 /216 variables (removed 4) and now considering 198/198 (removed 0) transitions.
// Phase 1: matrix 198 rows 212 cols
[2023-03-09 02:45:05] [INFO ] Computed 21 place invariants in 33 ms
[2023-03-09 02:45:05] [INFO ] Implicit Places using invariants in 537 ms returned [84]
Discarding 1 places :
Implicit Place search using SMT only with invariants took 595 ms to find 1 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 211/216 places, 198/198 transitions.
Applied a total of 0 rules in 20 ms. Remains 211 /211 variables (removed 0) and now considering 198/198 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 664 ms. Remains : 211/216 places, 198/198 transitions.
Support contains 91 out of 211 places after structural reductions.
[2023-03-09 02:45:06] [INFO ] Flatten gal took : 89 ms
[2023-03-09 02:45:06] [INFO ] Flatten gal took : 35 ms
[2023-03-09 02:45:06] [INFO ] Input system was already deterministic with 198 transitions.
Support contains 90 out of 211 places (down from 91) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 327 resets, run finished after 852 ms. (steps per millisecond=11 ) properties (out of 55) seen :14
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 31 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 25 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 25 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 24 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 28 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 26 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 29 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 24 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 30 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 31 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 24 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 30 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Running SMT prover for 41 properties.
// Phase 1: matrix 198 rows 211 cols
[2023-03-09 02:45:08] [INFO ] Computed 20 place invariants in 7 ms
[2023-03-09 02:45:08] [INFO ] [Real]Absence check using 2 positive place invariants in 4 ms returned sat
[2023-03-09 02:45:08] [INFO ] [Real]Absence check using 2 positive and 18 generalized place invariants in 12 ms returned sat
[2023-03-09 02:45:09] [INFO ] After 663ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:41
[2023-03-09 02:45:09] [INFO ] [Nat]Absence check using 2 positive place invariants in 3 ms returned sat
[2023-03-09 02:45:09] [INFO ] [Nat]Absence check using 2 positive and 18 generalized place invariants in 20 ms returned sat
[2023-03-09 02:45:11] [INFO ] After 1109ms SMT Verify possible using state equation in natural domain returned unsat :8 sat :33
[2023-03-09 02:45:11] [INFO ] Deduced a trap composed of 50 places in 144 ms of which 10 ms to minimize.
[2023-03-09 02:45:11] [INFO ] Deduced a trap composed of 48 places in 109 ms of which 1 ms to minimize.
[2023-03-09 02:45:11] [INFO ] Deduced a trap composed of 41 places in 111 ms of which 2 ms to minimize.
[2023-03-09 02:45:11] [INFO ] Deduced a trap composed of 55 places in 95 ms of which 3 ms to minimize.
[2023-03-09 02:45:11] [INFO ] Trap strengthening (SAT) tested/added 5/4 trap constraints in 560 ms
[2023-03-09 02:45:11] [INFO ] Deduced a trap composed of 43 places in 114 ms of which 2 ms to minimize.
[2023-03-09 02:45:12] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 152 ms
[2023-03-09 02:45:12] [INFO ] Deduced a trap composed of 47 places in 83 ms of which 1 ms to minimize.
[2023-03-09 02:45:12] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 120 ms
[2023-03-09 02:45:12] [INFO ] Deduced a trap composed of 52 places in 44 ms of which 1 ms to minimize.
[2023-03-09 02:45:12] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 68 ms
[2023-03-09 02:45:13] [INFO ] After 3185ms SMT Verify possible using trap constraints in natural domain returned unsat :8 sat :33
Attempting to minimize the solution found.
Minimization took 897 ms.
[2023-03-09 02:45:13] [INFO ] After 4743ms SMT Verify possible using all constraints in natural domain returned unsat :8 sat :33
Fused 41 Parikh solutions to 33 different solutions.
Parikh walk visited 0 properties in 1677 ms.
Support contains 48 out of 211 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 211/211 places, 198/198 transitions.
Drop transitions removed 17 transitions
Trivial Post-agglo rules discarded 17 transitions
Performed 17 trivial Post agglomeration. Transition count delta: 17
Iterating post reduction 0 with 17 rules applied. Total rules applied 17 place count 211 transition count 181
Reduce places removed 17 places and 0 transitions.
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Iterating post reduction 1 with 24 rules applied. Total rules applied 41 place count 194 transition count 174
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 2 with 7 rules applied. Total rules applied 48 place count 187 transition count 174
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 11 Pre rules applied. Total rules applied 48 place count 187 transition count 163
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 70 place count 176 transition count 163
Performed 17 Post agglomeration using F-continuation condition.Transition count delta: 17
Deduced a syphon composed of 17 places in 2 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 3 with 34 rules applied. Total rules applied 104 place count 159 transition count 146
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 0
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 110 place count 156 transition count 146
Free-agglomeration rule applied 1 times.
Iterating global reduction 3 with 1 rules applied. Total rules applied 111 place count 156 transition count 145
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 112 place count 155 transition count 145
Free-agglomeration rule (complex) applied 13 times.
Iterating global reduction 4 with 13 rules applied. Total rules applied 125 place count 155 transition count 132
Reduce places removed 13 places and 0 transitions.
Iterating post reduction 4 with 13 rules applied. Total rules applied 138 place count 142 transition count 132
Partial Free-agglomeration rule applied 9 times.
Drop transitions removed 9 transitions
Iterating global reduction 5 with 9 rules applied. Total rules applied 147 place count 142 transition count 132
Applied a total of 147 rules in 80 ms. Remains 142 /211 variables (removed 69) and now considering 132/198 (removed 66) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 81 ms. Remains : 142/211 places, 132/198 transitions.
Incomplete random walk after 10000 steps, including 715 resets, run finished after 346 ms. (steps per millisecond=28 ) properties (out of 33) seen :3
Incomplete Best-First random walk after 1000 steps, including 48 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 52 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 56 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 53 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 62 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 56 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 55 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 57 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 60 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 57 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 61 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 67 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 58 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 57 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 58 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 63 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 54 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 58 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 52 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 57 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 59 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 66 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 59 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 55 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 54 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 64 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 55 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 57 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 58 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1000 steps, including 50 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 30) seen :0
Interrupted probabilistic random walk after 160899 steps, run timeout after 3001 ms. (steps per millisecond=53 ) properties seen :{1=1, 2=1, 9=1, 10=1, 11=1, 13=1, 14=1, 15=1, 18=1, 20=1, 22=1, 25=1, 27=1}
Probabilistic random walk after 160899 steps, saw 80479 distinct states, run finished after 3002 ms. (steps per millisecond=53 ) properties seen :13
Running SMT prover for 17 properties.
// Phase 1: matrix 132 rows 142 cols
[2023-03-09 02:45:19] [INFO ] Computed 20 place invariants in 10 ms
[2023-03-09 02:45:19] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-09 02:45:19] [INFO ] [Real]Absence check using 2 positive and 18 generalized place invariants in 6 ms returned sat
[2023-03-09 02:45:19] [INFO ] After 176ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:17
[2023-03-09 02:45:20] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-09 02:45:20] [INFO ] [Nat]Absence check using 2 positive and 18 generalized place invariants in 15 ms returned sat
[2023-03-09 02:45:20] [INFO ] After 402ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :17
[2023-03-09 02:45:20] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-03-09 02:45:20] [INFO ] After 329ms SMT Verify possible using 6 Read/Feed constraints in natural domain returned unsat :0 sat :17
[2023-03-09 02:45:21] [INFO ] Deduced a trap composed of 7 places in 90 ms of which 1 ms to minimize.
[2023-03-09 02:45:21] [INFO ] Deduced a trap composed of 22 places in 62 ms of which 1 ms to minimize.
[2023-03-09 02:45:21] [INFO ] Deduced a trap composed of 26 places in 54 ms of which 1 ms to minimize.
[2023-03-09 02:45:21] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 267 ms
[2023-03-09 02:45:21] [INFO ] Deduced a trap composed of 25 places in 65 ms of which 3 ms to minimize.
[2023-03-09 02:45:21] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 87 ms
[2023-03-09 02:45:21] [INFO ] Deduced a trap composed of 23 places in 55 ms of which 1 ms to minimize.
[2023-03-09 02:45:21] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 79 ms
[2023-03-09 02:45:21] [INFO ] After 1143ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :17
Attempting to minimize the solution found.
Minimization took 293 ms.
[2023-03-09 02:45:22] [INFO ] After 2067ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :17
Fused 17 Parikh solutions to 16 different solutions.
Parikh walk visited 0 properties in 519 ms.
Support contains 28 out of 142 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 142/142 places, 132/132 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 142 transition count 128
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 8 place count 138 transition count 128
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 8 place count 138 transition count 126
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 12 place count 136 transition count 126
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 1 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 32 place count 126 transition count 116
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 0
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 36 place count 124 transition count 116
Free-agglomeration rule applied 1 times.
Iterating global reduction 2 with 1 rules applied. Total rules applied 37 place count 124 transition count 115
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 38 place count 123 transition count 115
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 3 with 1 rules applied. Total rules applied 39 place count 123 transition count 114
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 40 place count 122 transition count 114
Partial Free-agglomeration rule applied 5 times.
Drop transitions removed 5 transitions
Iterating global reduction 4 with 5 rules applied. Total rules applied 45 place count 122 transition count 114
Applied a total of 45 rules in 41 ms. Remains 122 /142 variables (removed 20) and now considering 114/132 (removed 18) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 41 ms. Remains : 122/142 places, 114/132 transitions.
Incomplete random walk after 10000 steps, including 944 resets, run finished after 254 ms. (steps per millisecond=39 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 72 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 69 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 66 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 67 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 74 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 70 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 70 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 71 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 71 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 70 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 68 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 77 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 73 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 76 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 74 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 67 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1000 steps, including 69 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 17) seen :0
Interrupted probabilistic random walk after 188208 steps, run timeout after 3001 ms. (steps per millisecond=62 ) properties seen :{1=1, 3=1}
Probabilistic random walk after 188208 steps, saw 94626 distinct states, run finished after 3001 ms. (steps per millisecond=62 ) properties seen :2
Running SMT prover for 15 properties.
// Phase 1: matrix 114 rows 122 cols
[2023-03-09 02:45:26] [INFO ] Computed 20 place invariants in 4 ms
[2023-03-09 02:45:26] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-09 02:45:26] [INFO ] [Real]Absence check using 2 positive and 18 generalized place invariants in 8 ms returned sat
[2023-03-09 02:45:26] [INFO ] After 156ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:15
[2023-03-09 02:45:26] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-09 02:45:26] [INFO ] [Nat]Absence check using 2 positive and 18 generalized place invariants in 7 ms returned sat
[2023-03-09 02:45:26] [INFO ] After 249ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :15
[2023-03-09 02:45:26] [INFO ] State equation strengthened by 11 read => feed constraints.
[2023-03-09 02:45:26] [INFO ] After 236ms SMT Verify possible using 11 Read/Feed constraints in natural domain returned unsat :0 sat :15
[2023-03-09 02:45:27] [INFO ] Deduced a trap composed of 5 places in 76 ms of which 1 ms to minimize.
[2023-03-09 02:45:27] [INFO ] Deduced a trap composed of 17 places in 52 ms of which 0 ms to minimize.
[2023-03-09 02:45:27] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 166 ms
[2023-03-09 02:45:27] [INFO ] Deduced a trap composed of 18 places in 70 ms of which 1 ms to minimize.
[2023-03-09 02:45:27] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 91 ms
[2023-03-09 02:45:27] [INFO ] Deduced a trap composed of 22 places in 46 ms of which 1 ms to minimize.
[2023-03-09 02:45:27] [INFO ] Deduced a trap composed of 20 places in 58 ms of which 0 ms to minimize.
[2023-03-09 02:45:27] [INFO ] Deduced a trap composed of 21 places in 37 ms of which 0 ms to minimize.
[2023-03-09 02:45:27] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 186 ms
[2023-03-09 02:45:27] [INFO ] After 988ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :15
Attempting to minimize the solution found.
Minimization took 207 ms.
[2023-03-09 02:45:27] [INFO ] After 1591ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :15
Parikh walk visited 0 properties in 285 ms.
Support contains 25 out of 122 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 122/122 places, 114/114 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 4 place count 120 transition count 112
Free-agglomeration rule (complex) applied 2 times.
Iterating global reduction 0 with 2 rules applied. Total rules applied 6 place count 120 transition count 110
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 8 place count 118 transition count 110
Applied a total of 8 rules in 15 ms. Remains 118 /122 variables (removed 4) and now considering 110/114 (removed 4) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 16 ms. Remains : 118/122 places, 110/114 transitions.
Incomplete random walk after 10000 steps, including 971 resets, run finished after 200 ms. (steps per millisecond=50 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 70 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 66 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 69 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 72 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 69 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 66 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 75 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 69 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 63 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 67 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 71 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 70 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 76 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 72 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 66 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Interrupted probabilistic random walk after 188139 steps, run timeout after 3006 ms. (steps per millisecond=62 ) properties seen :{}
Probabilistic random walk after 188139 steps, saw 94583 distinct states, run finished after 3007 ms. (steps per millisecond=62 ) properties seen :0
Running SMT prover for 15 properties.
// Phase 1: matrix 110 rows 118 cols
[2023-03-09 02:45:31] [INFO ] Computed 20 place invariants in 3 ms
[2023-03-09 02:45:31] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-09 02:45:31] [INFO ] [Real]Absence check using 2 positive and 18 generalized place invariants in 7 ms returned sat
[2023-03-09 02:45:31] [INFO ] After 139ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:15
[2023-03-09 02:45:31] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-09 02:45:31] [INFO ] [Nat]Absence check using 2 positive and 18 generalized place invariants in 8 ms returned sat
[2023-03-09 02:45:32] [INFO ] After 219ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :15
[2023-03-09 02:45:32] [INFO ] State equation strengthened by 12 read => feed constraints.
[2023-03-09 02:45:32] [INFO ] After 227ms SMT Verify possible using 12 Read/Feed constraints in natural domain returned unsat :0 sat :15
[2023-03-09 02:45:32] [INFO ] Deduced a trap composed of 5 places in 67 ms of which 2 ms to minimize.
[2023-03-09 02:45:32] [INFO ] Deduced a trap composed of 17 places in 61 ms of which 1 ms to minimize.
[2023-03-09 02:45:32] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 160 ms
[2023-03-09 02:45:32] [INFO ] Deduced a trap composed of 21 places in 35 ms of which 1 ms to minimize.
[2023-03-09 02:45:32] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 54 ms
[2023-03-09 02:45:32] [INFO ] Deduced a trap composed of 16 places in 53 ms of which 1 ms to minimize.
[2023-03-09 02:45:32] [INFO ] Deduced a trap composed of 17 places in 51 ms of which 0 ms to minimize.
[2023-03-09 02:45:32] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 135 ms
[2023-03-09 02:45:33] [INFO ] Deduced a trap composed of 20 places in 36 ms of which 0 ms to minimize.
[2023-03-09 02:45:33] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 55 ms
[2023-03-09 02:45:33] [INFO ] After 893ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :15
Attempting to minimize the solution found.
Minimization took 210 ms.
[2023-03-09 02:45:33] [INFO ] After 1464ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :15
Parikh walk visited 0 properties in 316 ms.
Support contains 25 out of 118 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 118/118 places, 110/110 transitions.
Applied a total of 0 rules in 9 ms. Remains 118 /118 variables (removed 0) and now considering 110/110 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 9 ms. Remains : 118/118 places, 110/110 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 118/118 places, 110/110 transitions.
Applied a total of 0 rules in 8 ms. Remains 118 /118 variables (removed 0) and now considering 110/110 (removed 0) transitions.
[2023-03-09 02:45:33] [INFO ] Invariant cache hit.
[2023-03-09 02:45:33] [INFO ] Implicit Places using invariants in 138 ms returned []
[2023-03-09 02:45:33] [INFO ] Invariant cache hit.
[2023-03-09 02:45:33] [INFO ] State equation strengthened by 12 read => feed constraints.
[2023-03-09 02:45:34] [INFO ] Implicit Places using invariants and state equation in 616 ms returned [26, 82, 89, 109, 115]
Discarding 5 places :
Implicit Place search using SMT with State Equation took 758 ms to find 5 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 1 : 113/118 places, 110/110 transitions.
Free-agglomeration rule (complex) applied 2 times.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 113 transition count 108
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 111 transition count 108
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 1 with 1 rules applied. Total rules applied 5 place count 111 transition count 108
Applied a total of 5 rules in 22 ms. Remains 111 /113 variables (removed 2) and now considering 108/110 (removed 2) transitions.
// Phase 1: matrix 108 rows 111 cols
[2023-03-09 02:45:34] [INFO ] Computed 15 place invariants in 4 ms
[2023-03-09 02:45:34] [INFO ] Implicit Places using invariants in 147 ms returned []
[2023-03-09 02:45:34] [INFO ] Invariant cache hit.
[2023-03-09 02:45:34] [INFO ] State equation strengthened by 14 read => feed constraints.
[2023-03-09 02:45:34] [INFO ] Implicit Places using invariants and state equation in 426 ms returned []
Implicit Place search using SMT with State Equation took 578 ms to find 0 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 2 : 111/118 places, 108/110 transitions.
Finished structural reductions in REACHABILITY mode , in 2 iterations and 1369 ms. Remains : 111/118 places, 108/110 transitions.
Incomplete random walk after 10000 steps, including 1035 resets, run finished after 359 ms. (steps per millisecond=27 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 78 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 78 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 79 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 74 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 77 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 79 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 67 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 73 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 76 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 71 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 78 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 69 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 76 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 68 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 73 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 15) seen :0
Interrupted probabilistic random walk after 210401 steps, run timeout after 3001 ms. (steps per millisecond=70 ) properties seen :{}
Probabilistic random walk after 210401 steps, saw 105211 distinct states, run finished after 3001 ms. (steps per millisecond=70 ) properties seen :0
Running SMT prover for 15 properties.
[2023-03-09 02:45:38] [INFO ] Invariant cache hit.
[2023-03-09 02:45:38] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-09 02:45:38] [INFO ] [Real]Absence check using 2 positive and 13 generalized place invariants in 5 ms returned sat
[2023-03-09 02:45:38] [INFO ] After 133ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:14
[2023-03-09 02:45:38] [INFO ] State equation strengthened by 14 read => feed constraints.
[2023-03-09 02:45:38] [INFO ] After 25ms SMT Verify possible using 14 Read/Feed constraints in real domain returned unsat :0 sat :0 real:15
[2023-03-09 02:45:38] [INFO ] After 305ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:15
[2023-03-09 02:45:38] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-09 02:45:39] [INFO ] [Nat]Absence check using 2 positive and 13 generalized place invariants in 5 ms returned sat
[2023-03-09 02:45:39] [INFO ] After 230ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :15
[2023-03-09 02:45:39] [INFO ] After 194ms SMT Verify possible using 14 Read/Feed constraints in natural domain returned unsat :0 sat :15
[2023-03-09 02:45:39] [INFO ] Deduced a trap composed of 5 places in 67 ms of which 1 ms to minimize.
[2023-03-09 02:45:39] [INFO ] Deduced a trap composed of 10 places in 61 ms of which 1 ms to minimize.
[2023-03-09 02:45:39] [INFO ] Deduced a trap composed of 17 places in 45 ms of which 1 ms to minimize.
[2023-03-09 02:45:39] [INFO ] Deduced a trap composed of 21 places in 44 ms of which 0 ms to minimize.
[2023-03-09 02:45:39] [INFO ] Deduced a trap composed of 20 places in 38 ms of which 0 ms to minimize.
[2023-03-09 02:45:39] [INFO ] Trap strengthening (SAT) tested/added 6/5 trap constraints in 315 ms
[2023-03-09 02:45:39] [INFO ] Deduced a trap composed of 16 places in 57 ms of which 1 ms to minimize.
[2023-03-09 02:45:39] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 75 ms
[2023-03-09 02:45:40] [INFO ] After 851ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :15
Attempting to minimize the solution found.
Minimization took 203 ms.
[2023-03-09 02:45:40] [INFO ] After 1432ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :15
Parikh walk visited 0 properties in 322 ms.
Support contains 25 out of 111 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 111/111 places, 108/108 transitions.
Applied a total of 0 rules in 7 ms. Remains 111 /111 variables (removed 0) and now considering 108/108 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 7 ms. Remains : 111/111 places, 108/108 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 111/111 places, 108/108 transitions.
Applied a total of 0 rules in 19 ms. Remains 111 /111 variables (removed 0) and now considering 108/108 (removed 0) transitions.
[2023-03-09 02:45:40] [INFO ] Invariant cache hit.
[2023-03-09 02:45:40] [INFO ] Implicit Places using invariants in 146 ms returned []
[2023-03-09 02:45:40] [INFO ] Invariant cache hit.
[2023-03-09 02:45:40] [INFO ] State equation strengthened by 14 read => feed constraints.
[2023-03-09 02:45:41] [INFO ] Implicit Places using invariants and state equation in 449 ms returned []
Implicit Place search using SMT with State Equation took 600 ms to find 0 implicit places.
[2023-03-09 02:45:41] [INFO ] Redundant transitions in 4 ms returned []
[2023-03-09 02:45:41] [INFO ] Invariant cache hit.
[2023-03-09 02:45:41] [INFO ] Dead Transitions using invariants and state equation in 160 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 795 ms. Remains : 111/111 places, 108/108 transitions.
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 3 Pre rules applied. Total rules applied 0 place count 111 transition count 105
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 6 place count 108 transition count 105
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 8 place count 106 transition count 103
Iterating global reduction 0 with 2 rules applied. Total rules applied 10 place count 106 transition count 103
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 0 with 1 rules applied. Total rules applied 11 place count 106 transition count 102
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 12 place count 105 transition count 102
Applied a total of 12 rules in 26 ms. Remains 105 /111 variables (removed 6) and now considering 102/108 (removed 6) transitions.
Running SMT prover for 15 properties.
// Phase 1: matrix 102 rows 105 cols
[2023-03-09 02:45:41] [INFO ] Computed 15 place invariants in 3 ms
[2023-03-09 02:45:41] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-09 02:45:41] [INFO ] [Real]Absence check using 2 positive and 13 generalized place invariants in 9 ms returned sat
[2023-03-09 02:45:41] [INFO ] After 206ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:15
[2023-03-09 02:45:41] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-09 02:45:41] [INFO ] [Nat]Absence check using 2 positive and 13 generalized place invariants in 8 ms returned sat
[2023-03-09 02:45:42] [INFO ] After 249ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :15
[2023-03-09 02:45:42] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-09 02:45:42] [INFO ] After 193ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :0 sat :15
[2023-03-09 02:45:42] [INFO ] Deduced a trap composed of 5 places in 64 ms of which 1 ms to minimize.
[2023-03-09 02:45:42] [INFO ] Deduced a trap composed of 17 places in 47 ms of which 1 ms to minimize.
[2023-03-09 02:45:42] [INFO ] Deduced a trap composed of 20 places in 41 ms of which 1 ms to minimize.
[2023-03-09 02:45:42] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 196 ms
[2023-03-09 02:45:42] [INFO ] Deduced a trap composed of 22 places in 43 ms of which 0 ms to minimize.
[2023-03-09 02:45:42] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 62 ms
[2023-03-09 02:45:42] [INFO ] Deduced a trap composed of 31 places in 38 ms of which 2 ms to minimize.
[2023-03-09 02:45:42] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 55 ms
[2023-03-09 02:45:42] [INFO ] After 766ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :15
Attempting to minimize the solution found.
Minimization took 193 ms.
[2023-03-09 02:45:43] [INFO ] After 1405ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :15
Successfully simplified 8 atomic propositions for a total of 16 simplifications.
FORMULA DoubleExponent-PT-004-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 02:45:43] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 26 ms
FORMULA DoubleExponent-PT-004-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 26 ms
[2023-03-09 02:45:43] [INFO ] Input system was already deterministic with 198 transitions.
Support contains 54 out of 211 places (down from 64) after GAL structural reductions.
Computed a total of 7 stabilizing places and 7 stable transitions
Graph (complete) has 352 edges and 211 vertex of which 209 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.6 ms
Starting structural reductions in LTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Applied a total of 0 rules in 7 ms. Remains 211 /211 variables (removed 0) and now considering 198/198 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 211/211 places, 198/198 transitions.
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 22 ms
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 23 ms
[2023-03-09 02:45:43] [INFO ] Input system was already deterministic with 198 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 49 transitions
Trivial Post-agglo rules discarded 49 transitions
Performed 49 trivial Post agglomeration. Transition count delta: 49
Iterating post reduction 0 with 49 rules applied. Total rules applied 49 place count 210 transition count 148
Reduce places removed 49 places and 0 transitions.
Iterating post reduction 1 with 49 rules applied. Total rules applied 98 place count 161 transition count 148
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 8 Pre rules applied. Total rules applied 98 place count 161 transition count 140
Deduced a syphon composed of 8 places in 1 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 114 place count 153 transition count 140
Performed 29 Post agglomeration using F-continuation condition.Transition count delta: 29
Deduced a syphon composed of 29 places in 1 ms
Reduce places removed 29 places and 0 transitions.
Iterating global reduction 2 with 58 rules applied. Total rules applied 172 place count 124 transition count 111
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 2 with 1 rules applied. Total rules applied 173 place count 123 transition count 110
Applied a total of 173 rules in 43 ms. Remains 123 /211 variables (removed 88) and now considering 110/198 (removed 88) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 43 ms. Remains : 123/211 places, 110/198 transitions.
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 14 ms
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 15 ms
[2023-03-09 02:45:43] [INFO ] Input system was already deterministic with 110 transitions.
Starting structural reductions in LTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Applied a total of 0 rules in 7 ms. Remains 211 /211 variables (removed 0) and now considering 198/198 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 211/211 places, 198/198 transitions.
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 22 ms
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 22 ms
[2023-03-09 02:45:43] [INFO ] Input system was already deterministic with 198 transitions.
Starting structural reductions in LTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Applied a total of 0 rules in 7 ms. Remains 211 /211 variables (removed 0) and now considering 198/198 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 211/211 places, 198/198 transitions.
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 18 ms
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 19 ms
[2023-03-09 02:45:43] [INFO ] Input system was already deterministic with 198 transitions.
Starting structural reductions in LTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Applied a total of 0 rules in 11 ms. Remains 211 /211 variables (removed 0) and now considering 198/198 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 211/211 places, 198/198 transitions.
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 18 ms
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 20 ms
[2023-03-09 02:45:43] [INFO ] Input system was already deterministic with 198 transitions.
Starting structural reductions in LTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Applied a total of 0 rules in 7 ms. Remains 211 /211 variables (removed 0) and now considering 198/198 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 211/211 places, 198/198 transitions.
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 18 ms
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 19 ms
[2023-03-09 02:45:43] [INFO ] Input system was already deterministic with 198 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 48 transitions
Trivial Post-agglo rules discarded 48 transitions
Performed 48 trivial Post agglomeration. Transition count delta: 48
Iterating post reduction 0 with 48 rules applied. Total rules applied 48 place count 210 transition count 149
Reduce places removed 48 places and 0 transitions.
Iterating post reduction 1 with 48 rules applied. Total rules applied 96 place count 162 transition count 149
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 7 Pre rules applied. Total rules applied 96 place count 162 transition count 142
Deduced a syphon composed of 7 places in 1 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 14 rules applied. Total rules applied 110 place count 155 transition count 142
Performed 29 Post agglomeration using F-continuation condition.Transition count delta: 29
Deduced a syphon composed of 29 places in 0 ms
Reduce places removed 29 places and 0 transitions.
Iterating global reduction 2 with 58 rules applied. Total rules applied 168 place count 126 transition count 113
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 2 with 1 rules applied. Total rules applied 169 place count 125 transition count 112
Applied a total of 169 rules in 37 ms. Remains 125 /211 variables (removed 86) and now considering 112/198 (removed 86) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 37 ms. Remains : 125/211 places, 112/198 transitions.
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 14 ms
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 12 ms
[2023-03-09 02:45:43] [INFO ] Input system was already deterministic with 112 transitions.
Starting structural reductions in LTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Applied a total of 0 rules in 7 ms. Remains 211 /211 variables (removed 0) and now considering 198/198 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 211/211 places, 198/198 transitions.
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 16 ms
[2023-03-09 02:45:43] [INFO ] Flatten gal took : 17 ms
[2023-03-09 02:45:43] [INFO ] Input system was already deterministic with 198 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 46 transitions
Trivial Post-agglo rules discarded 46 transitions
Performed 46 trivial Post agglomeration. Transition count delta: 46
Iterating post reduction 0 with 46 rules applied. Total rules applied 46 place count 210 transition count 151
Reduce places removed 46 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 47 rules applied. Total rules applied 93 place count 164 transition count 150
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 94 place count 163 transition count 150
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 9 Pre rules applied. Total rules applied 94 place count 163 transition count 141
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 3 with 18 rules applied. Total rules applied 112 place count 154 transition count 141
Performed 25 Post agglomeration using F-continuation condition.Transition count delta: 25
Deduced a syphon composed of 25 places in 1 ms
Reduce places removed 25 places and 0 transitions.
Iterating global reduction 3 with 50 rules applied. Total rules applied 162 place count 129 transition count 116
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 3 with 1 rules applied. Total rules applied 163 place count 128 transition count 115
Applied a total of 163 rules in 35 ms. Remains 128 /211 variables (removed 83) and now considering 115/198 (removed 83) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 128/211 places, 115/198 transitions.
[2023-03-09 02:45:44] [INFO ] Flatten gal took : 7 ms
[2023-03-09 02:45:44] [INFO ] Flatten gal took : 6 ms
[2023-03-09 02:45:44] [INFO ] Input system was already deterministic with 115 transitions.
Starting structural reductions in LTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Applied a total of 0 rules in 5 ms. Remains 211 /211 variables (removed 0) and now considering 198/198 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 211/211 places, 198/198 transitions.
[2023-03-09 02:45:44] [INFO ] Flatten gal took : 10 ms
[2023-03-09 02:45:44] [INFO ] Flatten gal took : 10 ms
[2023-03-09 02:45:44] [INFO ] Input system was already deterministic with 198 transitions.
Starting structural reductions in LTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Applied a total of 0 rules in 5 ms. Remains 211 /211 variables (removed 0) and now considering 198/198 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 211/211 places, 198/198 transitions.
[2023-03-09 02:45:44] [INFO ] Flatten gal took : 9 ms
[2023-03-09 02:45:44] [INFO ] Flatten gal took : 10 ms
[2023-03-09 02:45:44] [INFO ] Input system was already deterministic with 198 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 49 transitions
Trivial Post-agglo rules discarded 49 transitions
Performed 49 trivial Post agglomeration. Transition count delta: 49
Iterating post reduction 0 with 49 rules applied. Total rules applied 49 place count 210 transition count 148
Reduce places removed 49 places and 0 transitions.
Iterating post reduction 1 with 49 rules applied. Total rules applied 98 place count 161 transition count 148
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 8 Pre rules applied. Total rules applied 98 place count 161 transition count 140
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 114 place count 153 transition count 140
Performed 29 Post agglomeration using F-continuation condition.Transition count delta: 29
Deduced a syphon composed of 29 places in 1 ms
Reduce places removed 29 places and 0 transitions.
Iterating global reduction 2 with 58 rules applied. Total rules applied 172 place count 124 transition count 111
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 2 with 1 rules applied. Total rules applied 173 place count 123 transition count 110
Applied a total of 173 rules in 22 ms. Remains 123 /211 variables (removed 88) and now considering 110/198 (removed 88) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 123/211 places, 110/198 transitions.
[2023-03-09 02:45:44] [INFO ] Flatten gal took : 5 ms
[2023-03-09 02:45:44] [INFO ] Flatten gal took : 6 ms
[2023-03-09 02:45:44] [INFO ] Input system was already deterministic with 110 transitions.
Incomplete random walk after 10000 steps, including 1017 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 670 resets, run finished after 9 ms. (steps per millisecond=1111 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 963649 steps, run timeout after 3001 ms. (steps per millisecond=321 ) properties seen :{}
Probabilistic random walk after 963649 steps, saw 481931 distinct states, run finished after 3001 ms. (steps per millisecond=321 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 110 rows 123 cols
[2023-03-09 02:45:47] [INFO ] Computed 20 place invariants in 5 ms
[2023-03-09 02:45:47] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-09 02:45:47] [INFO ] [Real]Absence check using 2 positive and 18 generalized place invariants in 9 ms returned sat
[2023-03-09 02:45:47] [INFO ] After 68ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:45:47] [INFO ] State equation strengthened by 6 read => feed constraints.
[2023-03-09 02:45:47] [INFO ] After 13ms SMT Verify possible using 6 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:45:47] [INFO ] After 132ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:45:47] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-09 02:45:47] [INFO ] [Nat]Absence check using 2 positive and 18 generalized place invariants in 7 ms returned sat
[2023-03-09 02:45:47] [INFO ] After 68ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-09 02:45:47] [INFO ] After 12ms SMT Verify possible using 6 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-09 02:45:47] [INFO ] After 26ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-09 02:45:47] [INFO ] After 148ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 63 ms.
Support contains 1 out of 123 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 123/123 places, 110/110 transitions.
Graph (complete) has 295 edges and 123 vertex of which 121 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.1 ms
Discarding 2 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 4 place count 120 transition count 108
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 1 with 1 Pre rules applied. Total rules applied 4 place count 120 transition count 107
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 1 with 2 rules applied. Total rules applied 6 place count 119 transition count 107
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 1 with 20 rules applied. Total rules applied 26 place count 109 transition count 97
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 0
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 1 with 12 rules applied. Total rules applied 38 place count 103 transition count 97
Free-agglomeration rule (complex) applied 13 times.
Iterating global reduction 1 with 13 rules applied. Total rules applied 51 place count 103 transition count 84
Reduce places removed 13 places and 0 transitions.
Iterating post reduction 1 with 13 rules applied. Total rules applied 64 place count 90 transition count 84
Partial Free-agglomeration rule applied 15 times.
Drop transitions removed 15 transitions
Iterating global reduction 2 with 15 rules applied. Total rules applied 79 place count 90 transition count 84
Applied a total of 79 rules in 28 ms. Remains 90 /123 variables (removed 33) and now considering 84/110 (removed 26) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 28 ms. Remains : 90/123 places, 84/110 transitions.
Incomplete random walk after 1000000 steps, including 127373 resets, run finished after 1644 ms. (steps per millisecond=608 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000000 steps, including 84331 resets, run finished after 1049 ms. (steps per millisecond=953 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2019863 steps, run timeout after 6001 ms. (steps per millisecond=336 ) properties seen :{}
Probabilistic random walk after 2019863 steps, saw 1010068 distinct states, run finished after 6001 ms. (steps per millisecond=336 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 84 rows 90 cols
[2023-03-09 02:45:56] [INFO ] Computed 19 place invariants in 5 ms
[2023-03-09 02:45:56] [INFO ] [Real]Absence check using 3 positive place invariants in 2 ms returned sat
[2023-03-09 02:45:56] [INFO ] [Real]Absence check using 3 positive and 16 generalized place invariants in 10 ms returned sat
[2023-03-09 02:45:56] [INFO ] After 51ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:45:56] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:45:56] [INFO ] After 14ms SMT Verify possible using 13 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:45:56] [INFO ] After 118ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:45:56] [INFO ] [Nat]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-09 02:45:56] [INFO ] [Nat]Absence check using 3 positive and 16 generalized place invariants in 7 ms returned sat
[2023-03-09 02:45:56] [INFO ] After 45ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-09 02:45:56] [INFO ] After 14ms SMT Verify possible using 13 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-09 02:45:56] [INFO ] After 25ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 9 ms.
[2023-03-09 02:45:56] [INFO ] After 123ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 57 ms.
Support contains 1 out of 90 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 90/90 places, 84/84 transitions.
Applied a total of 0 rules in 7 ms. Remains 90 /90 variables (removed 0) and now considering 84/84 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 8 ms. Remains : 90/90 places, 84/84 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 90/90 places, 84/84 transitions.
Applied a total of 0 rules in 4 ms. Remains 90 /90 variables (removed 0) and now considering 84/84 (removed 0) transitions.
[2023-03-09 02:45:56] [INFO ] Invariant cache hit.
[2023-03-09 02:45:56] [INFO ] Implicit Places using invariants in 176 ms returned [20, 26, 58, 63, 81, 87]
Discarding 6 places :
Implicit Place search using SMT only with invariants took 178 ms to find 6 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 1 : 84/90 places, 84/84 transitions.
Free-agglomeration rule (complex) applied 3 times.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 84 transition count 81
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 6 place count 81 transition count 81
Applied a total of 6 rules in 7 ms. Remains 81 /84 variables (removed 3) and now considering 81/84 (removed 3) transitions.
// Phase 1: matrix 81 rows 81 cols
[2023-03-09 02:45:56] [INFO ] Computed 13 place invariants in 3 ms
[2023-03-09 02:45:56] [INFO ] Implicit Places using invariants in 131 ms returned []
[2023-03-09 02:45:56] [INFO ] Invariant cache hit.
[2023-03-09 02:45:57] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:45:57] [INFO ] Implicit Places using invariants and state equation in 411 ms returned []
Implicit Place search using SMT with State Equation took 544 ms to find 0 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 2 : 81/90 places, 81/84 transitions.
Finished structural reductions in REACHABILITY mode , in 2 iterations and 735 ms. Remains : 81/90 places, 81/84 transitions.
Incomplete random walk after 1000000 steps, including 142919 resets, run finished after 1364 ms. (steps per millisecond=733 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 90803 resets, run finished after 765 ms. (steps per millisecond=1307 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2081227 steps, run timeout after 6001 ms. (steps per millisecond=346 ) properties seen :{}
Probabilistic random walk after 2081227 steps, saw 1040615 distinct states, run finished after 6001 ms. (steps per millisecond=346 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-09 02:46:05] [INFO ] Invariant cache hit.
[2023-03-09 02:46:05] [INFO ] [Real]Absence check using 7 positive place invariants in 5 ms returned sat
[2023-03-09 02:46:05] [INFO ] [Real]Absence check using 7 positive and 6 generalized place invariants in 3 ms returned sat
[2023-03-09 02:46:05] [INFO ] After 57ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:46:05] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:46:05] [INFO ] After 23ms SMT Verify possible using 13 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:05] [INFO ] After 122ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:05] [INFO ] [Nat]Absence check using 7 positive place invariants in 6 ms returned sat
[2023-03-09 02:46:05] [INFO ] [Nat]Absence check using 7 positive and 6 generalized place invariants in 3 ms returned sat
[2023-03-09 02:46:05] [INFO ] After 63ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:05] [INFO ] After 22ms SMT Verify possible using 13 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:05] [INFO ] After 35ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 7 ms.
[2023-03-09 02:46:05] [INFO ] After 159ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 44 ms.
Support contains 1 out of 81 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 81/81 places, 81/81 transitions.
Applied a total of 0 rules in 3 ms. Remains 81 /81 variables (removed 0) and now considering 81/81 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3 ms. Remains : 81/81 places, 81/81 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 81/81 places, 81/81 transitions.
Applied a total of 0 rules in 5 ms. Remains 81 /81 variables (removed 0) and now considering 81/81 (removed 0) transitions.
[2023-03-09 02:46:05] [INFO ] Invariant cache hit.
[2023-03-09 02:46:05] [INFO ] Implicit Places using invariants in 150 ms returned []
[2023-03-09 02:46:05] [INFO ] Invariant cache hit.
[2023-03-09 02:46:06] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:46:06] [INFO ] Implicit Places using invariants and state equation in 408 ms returned []
Implicit Place search using SMT with State Equation took 559 ms to find 0 implicit places.
[2023-03-09 02:46:06] [INFO ] Redundant transitions in 2 ms returned []
[2023-03-09 02:46:06] [INFO ] Invariant cache hit.
[2023-03-09 02:46:06] [INFO ] Dead Transitions using invariants and state equation in 131 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 707 ms. Remains : 81/81 places, 81/81 transitions.
Incomplete random walk after 100000 steps, including 14345 resets, run finished after 430 ms. (steps per millisecond=232 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-09 02:46:06] [INFO ] Invariant cache hit.
[2023-03-09 02:46:06] [INFO ] [Real]Absence check using 7 positive place invariants in 6 ms returned sat
[2023-03-09 02:46:07] [INFO ] [Real]Absence check using 7 positive and 6 generalized place invariants in 4 ms returned sat
[2023-03-09 02:46:07] [INFO ] After 60ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:46:07] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:46:07] [INFO ] After 15ms SMT Verify possible using 13 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-09 02:46:07] [INFO ] After 30ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:07] [INFO ] After 143ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:07] [INFO ] [Nat]Absence check using 7 positive place invariants in 5 ms returned sat
[2023-03-09 02:46:07] [INFO ] [Nat]Absence check using 7 positive and 6 generalized place invariants in 3 ms returned sat
[2023-03-09 02:46:07] [INFO ] After 57ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:07] [INFO ] After 16ms SMT Verify possible using 13 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:07] [INFO ] After 32ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 12 ms.
[2023-03-09 02:46:07] [INFO ] After 151ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Incomplete random walk after 1000000 steps, including 143288 resets, run finished after 1378 ms. (steps per millisecond=725 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000000 steps, including 90772 resets, run finished after 751 ms. (steps per millisecond=1331 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2148022 steps, run timeout after 6001 ms. (steps per millisecond=357 ) properties seen :{}
Probabilistic random walk after 2148022 steps, saw 1074007 distinct states, run finished after 6003 ms. (steps per millisecond=357 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-09 02:46:15] [INFO ] Invariant cache hit.
[2023-03-09 02:46:15] [INFO ] [Real]Absence check using 7 positive place invariants in 5 ms returned sat
[2023-03-09 02:46:15] [INFO ] [Real]Absence check using 7 positive and 6 generalized place invariants in 2 ms returned sat
[2023-03-09 02:46:15] [INFO ] After 42ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:46:15] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:46:15] [INFO ] After 14ms SMT Verify possible using 13 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:15] [INFO ] After 93ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:15] [INFO ] [Nat]Absence check using 7 positive place invariants in 4 ms returned sat
[2023-03-09 02:46:15] [INFO ] [Nat]Absence check using 7 positive and 6 generalized place invariants in 3 ms returned sat
[2023-03-09 02:46:15] [INFO ] After 55ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:15] [INFO ] After 23ms SMT Verify possible using 13 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:15] [INFO ] After 36ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 9 ms.
[2023-03-09 02:46:15] [INFO ] After 139ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 47 ms.
Support contains 1 out of 81 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 81/81 places, 81/81 transitions.
Applied a total of 0 rules in 3 ms. Remains 81 /81 variables (removed 0) and now considering 81/81 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3 ms. Remains : 81/81 places, 81/81 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 81/81 places, 81/81 transitions.
Applied a total of 0 rules in 3 ms. Remains 81 /81 variables (removed 0) and now considering 81/81 (removed 0) transitions.
[2023-03-09 02:46:15] [INFO ] Invariant cache hit.
[2023-03-09 02:46:15] [INFO ] Implicit Places using invariants in 162 ms returned []
[2023-03-09 02:46:15] [INFO ] Invariant cache hit.
[2023-03-09 02:46:15] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:46:16] [INFO ] Implicit Places using invariants and state equation in 407 ms returned []
Implicit Place search using SMT with State Equation took 570 ms to find 0 implicit places.
[2023-03-09 02:46:16] [INFO ] Redundant transitions in 2 ms returned []
[2023-03-09 02:46:16] [INFO ] Invariant cache hit.
[2023-03-09 02:46:16] [INFO ] Dead Transitions using invariants and state equation in 133 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 722 ms. Remains : 81/81 places, 81/81 transitions.
Incomplete random walk after 100000 steps, including 14315 resets, run finished after 196 ms. (steps per millisecond=510 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-09 02:46:16] [INFO ] Invariant cache hit.
[2023-03-09 02:46:16] [INFO ] [Real]Absence check using 7 positive place invariants in 7 ms returned sat
[2023-03-09 02:46:16] [INFO ] [Real]Absence check using 7 positive and 6 generalized place invariants in 4 ms returned sat
[2023-03-09 02:46:16] [INFO ] After 63ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:46:16] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:46:16] [INFO ] After 16ms SMT Verify possible using 13 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-09 02:46:16] [INFO ] After 31ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:16] [INFO ] After 147ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:16] [INFO ] [Nat]Absence check using 7 positive place invariants in 5 ms returned sat
[2023-03-09 02:46:16] [INFO ] [Nat]Absence check using 7 positive and 6 generalized place invariants in 4 ms returned sat
[2023-03-09 02:46:16] [INFO ] After 61ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:16] [INFO ] After 18ms SMT Verify possible using 13 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:16] [INFO ] After 32ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-03-09 02:46:16] [INFO ] After 147ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Incomplete random walk after 10000 steps, including 1446 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 924 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 994472 steps, run timeout after 3001 ms. (steps per millisecond=331 ) properties seen :{}
Probabilistic random walk after 994472 steps, saw 497331 distinct states, run finished after 3001 ms. (steps per millisecond=331 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-09 02:46:19] [INFO ] Invariant cache hit.
[2023-03-09 02:46:19] [INFO ] [Real]Absence check using 7 positive place invariants in 4 ms returned sat
[2023-03-09 02:46:19] [INFO ] [Real]Absence check using 7 positive and 6 generalized place invariants in 2 ms returned sat
[2023-03-09 02:46:20] [INFO ] After 39ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:46:20] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:46:20] [INFO ] After 14ms SMT Verify possible using 13 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:20] [INFO ] After 92ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:20] [INFO ] [Nat]Absence check using 7 positive place invariants in 5 ms returned sat
[2023-03-09 02:46:20] [INFO ] [Nat]Absence check using 7 positive and 6 generalized place invariants in 4 ms returned sat
[2023-03-09 02:46:20] [INFO ] After 69ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:20] [INFO ] After 29ms SMT Verify possible using 13 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:20] [INFO ] After 43ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 8 ms.
[2023-03-09 02:46:20] [INFO ] After 175ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 2 ms.
Support contains 1 out of 81 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 81/81 places, 81/81 transitions.
Applied a total of 0 rules in 3 ms. Remains 81 /81 variables (removed 0) and now considering 81/81 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3 ms. Remains : 81/81 places, 81/81 transitions.
Incomplete random walk after 10000 steps, including 1480 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 929 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 976146 steps, run timeout after 3001 ms. (steps per millisecond=325 ) properties seen :{}
Probabilistic random walk after 976146 steps, saw 488162 distinct states, run finished after 3001 ms. (steps per millisecond=325 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-09 02:46:23] [INFO ] Invariant cache hit.
[2023-03-09 02:46:23] [INFO ] [Real]Absence check using 7 positive place invariants in 5 ms returned sat
[2023-03-09 02:46:23] [INFO ] [Real]Absence check using 7 positive and 6 generalized place invariants in 3 ms returned sat
[2023-03-09 02:46:23] [INFO ] After 45ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:46:23] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:46:23] [INFO ] After 14ms SMT Verify possible using 13 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:23] [INFO ] After 100ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:23] [INFO ] [Nat]Absence check using 7 positive place invariants in 4 ms returned sat
[2023-03-09 02:46:23] [INFO ] [Nat]Absence check using 7 positive and 6 generalized place invariants in 4 ms returned sat
[2023-03-09 02:46:23] [INFO ] After 42ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:23] [INFO ] After 14ms SMT Verify possible using 13 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:23] [INFO ] After 23ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-09 02:46:23] [INFO ] After 109ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 1 out of 81 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 81/81 places, 81/81 transitions.
Applied a total of 0 rules in 8 ms. Remains 81 /81 variables (removed 0) and now considering 81/81 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 8 ms. Remains : 81/81 places, 81/81 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 81/81 places, 81/81 transitions.
Applied a total of 0 rules in 2 ms. Remains 81 /81 variables (removed 0) and now considering 81/81 (removed 0) transitions.
[2023-03-09 02:46:23] [INFO ] Invariant cache hit.
[2023-03-09 02:46:23] [INFO ] Implicit Places using invariants in 79 ms returned []
[2023-03-09 02:46:23] [INFO ] Invariant cache hit.
[2023-03-09 02:46:23] [INFO ] State equation strengthened by 13 read => feed constraints.
[2023-03-09 02:46:23] [INFO ] Implicit Places using invariants and state equation in 297 ms returned []
Implicit Place search using SMT with State Equation took 376 ms to find 0 implicit places.
[2023-03-09 02:46:23] [INFO ] Redundant transitions in 2 ms returned []
[2023-03-09 02:46:23] [INFO ] Invariant cache hit.
[2023-03-09 02:46:23] [INFO ] Dead Transitions using invariants and state equation in 98 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 487 ms. Remains : 81/81 places, 81/81 transitions.
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 6 Pre rules applied. Total rules applied 0 place count 81 transition count 75
Deduced a syphon composed of 6 places in 1 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 0 with 12 rules applied. Total rules applied 12 place count 75 transition count 75
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 15 place count 72 transition count 72
Iterating global reduction 0 with 3 rules applied. Total rules applied 18 place count 72 transition count 72
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 20 place count 71 transition count 71
Free-agglomeration rule (complex) applied 2 times.
Iterating global reduction 0 with 2 rules applied. Total rules applied 22 place count 71 transition count 69
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 24 place count 69 transition count 69
Applied a total of 24 rules in 8 ms. Remains 69 /81 variables (removed 12) and now considering 69/81 (removed 12) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 69 rows 69 cols
[2023-03-09 02:46:23] [INFO ] Computed 13 place invariants in 3 ms
[2023-03-09 02:46:23] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-09 02:46:24] [INFO ] [Real]Absence check using 3 positive and 10 generalized place invariants in 5 ms returned sat
[2023-03-09 02:46:24] [INFO ] After 51ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:46:24] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-09 02:46:24] [INFO ] After 8ms SMT Verify possible using 1 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-09 02:46:24] [INFO ] After 19ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 7 ms.
[2023-03-09 02:46:24] [INFO ] After 120ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :1
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 6 Pre rules applied. Total rules applied 0 place count 81 transition count 75
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 0 with 12 rules applied. Total rules applied 12 place count 75 transition count 75
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 15 place count 72 transition count 72
Iterating global reduction 0 with 3 rules applied. Total rules applied 18 place count 72 transition count 72
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 20 place count 71 transition count 71
Free-agglomeration rule (complex) applied 2 times.
Iterating global reduction 0 with 2 rules applied. Total rules applied 22 place count 71 transition count 69
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 24 place count 69 transition count 69
Applied a total of 24 rules in 11 ms. Remains 69 /81 variables (removed 12) and now considering 69/81 (removed 12) transitions.
Running SMT prover for 1 properties.
[2023-03-09 02:46:24] [INFO ] Invariant cache hit.
[2023-03-09 02:46:24] [INFO ] [Real]Absence check using 3 positive place invariants in 3 ms returned sat
[2023-03-09 02:46:24] [INFO ] [Real]Absence check using 3 positive and 10 generalized place invariants in 6 ms returned sat
[2023-03-09 02:46:24] [INFO ] After 59ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-09 02:46:24] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-09 02:46:24] [INFO ] After 8ms SMT Verify possible using 1 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:24] [INFO ] After 114ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-09 02:46:24] [INFO ] [Nat]Absence check using 3 positive place invariants in 3 ms returned sat
[2023-03-09 02:46:24] [INFO ] [Nat]Absence check using 3 positive and 10 generalized place invariants in 5 ms returned sat
[2023-03-09 02:46:24] [INFO ] After 55ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:24] [INFO ] After 7ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-09 02:46:24] [INFO ] After 18ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 9 ms.
[2023-03-09 02:46:24] [INFO ] After 132ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in SI_CTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 49 transitions
Trivial Post-agglo rules discarded 49 transitions
Performed 49 trivial Post agglomeration. Transition count delta: 49
Iterating post reduction 0 with 49 rules applied. Total rules applied 49 place count 210 transition count 148
Reduce places removed 49 places and 0 transitions.
Iterating post reduction 1 with 49 rules applied. Total rules applied 98 place count 161 transition count 148
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 9 Pre rules applied. Total rules applied 98 place count 161 transition count 139
Deduced a syphon composed of 9 places in 1 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 2 with 18 rules applied. Total rules applied 116 place count 152 transition count 139
Performed 27 Post agglomeration using F-continuation condition.Transition count delta: 27
Deduced a syphon composed of 27 places in 0 ms
Reduce places removed 27 places and 0 transitions.
Iterating global reduction 2 with 54 rules applied. Total rules applied 170 place count 125 transition count 112
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 2 with 1 rules applied. Total rules applied 171 place count 124 transition count 111
Applied a total of 171 rules in 24 ms. Remains 124 /211 variables (removed 87) and now considering 111/198 (removed 87) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 124/211 places, 111/198 transitions.
[2023-03-09 02:46:24] [INFO ] Flatten gal took : 10 ms
[2023-03-09 02:46:24] [INFO ] Flatten gal took : 9 ms
[2023-03-09 02:46:24] [INFO ] Input system was already deterministic with 111 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 211/211 places, 198/198 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 43 transitions
Trivial Post-agglo rules discarded 43 transitions
Performed 43 trivial Post agglomeration. Transition count delta: 43
Iterating post reduction 0 with 43 rules applied. Total rules applied 43 place count 210 transition count 154
Reduce places removed 43 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 1 with 46 rules applied. Total rules applied 89 place count 167 transition count 151
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 92 place count 164 transition count 151
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 9 Pre rules applied. Total rules applied 92 place count 164 transition count 142
Deduced a syphon composed of 9 places in 1 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 3 with 18 rules applied. Total rules applied 110 place count 155 transition count 142
Performed 28 Post agglomeration using F-continuation condition.Transition count delta: 28
Deduced a syphon composed of 28 places in 0 ms
Reduce places removed 28 places and 0 transitions.
Iterating global reduction 3 with 56 rules applied. Total rules applied 166 place count 127 transition count 114
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 3 with 2 rules applied. Total rules applied 168 place count 127 transition count 114
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 3 with 1 rules applied. Total rules applied 169 place count 126 transition count 113
Applied a total of 169 rules in 23 ms. Remains 126 /211 variables (removed 85) and now considering 113/198 (removed 85) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 126/211 places, 113/198 transitions.
[2023-03-09 02:46:24] [INFO ] Flatten gal took : 9 ms
[2023-03-09 02:46:24] [INFO ] Flatten gal took : 8 ms
[2023-03-09 02:46:24] [INFO ] Input system was already deterministic with 113 transitions.
[2023-03-09 02:46:24] [INFO ] Flatten gal took : 14 ms
[2023-03-09 02:46:24] [INFO ] Flatten gal took : 13 ms
[2023-03-09 02:46:24] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-09 02:46:24] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 211 places, 198 transitions and 551 arcs took 3 ms.
Total runtime 79749 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DoubleExponent-PT-004
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/371
CTLFireability

FORMULA DoubleExponent-PT-004-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-004-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-004-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-004-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-004-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-004-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-004-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-004-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-004-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 8803300 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16103112 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/371/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/371/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/371/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 46 (type EXCL) for 3 DoubleExponent-PT-004-CTLFireability-01
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 46 (type EXCL) for DoubleExponent-PT-004-CTLFireability-01
lola: result : true
lola: markings : 8
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DoubleExponent-PT-004-CTLFireability-00
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 47 (type FNDP) for 37 DoubleExponent-PT-004-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 48 (type EQUN) for 37 DoubleExponent-PT-004-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SRCH) for 37 DoubleExponent-PT-004-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 50 (type SRCH) for DoubleExponent-PT-004-CTLFireability-13
lola: result : unknown
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/371/CTLFireability-48.sara.
sara: place or transition ordering is non-deterministic
sara: warning, failure of lp_solve (at job 61)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 4/257 11/32 DoubleExponent-PT-004-CTLFireability-00 1669189 m, 333837 m/sec, 1669189 t fired, .
47 EF FNDP 4/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1930043 t fired, 197449 attempts, .
48 EF STEQ 4/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 sara is running.

Time elapsed: 5 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 14
lola: FINISHED task # 48 (type EQUN) for DoubleExponent-PT-004-CTLFireability-13
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 9/257 20/32 DoubleExponent-PT-004-CTLFireability-00 3516119 m, 369386 m/sec, 3516119 t fired, .
47 EF FNDP 9/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 4118339 t fired, 421811 attempts, .

Time elapsed: 10 secs. Pages in use: 20
# running tasks: 2 of 4 Visible: 14
lola: FINISHED task # 1 (type EXCL) for DoubleExponent-PT-004-CTLFireability-00
lola: result : false
lola: markings : 4786241
lola: fired transitions : 4786240
lola: time used : 13.000000
lola: memory pages used : 25
lola: LAUNCH task # 35 (type EXCL) for 34 DoubleExponent-PT-004-CTLFireability-12
lola: time limit : 275 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 1/275 4/32 DoubleExponent-PT-004-CTLFireability-12 523944 m, 104788 m/sec, 523944 t fired, .
47 EF FNDP 14/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 6397639 t fired, 655224 attempts, .

Time elapsed: 15 secs. Pages in use: 25
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 6/275 14/32 DoubleExponent-PT-004-CTLFireability-12 2196038 m, 334418 m/sec, 2196038 t fired, .
47 EF FNDP 19/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 8678584 t fired, 889320 attempts, .

Time elapsed: 20 secs. Pages in use: 25
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 11/275 21/32 DoubleExponent-PT-004-CTLFireability-12 3836857 m, 328163 m/sec, 3836857 t fired, .
47 EF FNDP 24/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 10956821 t fired, 1122898 attempts, .

Time elapsed: 25 secs. Pages in use: 25
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 16/275 28/32 DoubleExponent-PT-004-CTLFireability-12 5394406 m, 311509 m/sec, 5394406 t fired, .
47 EF FNDP 29/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 13235595 t fired, 1356537 attempts, .

Time elapsed: 30 secs. Pages in use: 28
# running tasks: 2 of 4 Visible: 14
lola: CANCELED task # 35 (type EXCL) for DoubleExponent-PT-004-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 34/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 15527064 t fired, 1591372 attempts, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: LAUNCH task # 32 (type EXCL) for 27 DoubleExponent-PT-004-CTLFireability-11
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for DoubleExponent-PT-004-CTLFireability-11
lola: result : true
lola: markings : 36
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 27 DoubleExponent-PT-004-CTLFireability-11
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for DoubleExponent-PT-004-CTLFireability-11
lola: result : true
lola: markings : 69
lola: fired transitions : 68
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 DoubleExponent-PT-004-CTLFireability-09
lola: time limit : 356 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/356 8/32 DoubleExponent-PT-004-CTLFireability-09 1221897 m, 244379 m/sec, 2443795 t fired, .
47 EF FNDP 39/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 17804984 t fired, 1825110 attempts, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/356 15/32 DoubleExponent-PT-004-CTLFireability-09 2431289 m, 241878 m/sec, 4862579 t fired, .
47 EF FNDP 44/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 20082440 t fired, 2058524 attempts, .

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/356 20/32 DoubleExponent-PT-004-CTLFireability-09 3627686 m, 239279 m/sec, 7255374 t fired, .
47 EF FNDP 49/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 22359725 t fired, 2292147 attempts, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/356 25/32 DoubleExponent-PT-004-CTLFireability-09 4788062 m, 232075 m/sec, 9576125 t fired, .
47 EF FNDP 54/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 24637677 t fired, 2525589 attempts, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 25/356 30/32 DoubleExponent-PT-004-CTLFireability-09 5922144 m, 226816 m/sec, 11844289 t fired, .
47 EF FNDP 59/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 26913013 t fired, 2758988 attempts, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: CANCELED task # 22 (type EXCL) for DoubleExponent-PT-004-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 64/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 29201796 t fired, 2993722 attempts, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: LAUNCH task # 16 (type EXCL) for 15 DoubleExponent-PT-004-CTLFireability-07
lola: time limit : 392 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for DoubleExponent-PT-004-CTLFireability-07
lola: result : false
lola: markings : 857
lola: fired transitions : 1738
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 DoubleExponent-PT-004-CTLFireability-06
lola: time limit : 441 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/441 11/32 DoubleExponent-PT-004-CTLFireability-06 1688894 m, 337778 m/sec, 1688894 t fired, .
47 EF FNDP 69/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 31475217 t fired, 3226635 attempts, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/441 19/32 DoubleExponent-PT-004-CTLFireability-06 3355224 m, 333266 m/sec, 3355224 t fired, .
47 EF FNDP 74/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 33752012 t fired, 3459985 attempts, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/441 26/32 DoubleExponent-PT-004-CTLFireability-06 4941327 m, 317220 m/sec, 4941326 t fired, .
47 EF FNDP 79/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 36028163 t fired, 3693280 attempts, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: CANCELED task # 13 (type EXCL) for DoubleExponent-PT-004-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 84/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 38306060 t fired, 3926812 attempts, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: LAUNCH task # 10 (type EXCL) for 9 DoubleExponent-PT-004-CTLFireability-04
lola: time limit : 502 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for DoubleExponent-PT-004-CTLFireability-04
lola: result : true
lola: markings : 25
lola: fired transitions : 49
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 DoubleExponent-PT-004-CTLFireability-02
lola: time limit : 585 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/585 7/32 DoubleExponent-PT-004-CTLFireability-02 1059033 m, 211806 m/sec, 2135833 t fired, .
47 EF FNDP 89/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 40586004 t fired, 4160638 attempts, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/585 13/32 DoubleExponent-PT-004-CTLFireability-02 2106413 m, 209476 m/sec, 4246953 t fired, .
47 EF FNDP 94/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 42862271 t fired, 4393646 attempts, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/585 20/32 DoubleExponent-PT-004-CTLFireability-02 3639183 m, 306554 m/sec, 6062395 t fired, .
47 EF FNDP 99/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 45139589 t fired, 4626957 attempts, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/585 27/32 DoubleExponent-PT-004-CTLFireability-02 5256122 m, 323387 m/sec, 7679334 t fired, .
47 EF FNDP 104/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 47416422 t fired, 4860332 attempts, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: CANCELED task # 7 (type EXCL) for DoubleExponent-PT-004-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 109/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 49698661 t fired, 5094131 attempts, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: LAUNCH task # 49 (type EXCL) for 37 DoubleExponent-PT-004-CTLFireability-13
lola: time limit : 698 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 114/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 51989739 t fired, 5329467 attempts, .
49 EF EXCL 5/698 9/32 DoubleExponent-PT-004-CTLFireability-13 1941697 m, 388339 m/sec, 1941696 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 120/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 54274762 t fired, 5563301 attempts, .
49 EF EXCL 11/698 16/32 DoubleExponent-PT-004-CTLFireability-13 3792062 m, 370073 m/sec, 3792061 t fired, .

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 125/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 56559973 t fired, 5797585 attempts, .
49 EF EXCL 16/698 23/32 DoubleExponent-PT-004-CTLFireability-13 5575688 m, 356725 m/sec, 5575687 t fired, .

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 130/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 58852363 t fired, 6032841 attempts, .
49 EF EXCL 21/698 30/32 DoubleExponent-PT-004-CTLFireability-13 7339324 m, 352727 m/sec, 7339324 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: CANCELED task # 49 (type EXCL) for DoubleExponent-PT-004-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-10: EU 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-004-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 135/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 61148039 t fired, 6267896 attempts, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: LAUNCH task # 25 (type EXCL) for 24 DoubleExponent-PT-004-CTLFireability-10
lola: time limit : 866 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for DoubleExponent-PT-004-CTLFireability-10
lola: result : true
lola: markings : 2116
lola: fired transitions : 2115
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 DoubleExponent-PT-004-CTLFireability-14
lola: time limit : 1154 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for DoubleExponent-PT-004-CTLFireability-14
lola: result : true
lola: markings : 509
lola: fired transitions : 517
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 DoubleExponent-PT-004-CTLFireability-08
lola: time limit : 1732 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/1732 5/32 DoubleExponent-PT-004-CTLFireability-08 842912 m, 168582 m/sec, 3220050 t fired, .
47 EF FNDP 140/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 63428938 t fired, 6501716 attempts, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/1732 9/32 DoubleExponent-PT-004-CTLFireability-08 1681812 m, 167780 m/sec, 6424983 t fired, .
47 EF FNDP 145/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 65703904 t fired, 6734749 attempts, .

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-004-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/1732 13/32 DoubleExponent-PT-004-CTLFireability-08 2508738 m, 165385 m/sec, 9583923 t fired, .
47 EF FNDP 150/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 67978811 t fired, 6967728 attempts, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: FINISHED task # 19 (type EXCL) for DoubleExponent-PT-004-CTLFireability-08
lola: result : false
lola: markings : 2828181
lola: fired transitions : 10804205
lola: time used : 16.000000
lola: memory pages used : 15
lola: LAUNCH task # 44 (type EXCL) for 43 DoubleExponent-PT-004-CTLFireability-15
lola: time limit : 3448 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for DoubleExponent-PT-004-CTLFireability-15
lola: result : true
lola: markings : 1413332
lola: fired transitions : 1413350
lola: time used : 3.000000
lola: memory pages used : 8
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 155/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 70256210 t fired, 7201322 attempts, .

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 160/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 72559710 t fired, 7437563 attempts, .

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 165/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 74863101 t fired, 7673791 attempts, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 170/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 77164814 t fired, 7909891 attempts, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 175/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 79467504 t fired, 8146167 attempts, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 180/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 81770286 t fired, 8381857 attempts, .

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 185/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 84072757 t fired, 8618327 attempts, .

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 190/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 86373542 t fired, 8853862 attempts, .

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 195/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 88675876 t fired, 9090278 attempts, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 200/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 90976072 t fired, 9325942 attempts, .

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 205/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 93273128 t fired, 9561640 attempts, .

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 210/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 95572221 t fired, 9797117 attempts, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 215/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 97870687 t fired, 10032544 attempts, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 220/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 100170621 t fired, 10268428 attempts, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 225/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 102470103 t fired, 10504204 attempts, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 230/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 104768603 t fired, 10739805 attempts, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 235/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 107069377 t fired, 10975787 attempts, .

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 240/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 109367544 t fired, 11211618 attempts, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 245/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 111668369 t fired, 11447512 attempts, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 250/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 113972090 t fired, 11683786 attempts, .

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 255/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 116276279 t fired, 11919959 attempts, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 260/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 118578167 t fired, 12155939 attempts, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 265/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 120879041 t fired, 12391694 attempts, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 270/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 123178315 t fired, 12627130 attempts, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 275/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 125476891 t fired, 12862714 attempts, .

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 280/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 127774932 t fired, 13098638 attempts, .

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 285/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 130074691 t fired, 13334529 attempts, .

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 290/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 132378810 t fired, 13570763 attempts, .

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 295/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 134680655 t fired, 13806725 attempts, .

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 300/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 136976479 t fired, 14042077 attempts, .

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 305/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 139278415 t fired, 14278166 attempts, .

Time elapsed: 306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 310/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 141575522 t fired, 14513759 attempts, .

Time elapsed: 311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 315/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 143878912 t fired, 14749905 attempts, .

Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 320/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 146182103 t fired, 14985907 attempts, .

Time elapsed: 321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 325/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 148484658 t fired, 15221858 attempts, .

Time elapsed: 326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 330/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 150786971 t fired, 15457875 attempts, .

Time elapsed: 331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 335/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 153087231 t fired, 15693557 attempts, .

Time elapsed: 336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 340/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 155385856 t fired, 15929277 attempts, .

Time elapsed: 341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 345/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 157684149 t fired, 16164830 attempts, .

Time elapsed: 346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 350/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 159983679 t fired, 16400732 attempts, .

Time elapsed: 351 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 355/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 162284208 t fired, 16636419 attempts, .

Time elapsed: 356 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 360/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 164586016 t fired, 16872740 attempts, .

Time elapsed: 361 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 365/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 166887904 t fired, 17108843 attempts, .

Time elapsed: 366 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 370/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 169189287 t fired, 17345079 attempts, .

Time elapsed: 371 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 375/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 171489847 t fired, 17581217 attempts, .

Time elapsed: 376 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 380/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 173790976 t fired, 17817152 attempts, .

Time elapsed: 381 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 385/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 176092493 t fired, 18053384 attempts, .

Time elapsed: 386 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 390/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 178397358 t fired, 18289779 attempts, .

Time elapsed: 391 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 395/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 180701286 t fired, 18526298 attempts, .

Time elapsed: 396 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 400/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 183005724 t fired, 18762806 attempts, .

Time elapsed: 401 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 405/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 185308035 t fired, 18998912 attempts, .

Time elapsed: 406 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 410/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 187610633 t fired, 19234994 attempts, .

Time elapsed: 411 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 415/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 189913518 t fired, 19471238 attempts, .

Time elapsed: 416 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 420/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 192212848 t fired, 19707009 attempts, .

Time elapsed: 421 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 425/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 194515316 t fired, 19942989 attempts, .

Time elapsed: 426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 430/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 196818531 t fired, 20179045 attempts, .

Time elapsed: 431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 435/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 199122126 t fired, 20414941 attempts, .

Time elapsed: 436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 440/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 201427174 t fired, 20651264 attempts, .

Time elapsed: 441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 445/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 203728424 t fired, 20886926 attempts, .

Time elapsed: 446 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 450/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 206031643 t fired, 21123192 attempts, .

Time elapsed: 451 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 455/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 208334638 t fired, 21359200 attempts, .

Time elapsed: 456 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 460/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 210638394 t fired, 21595436 attempts, .

Time elapsed: 461 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 465/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 212942683 t fired, 21831460 attempts, .

Time elapsed: 466 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 470/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 215244219 t fired, 22067666 attempts, .

Time elapsed: 471 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 475/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 217547430 t fired, 22303962 attempts, .

Time elapsed: 476 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 480/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 219846377 t fired, 22539780 attempts, .

Time elapsed: 481 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 485/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 222147919 t fired, 22775862 attempts, .

Time elapsed: 486 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 490/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 224450441 t fired, 23011712 attempts, .

Time elapsed: 491 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 495/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 226754972 t fired, 23248342 attempts, .

Time elapsed: 496 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 500/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 229060192 t fired, 23484844 attempts, .

Time elapsed: 501 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 505/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 231365596 t fired, 23721382 attempts, .

Time elapsed: 506 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 510/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 233669702 t fired, 23958125 attempts, .

Time elapsed: 511 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 515/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 235973940 t fired, 24194211 attempts, .

Time elapsed: 516 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 520/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 238279175 t fired, 24430315 attempts, .

Time elapsed: 521 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 525/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 240584403 t fired, 24666263 attempts, .

Time elapsed: 526 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 530/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 242886423 t fired, 24902062 attempts, .

Time elapsed: 531 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 535/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 245191049 t fired, 25138028 attempts, .

Time elapsed: 536 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 540/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 247494224 t fired, 25374393 attempts, .

Time elapsed: 541 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 545/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 249795725 t fired, 25610278 attempts, .

Time elapsed: 546 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 550/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 252093731 t fired, 25845817 attempts, .

Time elapsed: 551 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 555/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 254391351 t fired, 26081002 attempts, .

Time elapsed: 556 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 560/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 256689247 t fired, 26316521 attempts, .

Time elapsed: 561 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 565/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 258988592 t fired, 26552382 attempts, .

Time elapsed: 566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 570/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 261288089 t fired, 26788071 attempts, .

Time elapsed: 571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 575/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 263589654 t fired, 27024313 attempts, .

Time elapsed: 576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 580/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 265891719 t fired, 27260696 attempts, .

Time elapsed: 581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 585/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 268195424 t fired, 27497042 attempts, .

Time elapsed: 586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 590/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 270496323 t fired, 27732780 attempts, .

Time elapsed: 591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 595/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 272796704 t fired, 27969046 attempts, .

Time elapsed: 596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 600/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 275093965 t fired, 28204817 attempts, .

Time elapsed: 601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 605/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 277394652 t fired, 28440667 attempts, .

Time elapsed: 606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 610/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 279696540 t fired, 28676944 attempts, .

Time elapsed: 611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 615/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 281999107 t fired, 28912788 attempts, .

Time elapsed: 616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 620/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 284302174 t fired, 29149099 attempts, .

Time elapsed: 621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 625/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 286600635 t fired, 29384246 attempts, .

Time elapsed: 626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 630/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 288899378 t fired, 29619862 attempts, .

Time elapsed: 631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 635/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 291201037 t fired, 29856178 attempts, .

Time elapsed: 636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 640/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 293503552 t fired, 30092431 attempts, .

Time elapsed: 641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 645/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 295801332 t fired, 30328119 attempts, .

Time elapsed: 646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 650/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 298101196 t fired, 30563890 attempts, .

Time elapsed: 651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 655/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 300400936 t fired, 30799482 attempts, .

Time elapsed: 656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 660/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 302699029 t fired, 31035096 attempts, .

Time elapsed: 661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 665/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 304997556 t fired, 31270508 attempts, .

Time elapsed: 666 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 670/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 307295386 t fired, 31506102 attempts, .

Time elapsed: 671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 675/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 309593160 t fired, 31741742 attempts, .

Time elapsed: 676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 680/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 311891225 t fired, 31977122 attempts, .

Time elapsed: 681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 685/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 314189726 t fired, 32212843 attempts, .

Time elapsed: 686 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 690/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 316490645 t fired, 32448096 attempts, .

Time elapsed: 691 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 695/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 318792852 t fired, 32684010 attempts, .

Time elapsed: 696 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 700/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 321093363 t fired, 32919939 attempts, .

Time elapsed: 701 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 705/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 323396049 t fired, 33155807 attempts, .

Time elapsed: 706 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 710/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 325694767 t fired, 33391665 attempts, .

Time elapsed: 711 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 715/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 327992268 t fired, 33626832 attempts, .

Time elapsed: 716 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 720/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 330289992 t fired, 33862150 attempts, .

Time elapsed: 721 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 725/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 332591516 t fired, 34098134 attempts, .

Time elapsed: 726 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 730/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 334892576 t fired, 34334161 attempts, .

Time elapsed: 731 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 735/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 337193733 t fired, 34570318 attempts, .

Time elapsed: 736 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 740/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 339491724 t fired, 34805494 attempts, .

Time elapsed: 741 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 745/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 341790270 t fired, 35041562 attempts, .

Time elapsed: 746 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 750/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 344086259 t fired, 35277055 attempts, .

Time elapsed: 751 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 755/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 346381886 t fired, 35512366 attempts, .

Time elapsed: 756 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 760/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 348676285 t fired, 35747309 attempts, .

Time elapsed: 761 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 765/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 350976161 t fired, 35983095 attempts, .

Time elapsed: 766 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 770/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 353273278 t fired, 36218330 attempts, .

Time elapsed: 771 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 775/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 355573081 t fired, 36453782 attempts, .

Time elapsed: 776 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 780/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 357874241 t fired, 36689734 attempts, .

Time elapsed: 781 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 785/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 360171781 t fired, 36925055 attempts, .

Time elapsed: 786 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 790/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 362468454 t fired, 37160822 attempts, .

Time elapsed: 791 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 795/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 364765941 t fired, 37396374 attempts, .

Time elapsed: 796 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 800/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 367064194 t fired, 37632129 attempts, .

Time elapsed: 801 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 805/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 369364854 t fired, 37867901 attempts, .

Time elapsed: 806 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 810/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 371666392 t fired, 38103601 attempts, .

Time elapsed: 811 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 815/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 373968831 t fired, 38339615 attempts, .

Time elapsed: 816 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 820/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 376265196 t fired, 38574884 attempts, .

Time elapsed: 821 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 825/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 378556999 t fired, 38809627 attempts, .

Time elapsed: 826 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 830/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 380849732 t fired, 39044781 attempts, .

Time elapsed: 831 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 835/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 383145493 t fired, 39279747 attempts, .

Time elapsed: 836 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 840/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 385444523 t fired, 39515577 attempts, .

Time elapsed: 841 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 845/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 387740496 t fired, 39751140 attempts, .

Time elapsed: 846 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 850/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 390036683 t fired, 39986603 attempts, .

Time elapsed: 851 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 855/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 392332989 t fired, 40222191 attempts, .

Time elapsed: 856 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 860/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 394632448 t fired, 40457973 attempts, .

Time elapsed: 861 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 865/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 396936445 t fired, 40694218 attempts, .

Time elapsed: 866 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 870/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 399238887 t fired, 40930163 attempts, .

Time elapsed: 871 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 875/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 401540964 t fired, 41165946 attempts, .

Time elapsed: 876 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 880/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 403839019 t fired, 41401521 attempts, .

Time elapsed: 881 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 885/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 406132420 t fired, 41636492 attempts, .

Time elapsed: 886 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 890/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 408430619 t fired, 41872319 attempts, .

Time elapsed: 891 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 895/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 410727022 t fired, 42107806 attempts, .

Time elapsed: 896 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 900/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 413029392 t fired, 42344127 attempts, .

Time elapsed: 901 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 905/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 415327827 t fired, 42579520 attempts, .

Time elapsed: 906 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 910/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 417624245 t fired, 42815045 attempts, .

Time elapsed: 911 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 915/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 419919429 t fired, 43050078 attempts, .

Time elapsed: 916 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 920/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 422218879 t fired, 43286097 attempts, .

Time elapsed: 921 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 925/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 424515959 t fired, 43521488 attempts, .

Time elapsed: 926 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 930/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 426814820 t fired, 43757315 attempts, .

Time elapsed: 931 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 935/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 429113173 t fired, 43993070 attempts, .

Time elapsed: 936 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 940/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 431410805 t fired, 44228521 attempts, .

Time elapsed: 941 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 945/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 433706500 t fired, 44463775 attempts, .

Time elapsed: 946 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 950/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 436002390 t fired, 44699282 attempts, .

Time elapsed: 951 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 955/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 438300890 t fired, 44934508 attempts, .

Time elapsed: 956 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 960/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 440602411 t fired, 45170618 attempts, .

Time elapsed: 961 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 965/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 442905027 t fired, 45406932 attempts, .

Time elapsed: 966 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 970/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 445208668 t fired, 45643043 attempts, .

Time elapsed: 971 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 975/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 447512340 t fired, 45879097 attempts, .

Time elapsed: 976 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 980/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 449816315 t fired, 46115320 attempts, .

Time elapsed: 981 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 985/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 452116319 t fired, 46351095 attempts, .

Time elapsed: 986 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 990/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 454412853 t fired, 46586963 attempts, .

Time elapsed: 991 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 995/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 456706234 t fired, 46821696 attempts, .

Time elapsed: 996 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1000/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 459000636 t fired, 47057049 attempts, .

Time elapsed: 1001 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1005/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 461296374 t fired, 47292187 attempts, .

Time elapsed: 1006 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1010/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 463593322 t fired, 47527551 attempts, .

Time elapsed: 1011 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1015/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 465892597 t fired, 47763359 attempts, .

Time elapsed: 1016 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1020/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 468193761 t fired, 47999313 attempts, .

Time elapsed: 1021 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1025/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 470490151 t fired, 48234455 attempts, .

Time elapsed: 1026 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1030/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 472785883 t fired, 48470101 attempts, .

Time elapsed: 1031 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1035/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 475080793 t fired, 48705490 attempts, .

Time elapsed: 1036 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1040/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 477375696 t fired, 48940868 attempts, .

Time elapsed: 1041 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1045/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 479670052 t fired, 49176213 attempts, .

Time elapsed: 1046 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1050/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 481969274 t fired, 49412248 attempts, .

Time elapsed: 1051 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1055/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 484264862 t fired, 49647529 attempts, .

Time elapsed: 1056 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1060/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 486560852 t fired, 49883186 attempts, .

Time elapsed: 1061 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1065/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 488861310 t fired, 50119387 attempts, .

Time elapsed: 1066 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1070/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 491161206 t fired, 50354854 attempts, .

Time elapsed: 1071 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1075/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 493461926 t fired, 50590237 attempts, .

Time elapsed: 1076 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1080/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 495765127 t fired, 50826444 attempts, .

Time elapsed: 1081 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1085/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 498067863 t fired, 51062641 attempts, .

Time elapsed: 1086 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1090/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 500367803 t fired, 51298361 attempts, .

Time elapsed: 1091 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1095/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 502668201 t fired, 51534325 attempts, .

Time elapsed: 1096 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1100/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 504965137 t fired, 51769563 attempts, .

Time elapsed: 1101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1105/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 507262232 t fired, 52005041 attempts, .

Time elapsed: 1106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1110/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 509558309 t fired, 52240179 attempts, .

Time elapsed: 1111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1115/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 511852862 t fired, 52475599 attempts, .

Time elapsed: 1116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1120/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 514148526 t fired, 52711155 attempts, .

Time elapsed: 1121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1125/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 516443746 t fired, 52946554 attempts, .

Time elapsed: 1126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1130/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 518736901 t fired, 53181266 attempts, .

Time elapsed: 1131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1135/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 521032697 t fired, 53416750 attempts, .

Time elapsed: 1136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1140/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 523330190 t fired, 53652514 attempts, .

Time elapsed: 1141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1145/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 525628035 t fired, 53888186 attempts, .

Time elapsed: 1146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1150/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 527924659 t fired, 54123796 attempts, .

Time elapsed: 1151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1155/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 530222884 t fired, 54359648 attempts, .

Time elapsed: 1156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1160/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 532518861 t fired, 54595022 attempts, .

Time elapsed: 1161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1165/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 534816491 t fired, 54830802 attempts, .

Time elapsed: 1166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1170/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 537107251 t fired, 55065564 attempts, .

Time elapsed: 1171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1175/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 539409548 t fired, 55301492 attempts, .

Time elapsed: 1176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1180/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 541712838 t fired, 55537573 attempts, .

Time elapsed: 1181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1185/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 544016584 t fired, 55773735 attempts, .

Time elapsed: 1186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1190/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 546318188 t fired, 56009324 attempts, .

Time elapsed: 1191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1195/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 548621174 t fired, 56245181 attempts, .

Time elapsed: 1196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1200/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 550924631 t fired, 56481188 attempts, .

Time elapsed: 1201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1205/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 553228412 t fired, 56717486 attempts, .

Time elapsed: 1206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1210/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 555532979 t fired, 56953989 attempts, .

Time elapsed: 1211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1215/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 557834951 t fired, 57190053 attempts, .

Time elapsed: 1216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1220/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 560134294 t fired, 57425748 attempts, .

Time elapsed: 1221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1225/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 562432086 t fired, 57661451 attempts, .

Time elapsed: 1226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1230/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 564729987 t fired, 57897063 attempts, .

Time elapsed: 1231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1235/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 567024206 t fired, 58132394 attempts, .

Time elapsed: 1236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1240/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 569323302 t fired, 58367833 attempts, .

Time elapsed: 1241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1245/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 571619182 t fired, 58603171 attempts, .

Time elapsed: 1246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1250/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 573920837 t fired, 58838973 attempts, .

Time elapsed: 1251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1255/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 576219180 t fired, 59074681 attempts, .

Time elapsed: 1256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1260/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 578518529 t fired, 59310549 attempts, .

Time elapsed: 1261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1265/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 580814340 t fired, 59545954 attempts, .

Time elapsed: 1266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1270/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 583112118 t fired, 59781654 attempts, .

Time elapsed: 1271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1275/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 585410396 t fired, 60017058 attempts, .

Time elapsed: 1276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1280/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 587711180 t fired, 60252747 attempts, .

Time elapsed: 1281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1285/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 590012467 t fired, 60488564 attempts, .

Time elapsed: 1286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1290/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 592312147 t fired, 60724290 attempts, .

Time elapsed: 1291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1295/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 594608771 t fired, 60959739 attempts, .

Time elapsed: 1296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1300/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 596905909 t fired, 61194969 attempts, .

Time elapsed: 1301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1305/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 599204277 t fired, 61430678 attempts, .

Time elapsed: 1306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1310/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 601502055 t fired, 61666173 attempts, .

Time elapsed: 1311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1315/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 603797327 t fired, 61901155 attempts, .

Time elapsed: 1316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1320/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 606095316 t fired, 62137082 attempts, .

Time elapsed: 1321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1325/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 608393382 t fired, 62372713 attempts, .

Time elapsed: 1326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1330/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 610694529 t fired, 62608695 attempts, .

Time elapsed: 1331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1335/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 612992361 t fired, 62844292 attempts, .

Time elapsed: 1336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1340/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 615291317 t fired, 63080395 attempts, .

Time elapsed: 1341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1345/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 617589693 t fired, 63315947 attempts, .

Time elapsed: 1346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1350/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 619888940 t fired, 63551383 attempts, .

Time elapsed: 1351 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1355/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 622187559 t fired, 63786895 attempts, .

Time elapsed: 1356 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1360/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 624485756 t fired, 64022695 attempts, .

Time elapsed: 1361 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1365/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 626783425 t fired, 64257968 attempts, .

Time elapsed: 1366 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1370/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 629083079 t fired, 64493885 attempts, .

Time elapsed: 1371 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1375/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 631383833 t fired, 64730131 attempts, .

Time elapsed: 1376 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1380/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 633687669 t fired, 64967064 attempts, .

Time elapsed: 1381 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1385/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 635989383 t fired, 65203064 attempts, .

Time elapsed: 1386 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1390/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 638290321 t fired, 65438969 attempts, .

Time elapsed: 1391 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1395/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 640591468 t fired, 65674854 attempts, .

Time elapsed: 1396 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1400/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 642891446 t fired, 65910047 attempts, .

Time elapsed: 1401 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1405/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 645192127 t fired, 66145682 attempts, .

Time elapsed: 1406 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1410/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 647490036 t fired, 66381551 attempts, .

Time elapsed: 1411 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1415/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 649791206 t fired, 66617638 attempts, .

Time elapsed: 1416 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1420/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 652090492 t fired, 66853190 attempts, .

Time elapsed: 1421 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1425/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 654387455 t fired, 67088968 attempts, .

Time elapsed: 1426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1430/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 656684724 t fired, 67324345 attempts, .

Time elapsed: 1431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1435/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 658985132 t fired, 67560351 attempts, .

Time elapsed: 1436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1440/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 661288199 t fired, 67796594 attempts, .

Time elapsed: 1441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1445/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 663591327 t fired, 68032589 attempts, .

Time elapsed: 1446 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1450/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 665895396 t fired, 68268622 attempts, .

Time elapsed: 1451 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1455/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 668198477 t fired, 68504759 attempts, .

Time elapsed: 1456 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1460/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 670500405 t fired, 68740914 attempts, .

Time elapsed: 1461 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1465/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 672802518 t fired, 68976730 attempts, .

Time elapsed: 1466 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1470/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 675105826 t fired, 69212865 attempts, .

Time elapsed: 1471 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1475/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 677406840 t fired, 69449066 attempts, .

Time elapsed: 1476 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1480/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 679707501 t fired, 69684786 attempts, .

Time elapsed: 1481 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1485/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 682007897 t fired, 69920349 attempts, .

Time elapsed: 1486 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1490/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 684307141 t fired, 70156410 attempts, .

Time elapsed: 1491 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1495/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 686605614 t fired, 70391823 attempts, .

Time elapsed: 1496 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1500/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 688904193 t fired, 70627423 attempts, .

Time elapsed: 1501 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1505/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 691202640 t fired, 70863579 attempts, .

Time elapsed: 1506 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1510/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 693501191 t fired, 71099329 attempts, .

Time elapsed: 1511 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1515/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 695802425 t fired, 71335030 attempts, .

Time elapsed: 1516 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1520/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 698104990 t fired, 71571300 attempts, .

Time elapsed: 1521 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1525/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 700408404 t fired, 71807395 attempts, .

Time elapsed: 1526 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1530/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 702709160 t fired, 72043739 attempts, .

Time elapsed: 1531 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1535/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 705009544 t fired, 72279480 attempts, .

Time elapsed: 1536 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1540/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 707310621 t fired, 72515479 attempts, .

Time elapsed: 1541 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1545/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 709611178 t fired, 72751185 attempts, .

Time elapsed: 1546 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1550/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 711912031 t fired, 72987205 attempts, .

Time elapsed: 1551 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1555/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 714215174 t fired, 73223258 attempts, .

Time elapsed: 1556 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1560/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 716515899 t fired, 73458893 attempts, .

Time elapsed: 1561 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1565/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 718812299 t fired, 73694356 attempts, .

Time elapsed: 1566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1570/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 721109608 t fired, 73930030 attempts, .

Time elapsed: 1571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1575/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 723406042 t fired, 74165515 attempts, .

Time elapsed: 1576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1580/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 725704361 t fired, 74400945 attempts, .

Time elapsed: 1581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1585/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 728003153 t fired, 74636846 attempts, .

Time elapsed: 1586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1590/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 730306474 t fired, 74872629 attempts, .

Time elapsed: 1591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1595/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 732605236 t fired, 75108195 attempts, .

Time elapsed: 1596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1600/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 734903401 t fired, 75343380 attempts, .

Time elapsed: 1601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1605/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 737178848 t fired, 75577196 attempts, .

Time elapsed: 1606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1610/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 739478434 t fired, 75812918 attempts, .

Time elapsed: 1611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1615/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 741781291 t fired, 76048929 attempts, .

Time elapsed: 1616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1620/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 744083290 t fired, 76285490 attempts, .

Time elapsed: 1621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1625/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 746381221 t fired, 76520813 attempts, .

Time elapsed: 1626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1630/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 748679234 t fired, 76756410 attempts, .

Time elapsed: 1631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1635/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 750978319 t fired, 76992349 attempts, .

Time elapsed: 1636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1640/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 753275784 t fired, 77227825 attempts, .

Time elapsed: 1641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1645/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 755574992 t fired, 77463214 attempts, .

Time elapsed: 1646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1650/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 757876493 t fired, 77699100 attempts, .

Time elapsed: 1651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1655/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 760177334 t fired, 77934911 attempts, .

Time elapsed: 1656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1660/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 762476436 t fired, 78170744 attempts, .

Time elapsed: 1661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1665/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 764772841 t fired, 78406001 attempts, .

Time elapsed: 1666 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1670/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 767070529 t fired, 78641453 attempts, .

Time elapsed: 1671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1675/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 769368076 t fired, 78877019 attempts, .

Time elapsed: 1676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1680/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 771667150 t fired, 79112706 attempts, .

Time elapsed: 1681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1685/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 773968780 t fired, 79348993 attempts, .

Time elapsed: 1686 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1690/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 776272912 t fired, 79585130 attempts, .

Time elapsed: 1691 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1695/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 778575660 t fired, 79821111 attempts, .

Time elapsed: 1696 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1700/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 780879822 t fired, 80056804 attempts, .

Time elapsed: 1701 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1705/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 783182655 t fired, 80292870 attempts, .

Time elapsed: 1706 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1710/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 785484683 t fired, 80528801 attempts, .

Time elapsed: 1711 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1715/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 787783469 t fired, 80764683 attempts, .

Time elapsed: 1716 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1720/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 790080669 t fired, 80999970 attempts, .

Time elapsed: 1721 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1725/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 792379871 t fired, 81236113 attempts, .

Time elapsed: 1726 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1730/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 794677974 t fired, 81471822 attempts, .

Time elapsed: 1731 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1735/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 796978240 t fired, 81707456 attempts, .

Time elapsed: 1736 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1740/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 799281733 t fired, 81943548 attempts, .

Time elapsed: 1741 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1745/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 801585090 t fired, 82179774 attempts, .

Time elapsed: 1746 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1750/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 803891223 t fired, 82416150 attempts, .

Time elapsed: 1751 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1755/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 806193844 t fired, 82652181 attempts, .

Time elapsed: 1756 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1760/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 808496630 t fired, 82888097 attempts, .

Time elapsed: 1761 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1765/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 810798372 t fired, 83123816 attempts, .

Time elapsed: 1766 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1770/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 813102349 t fired, 83359945 attempts, .

Time elapsed: 1771 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1775/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 815404611 t fired, 83596587 attempts, .

Time elapsed: 1776 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1780/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 817708732 t fired, 83832737 attempts, .

Time elapsed: 1781 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1785/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 820013448 t fired, 84069278 attempts, .

Time elapsed: 1786 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1790/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 822316254 t fired, 84305748 attempts, .

Time elapsed: 1791 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1795/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 824617774 t fired, 84541747 attempts, .

Time elapsed: 1796 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1800/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 826921568 t fired, 84778062 attempts, .

Time elapsed: 1801 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1805/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 829224481 t fired, 85014340 attempts, .

Time elapsed: 1806 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1810/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 831526267 t fired, 85250501 attempts, .

Time elapsed: 1811 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1815/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 833829295 t fired, 85486574 attempts, .

Time elapsed: 1816 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1820/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 836133962 t fired, 85723070 attempts, .

Time elapsed: 1821 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1825/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 838434744 t fired, 85958894 attempts, .

Time elapsed: 1826 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1830/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 840736491 t fired, 86194581 attempts, .

Time elapsed: 1831 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1835/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 843037675 t fired, 86430483 attempts, .

Time elapsed: 1836 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1840/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 845337602 t fired, 86666187 attempts, .

Time elapsed: 1841 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1845/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 847638132 t fired, 86901737 attempts, .

Time elapsed: 1846 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1850/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 849939679 t fired, 87137636 attempts, .

Time elapsed: 1851 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1855/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 852242579 t fired, 87373816 attempts, .

Time elapsed: 1856 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1860/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 854544996 t fired, 87609803 attempts, .

Time elapsed: 1861 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1865/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 856850064 t fired, 87845939 attempts, .

Time elapsed: 1866 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1870/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 859151894 t fired, 88081539 attempts, .

Time elapsed: 1871 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1875/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 861451720 t fired, 88317385 attempts, .

Time elapsed: 1876 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1880/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 863754849 t fired, 88553696 attempts, .

Time elapsed: 1881 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1885/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 866059188 t fired, 88789997 attempts, .

Time elapsed: 1886 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1890/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 868362995 t fired, 89026430 attempts, .

Time elapsed: 1891 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1895/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 870665628 t fired, 89262213 attempts, .

Time elapsed: 1896 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1900/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 872968512 t fired, 89498773 attempts, .

Time elapsed: 1901 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1905/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 875268636 t fired, 89734556 attempts, .

Time elapsed: 1906 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1910/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 877567570 t fired, 89970554 attempts, .

Time elapsed: 1911 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1915/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 879868077 t fired, 90206391 attempts, .

Time elapsed: 1916 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1920/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 882171221 t fired, 90442297 attempts, .

Time elapsed: 1921 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1925/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 884474673 t fired, 90678712 attempts, .

Time elapsed: 1926 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1930/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 886777868 t fired, 90914737 attempts, .

Time elapsed: 1931 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1935/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 889080777 t fired, 91151195 attempts, .

Time elapsed: 1936 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1940/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 891383897 t fired, 91387610 attempts, .

Time elapsed: 1941 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1945/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 893685684 t fired, 91623698 attempts, .

Time elapsed: 1946 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1950/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 895986660 t fired, 91859786 attempts, .

Time elapsed: 1951 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1955/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 898286906 t fired, 92095752 attempts, .

Time elapsed: 1956 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1960/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 900588697 t fired, 92331740 attempts, .

Time elapsed: 1961 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1965/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 902889785 t fired, 92567376 attempts, .

Time elapsed: 1966 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1970/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 905191944 t fired, 92803523 attempts, .

Time elapsed: 1971 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1975/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 907495942 t fired, 93039990 attempts, .

Time elapsed: 1976 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1980/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 909797511 t fired, 93275923 attempts, .

Time elapsed: 1981 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1985/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 912100810 t fired, 93511958 attempts, .

Time elapsed: 1986 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1990/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 914404948 t fired, 93748200 attempts, .

Time elapsed: 1991 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 1995/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 916708680 t fired, 93984529 attempts, .

Time elapsed: 1996 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2000/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 919009892 t fired, 94220108 attempts, .

Time elapsed: 2001 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2005/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 921314700 t fired, 94456324 attempts, .

Time elapsed: 2006 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2010/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 923613153 t fired, 94692002 attempts, .

Time elapsed: 2011 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2015/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 925913675 t fired, 94927801 attempts, .

Time elapsed: 2016 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2020/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 928216344 t fired, 95164032 attempts, .

Time elapsed: 2021 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2025/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 930517397 t fired, 95399781 attempts, .

Time elapsed: 2026 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2030/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 932817869 t fired, 95635601 attempts, .

Time elapsed: 2031 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2035/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 935118991 t fired, 95871565 attempts, .

Time elapsed: 2036 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2040/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 937422563 t fired, 96107770 attempts, .

Time elapsed: 2041 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2045/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 939723865 t fired, 96344007 attempts, .

Time elapsed: 2046 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2050/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 942025317 t fired, 96580168 attempts, .

Time elapsed: 2051 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2055/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 944329126 t fired, 96816738 attempts, .

Time elapsed: 2056 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2060/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 946633152 t fired, 97052959 attempts, .

Time elapsed: 2061 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2065/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 948936133 t fired, 97289072 attempts, .

Time elapsed: 2066 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2070/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 951236448 t fired, 97524571 attempts, .

Time elapsed: 2071 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2075/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 953536016 t fired, 97760278 attempts, .

Time elapsed: 2076 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2080/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 955836492 t fired, 97995966 attempts, .

Time elapsed: 2081 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2085/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 958133278 t fired, 98231282 attempts, .

Time elapsed: 2086 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2090/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 960432659 t fired, 98467027 attempts, .

Time elapsed: 2091 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2095/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 962732602 t fired, 98702768 attempts, .

Time elapsed: 2096 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2100/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 965032514 t fired, 98938617 attempts, .

Time elapsed: 2101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2105/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 967333543 t fired, 99174417 attempts, .

Time elapsed: 2106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2110/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 969631550 t fired, 99410224 attempts, .

Time elapsed: 2111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2115/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 971925462 t fired, 99645319 attempts, .

Time elapsed: 2116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2120/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 974224253 t fired, 99881027 attempts, .

Time elapsed: 2121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2125/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 976520091 t fired, 100116761 attempts, .

Time elapsed: 2126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2130/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 978821103 t fired, 100352774 attempts, .

Time elapsed: 2131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2135/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 981124885 t fired, 100588978 attempts, .

Time elapsed: 2136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2140/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 983420769 t fired, 100824263 attempts, .

Time elapsed: 2141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2145/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 985715750 t fired, 101059464 attempts, .

Time elapsed: 2146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2150/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 988011738 t fired, 101294787 attempts, .

Time elapsed: 2151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2155/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 990307456 t fired, 101530239 attempts, .

Time elapsed: 2156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2160/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 992602639 t fired, 101765290 attempts, .

Time elapsed: 2161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2165/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 994897018 t fired, 102000265 attempts, .

Time elapsed: 2166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2170/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 997192066 t fired, 102235424 attempts, .

Time elapsed: 2171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2175/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 999486752 t fired, 102470886 attempts, .

Time elapsed: 2176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2180/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1001783436 t fired, 102706541 attempts, .

Time elapsed: 2181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2185/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1004081415 t fired, 102942156 attempts, .

Time elapsed: 2186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2190/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1006382147 t fired, 103177997 attempts, .

Time elapsed: 2191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2195/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1008679721 t fired, 103413784 attempts, .

Time elapsed: 2196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2200/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1010979532 t fired, 103649519 attempts, .

Time elapsed: 2201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2205/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1013278925 t fired, 103885200 attempts, .

Time elapsed: 2206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2210/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1015583498 t fired, 104122127 attempts, .

Time elapsed: 2211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2215/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1017882054 t fired, 104357195 attempts, .

Time elapsed: 2216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2220/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1020182301 t fired, 104593648 attempts, .

Time elapsed: 2221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2225/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1022478449 t fired, 104828799 attempts, .

Time elapsed: 2226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2230/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1024779106 t fired, 105064764 attempts, .

Time elapsed: 2231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2235/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1027075113 t fired, 105299865 attempts, .

Time elapsed: 2236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2240/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1029370881 t fired, 105535691 attempts, .

Time elapsed: 2241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2245/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1031663839 t fired, 105770634 attempts, .

Time elapsed: 2246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2250/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1033955492 t fired, 106005438 attempts, .

Time elapsed: 2251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2255/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1036248922 t fired, 106240847 attempts, .

Time elapsed: 2256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2260/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1038542740 t fired, 106476017 attempts, .

Time elapsed: 2261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2265/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1040838305 t fired, 106711259 attempts, .

Time elapsed: 2266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2270/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1043131444 t fired, 106946183 attempts, .

Time elapsed: 2271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2275/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1045424215 t fired, 107181054 attempts, .

Time elapsed: 2276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2280/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1047717617 t fired, 107416313 attempts, .

Time elapsed: 2281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2285/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1050012103 t fired, 107651999 attempts, .

Time elapsed: 2286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2290/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1052307362 t fired, 107887367 attempts, .

Time elapsed: 2291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2295/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1054603751 t fired, 108122793 attempts, .

Time elapsed: 2296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2300/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1056901736 t fired, 108358414 attempts, .

Time elapsed: 2301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2305/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1059202759 t fired, 108594497 attempts, .

Time elapsed: 2306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2310/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1061503696 t fired, 108830454 attempts, .

Time elapsed: 2311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2315/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1063800766 t fired, 109065609 attempts, .

Time elapsed: 2316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2320/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1066099162 t fired, 109301549 attempts, .

Time elapsed: 2321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2325/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1068396564 t fired, 109537197 attempts, .

Time elapsed: 2326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2330/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1070695640 t fired, 109773034 attempts, .

Time elapsed: 2331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2335/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1072994610 t fired, 110008891 attempts, .

Time elapsed: 2336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2340/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1075288869 t fired, 110244591 attempts, .

Time elapsed: 2341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2345/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1077583378 t fired, 110480056 attempts, .

Time elapsed: 2346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2350/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1079876181 t fired, 110714837 attempts, .

Time elapsed: 2351 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2355/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1082170025 t fired, 110950090 attempts, .

Time elapsed: 2356 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2360/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1084432764 t fired, 111181784 attempts, .

Time elapsed: 2361 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2365/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1086691496 t fired, 111413359 attempts, .

Time elapsed: 2366 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2370/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1088924044 t fired, 111642525 attempts, .

Time elapsed: 2371 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2375/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1091148019 t fired, 111870268 attempts, .

Time elapsed: 2376 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2380/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1093361306 t fired, 112097465 attempts, .

Time elapsed: 2381 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2385/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1095591377 t fired, 112325843 attempts, .

Time elapsed: 2386 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2390/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1097824355 t fired, 112554790 attempts, .

Time elapsed: 2391 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2395/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1100095654 t fired, 112787990 attempts, .

Time elapsed: 2396 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2400/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1102379759 t fired, 113022364 attempts, .

Time elapsed: 2401 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2405/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1104667952 t fired, 113257031 attempts, .

Time elapsed: 2406 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2410/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1106962396 t fired, 113492545 attempts, .

Time elapsed: 2411 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2415/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1109257918 t fired, 113727799 attempts, .

Time elapsed: 2416 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2420/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1111539487 t fired, 113961544 attempts, .

Time elapsed: 2421 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2425/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1113818135 t fired, 114195569 attempts, .

Time elapsed: 2426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2430/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1116103962 t fired, 114429632 attempts, .

Time elapsed: 2431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2435/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1118396291 t fired, 114664034 attempts, .

Time elapsed: 2436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2440/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1120684555 t fired, 114898389 attempts, .

Time elapsed: 2441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2445/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1122971475 t fired, 115133075 attempts, .

Time elapsed: 2446 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2450/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1125264863 t fired, 115368152 attempts, .

Time elapsed: 2451 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2455/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1127559287 t fired, 115603377 attempts, .

Time elapsed: 2456 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2460/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1129855737 t fired, 115838578 attempts, .

Time elapsed: 2461 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2465/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1132151871 t fired, 116074306 attempts, .

Time elapsed: 2466 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2470/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1134443457 t fired, 116309101 attempts, .

Time elapsed: 2471 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2475/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1136727821 t fired, 116542942 attempts, .

Time elapsed: 2476 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2480/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1139007786 t fired, 116776767 attempts, .

Time elapsed: 2481 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2485/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1141284096 t fired, 117010357 attempts, .

Time elapsed: 2486 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2490/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1143561381 t fired, 117243688 attempts, .

Time elapsed: 2491 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2495/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1145814778 t fired, 117474264 attempts, .

Time elapsed: 2496 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2500/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1147999096 t fired, 117698226 attempts, .

Time elapsed: 2501 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2505/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1150185817 t fired, 117922555 attempts, .

Time elapsed: 2506 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2510/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1152369565 t fired, 118146337 attempts, .

Time elapsed: 2511 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2515/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1154553303 t fired, 118370034 attempts, .

Time elapsed: 2516 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2520/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1156757555 t fired, 118596312 attempts, .

Time elapsed: 2521 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2525/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1158962973 t fired, 118822357 attempts, .

Time elapsed: 2526 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2530/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1161168814 t fired, 119048721 attempts, .

Time elapsed: 2531 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2535/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1163379360 t fired, 119275372 attempts, .

Time elapsed: 2536 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2540/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1165619827 t fired, 119504939 attempts, .

Time elapsed: 2541 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2545/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1167865403 t fired, 119735115 attempts, .

Time elapsed: 2546 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2550/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1170097474 t fired, 119963695 attempts, .

Time elapsed: 2551 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2555/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1172324724 t fired, 120192291 attempts, .

Time elapsed: 2556 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2560/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1174584427 t fired, 120423896 attempts, .

Time elapsed: 2561 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2565/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1176811376 t fired, 120652085 attempts, .

Time elapsed: 2566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2570/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1179043583 t fired, 120881272 attempts, .

Time elapsed: 2571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2575/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1181259389 t fired, 121108389 attempts, .

Time elapsed: 2576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2580/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1183486976 t fired, 121336698 attempts, .

Time elapsed: 2581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2585/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1185737528 t fired, 121567048 attempts, .

Time elapsed: 2586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2590/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1187931409 t fired, 121791723 attempts, .

Time elapsed: 2591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2595/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1190180905 t fired, 122022683 attempts, .

Time elapsed: 2596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2600/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1192455894 t fired, 122255809 attempts, .

Time elapsed: 2601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2605/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1194716730 t fired, 122487881 attempts, .

Time elapsed: 2606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2610/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1196988718 t fired, 122720842 attempts, .

Time elapsed: 2611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2615/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1199265206 t fired, 122954576 attempts, .

Time elapsed: 2616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2620/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1201537020 t fired, 123187480 attempts, .

Time elapsed: 2621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2625/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1203807430 t fired, 123420145 attempts, .

Time elapsed: 2626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2630/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1206080380 t fired, 123652820 attempts, .

Time elapsed: 2631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2635/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1208353280 t fired, 123885852 attempts, .

Time elapsed: 2636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2640/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1210629535 t fired, 124119261 attempts, .

Time elapsed: 2641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2645/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1212898289 t fired, 124351900 attempts, .

Time elapsed: 2646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2650/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1215170689 t fired, 124584541 attempts, .

Time elapsed: 2651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2655/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1217447841 t fired, 124818093 attempts, .

Time elapsed: 2656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2660/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1219726202 t fired, 125051338 attempts, .

Time elapsed: 2661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2665/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1221990689 t fired, 125284007 attempts, .

Time elapsed: 2666 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2670/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1224260727 t fired, 125516444 attempts, .

Time elapsed: 2671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2675/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1226537296 t fired, 125749518 attempts, .

Time elapsed: 2676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2680/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1228814556 t fired, 125982744 attempts, .

Time elapsed: 2681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2685/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1231075247 t fired, 126214641 attempts, .

Time elapsed: 2686 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2690/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1233347911 t fired, 126447790 attempts, .

Time elapsed: 2691 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2695/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1235626454 t fired, 126681628 attempts, .

Time elapsed: 2696 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2700/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1237907215 t fired, 126915599 attempts, .

Time elapsed: 2701 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2705/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1240169668 t fired, 127147564 attempts, .

Time elapsed: 2706 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2710/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1242428391 t fired, 127379257 attempts, .

Time elapsed: 2711 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2715/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1244687266 t fired, 127610855 attempts, .

Time elapsed: 2716 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2720/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1246943757 t fired, 127841954 attempts, .

Time elapsed: 2721 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2725/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1249201331 t fired, 128073438 attempts, .

Time elapsed: 2726 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2730/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1251458785 t fired, 128305142 attempts, .

Time elapsed: 2731 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2735/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1253716750 t fired, 128536680 attempts, .

Time elapsed: 2736 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2740/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1255973244 t fired, 128768064 attempts, .

Time elapsed: 2741 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2745/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1258235086 t fired, 129000253 attempts, .

Time elapsed: 2746 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2750/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1260491838 t fired, 129231879 attempts, .

Time elapsed: 2751 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2755/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1262747373 t fired, 129462671 attempts, .

Time elapsed: 2756 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2760/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1265005209 t fired, 129694531 attempts, .

Time elapsed: 2761 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2765/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1267263428 t fired, 129925983 attempts, .

Time elapsed: 2766 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2770/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1269520061 t fired, 130157318 attempts, .

Time elapsed: 2771 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2775/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1271779336 t fired, 130388747 attempts, .

Time elapsed: 2776 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2780/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1274036477 t fired, 130619938 attempts, .

Time elapsed: 2781 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2785/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1276298386 t fired, 130851901 attempts, .

Time elapsed: 2786 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2790/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1278554443 t fired, 131083714 attempts, .

Time elapsed: 2791 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2795/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1280809319 t fired, 131314721 attempts, .

Time elapsed: 2796 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2800/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1283064833 t fired, 131545808 attempts, .

Time elapsed: 2801 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2805/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1285317926 t fired, 131776366 attempts, .

Time elapsed: 2806 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2810/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1287572114 t fired, 132007535 attempts, .

Time elapsed: 2811 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU
DoubleExponent-PT-004-CTLFireability-11: CONJ true CONJ
DoubleExponent-PT-004-CTLFireability-14: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-004-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-004-CTLFireability-13: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 EF FNDP 2815/3599 0/5 DoubleExponent-PT-004-CTLFireability-13 1289830117 t fired, 132238823 attempts, .

Time elapsed: 2816 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-004-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-01: F false state space / EG
DoubleExponent-PT-004-CTLFireability-04: CTL true CTL model checker
DoubleExponent-PT-004-CTLFireability-07: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-08: CTL false CTL model checker
DoubleExponent-PT-004-CTLFireability-10: EU true state space /EU

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleExponent-PT-004"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DoubleExponent-PT-004, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819414500466"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleExponent-PT-004.tgz
mv DoubleExponent-PT-004 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;