About the Execution of LoLa+red for Diffusion2D-PT-D05N050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 13653.207 | 251397.00 | 246238.00 | 1357.40 | ?TTF?T?FFT?FTTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r135-smll-167819413400058.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Diffusion2D-PT-D05N050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819413400058
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 6.8K Feb 26 04:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Feb 26 04:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Feb 26 04:21 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 04:21 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Feb 25 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 04:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Feb 26 04:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Feb 26 04:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 73K Feb 26 04:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:57 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:57 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 55K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-00
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-01
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-02
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-03
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-04
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-05
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-06
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-07
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-08
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-09
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-10
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-11
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-12
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-13
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-14
FORMULA_NAME Diffusion2D-PT-D05N050-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678272498515
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Diffusion2D-PT-D05N050
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 10:48:20] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 10:48:20] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 10:48:20] [INFO ] Load time of PNML (sax parser for PT used): 61 ms
[2023-03-08 10:48:20] [INFO ] Transformed 25 places.
[2023-03-08 10:48:20] [INFO ] Transformed 144 transitions.
[2023-03-08 10:48:20] [INFO ] Parsed PT model containing 25 places and 144 transitions and 288 arcs in 154 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
Initial state reduction rules removed 2 formulas.
FORMULA Diffusion2D-PT-D05N050-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Diffusion2D-PT-D05N050-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 24 out of 25 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 15 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
// Phase 1: matrix 144 rows 25 cols
[2023-03-08 10:48:21] [INFO ] Computed 1 place invariants in 11 ms
[2023-03-08 10:48:21] [INFO ] Implicit Places using invariants in 198 ms returned []
[2023-03-08 10:48:21] [INFO ] Invariant cache hit.
[2023-03-08 10:48:21] [INFO ] Implicit Places using invariants and state equation in 118 ms returned []
Implicit Place search using SMT with State Equation took 357 ms to find 0 implicit places.
[2023-03-08 10:48:21] [INFO ] Invariant cache hit.
[2023-03-08 10:48:21] [INFO ] Dead Transitions using invariants and state equation in 192 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 573 ms. Remains : 25/25 places, 144/144 transitions.
Support contains 24 out of 25 places after structural reductions.
[2023-03-08 10:48:21] [INFO ] Flatten gal took : 46 ms
[2023-03-08 10:48:21] [INFO ] Flatten gal took : 15 ms
[2023-03-08 10:48:21] [INFO ] Input system was already deterministic with 144 transitions.
Incomplete random walk after 10017 steps, including 2 resets, run finished after 108 ms. (steps per millisecond=92 ) properties (out of 34) seen :28
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 6) seen :4
Finished Best-First random walk after 7922 steps, including 2 resets, run visited all 2 properties in 14 ms. (steps per millisecond=565 )
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 11 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 11 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 3 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 8 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 8 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Graph (trivial) has 114 edges and 25 vertex of which 23 / 25 are part of one of the 1 SCC in 4 ms
Free SCC test removed 22 places
Ensure Unique test removed 137 transitions
Reduce isomorphic transitions removed 137 transitions.
Applied a total of 1 rules in 11 ms. Remains 3 /25 variables (removed 22) and now considering 7/144 (removed 137) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 3/25 places, 7/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 0 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Graph (trivial) has 118 edges and 25 vertex of which 23 / 25 are part of one of the 1 SCC in 0 ms
Free SCC test removed 22 places
Ensure Unique test removed 139 transitions
Reduce isomorphic transitions removed 139 transitions.
Applied a total of 1 rules in 2 ms. Remains 3 /25 variables (removed 22) and now considering 5/144 (removed 139) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 3/25 places, 5/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 0 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 2 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 8 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 8 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 8 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 6 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 9 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 2 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 6 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 2 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 6 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 6 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Graph (trivial) has 134 edges and 25 vertex of which 24 / 25 are part of one of the 1 SCC in 0 ms
Free SCC test removed 23 places
Ensure Unique test removed 141 transitions
Reduce isomorphic transitions removed 141 transitions.
Applied a total of 1 rules in 2 ms. Remains 2 /25 variables (removed 23) and now considering 3/144 (removed 141) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 2/25 places, 3/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 0 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 3 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 11 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 6 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 5 ms
[2023-03-08 10:48:22] [INFO ] Input system was already deterministic with 144 transitions.
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 6 ms
[2023-03-08 10:48:22] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:48:22] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 10:48:22] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 25 places, 144 transitions and 288 arcs took 1 ms.
Total runtime 1998 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Diffusion2D-PT-D05N050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/370
CTLFireability
FORMULA Diffusion2D-PT-D05N050-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N050-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N050-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N050-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N050-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N050-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N050-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N050-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N050-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N050-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678272749912
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/370/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/370/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/370/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 4 (type EXCL) for 3 Diffusion2D-PT-D05N050-CTLFireability-01
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-01
lola: result : true
lola: markings : 51
lola: fired transitions : 209
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 10 (type EXCL) for 9 Diffusion2D-PT-D05N050-CTLFireability-03
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 10 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-03
lola: result : false
lola: markings : 2515
lola: fired transitions : 7578
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: LAUNCH task # 23 (type EXCL) for 22 Diffusion2D-PT-D05N050-CTLFireability-06
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:714
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/240 3/32 Diffusion2D-PT-D05N050-CTLFireability-06 605803 m, 121160 m/sec, 3426728 t fired, .
Time elapsed: 5 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/240 5/32 Diffusion2D-PT-D05N050-CTLFireability-06 1186611 m, 116161 m/sec, 6645115 t fired, .
Time elapsed: 10 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/240 8/32 Diffusion2D-PT-D05N050-CTLFireability-06 1748898 m, 112457 m/sec, 9724540 t fired, .
Time elapsed: 15 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 20/240 10/32 Diffusion2D-PT-D05N050-CTLFireability-06 2311867 m, 112593 m/sec, 12809786 t fired, .
Time elapsed: 20 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 25/240 12/32 Diffusion2D-PT-D05N050-CTLFireability-06 2867292 m, 111085 m/sec, 15853820 t fired, .
Time elapsed: 25 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 30/240 15/32 Diffusion2D-PT-D05N050-CTLFireability-06 3417132 m, 109968 m/sec, 18850224 t fired, .
Time elapsed: 30 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 35/240 17/32 Diffusion2D-PT-D05N050-CTLFireability-06 3954587 m, 107491 m/sec, 21741044 t fired, .
Time elapsed: 35 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 40/240 19/32 Diffusion2D-PT-D05N050-CTLFireability-06 4509656 m, 111013 m/sec, 24800881 t fired, .
Time elapsed: 40 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 45/240 21/32 Diffusion2D-PT-D05N050-CTLFireability-06 5052791 m, 108627 m/sec, 27743294 t fired, .
Time elapsed: 45 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 50/240 24/32 Diffusion2D-PT-D05N050-CTLFireability-06 5573891 m, 104220 m/sec, 30533373 t fired, .
Time elapsed: 50 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 55/240 26/32 Diffusion2D-PT-D05N050-CTLFireability-06 6113673 m, 107956 m/sec, 33469351 t fired, .
Time elapsed: 55 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 60/240 28/32 Diffusion2D-PT-D05N050-CTLFireability-06 6644389 m, 106143 m/sec, 36314459 t fired, .
Time elapsed: 60 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 65/240 30/32 Diffusion2D-PT-D05N050-CTLFireability-06 7167375 m, 104597 m/sec, 39114976 t fired, .
Time elapsed: 65 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 70/240 32/32 Diffusion2D-PT-D05N050-CTLFireability-06 7686753 m, 103875 m/sec, 41891346 t fired, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 23 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 52 (type EXCL) for 43 Diffusion2D-PT-D05N050-CTLFireability-14
lola: time limit : 251 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-14
lola: result : true
lola: markings : 3
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 Diffusion2D-PT-D05N050-CTLFireability-13
lola: time limit : 320 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-13
lola: result : true
lola: markings : 11
lola: fired transitions : 26
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 Diffusion2D-PT-D05N050-CTLFireability-10
lola: time limit : 352 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 5/352 5/32 Diffusion2D-PT-D05N050-CTLFireability-10 1073673 m, 214734 m/sec, 4381878 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 10/352 9/32 Diffusion2D-PT-D05N050-CTLFireability-10 2018911 m, 189047 m/sec, 8273781 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 15/352 13/32 Diffusion2D-PT-D05N050-CTLFireability-10 2996779 m, 195573 m/sec, 12294308 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 20/352 17/32 Diffusion2D-PT-D05N050-CTLFireability-10 3965497 m, 193743 m/sec, 16273580 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 25/352 21/32 Diffusion2D-PT-D05N050-CTLFireability-10 4938767 m, 194654 m/sec, 20289390 t fired, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 30/352 25/32 Diffusion2D-PT-D05N050-CTLFireability-10 5886798 m, 189606 m/sec, 24201311 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 35/352 29/32 Diffusion2D-PT-D05N050-CTLFireability-10 6832265 m, 189093 m/sec, 28093385 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 35 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 32 (type EXCL) for 31 Diffusion2D-PT-D05N050-CTLFireability-09
lola: time limit : 387 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-09
lola: result : true
lola: markings : 47
lola: fired transitions : 84
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 Diffusion2D-PT-D05N050-CTLFireability-08
lola: time limit : 435 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-08
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 Diffusion2D-PT-D05N050-CTLFireability-07
lola: time limit : 497 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-07
lola: result : false
lola: markings : 4
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 15 Diffusion2D-PT-D05N050-CTLFireability-05
lola: time limit : 580 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-05
lola: result : true
lola: markings : 66041
lola: fired transitions : 236411
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 Diffusion2D-PT-D05N050-CTLFireability-04
lola: time limit : 871 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/871 2/32 Diffusion2D-PT-D05N050-CTLFireability-04 444836 m, 88967 m/sec, 2524489 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/871 4/32 Diffusion2D-PT-D05N050-CTLFireability-04 899471 m, 90927 m/sec, 5116496 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/871 6/32 Diffusion2D-PT-D05N050-CTLFireability-04 1366207 m, 93347 m/sec, 7737864 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/871 8/32 Diffusion2D-PT-D05N050-CTLFireability-04 1818925 m, 90543 m/sec, 10291331 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/871 10/32 Diffusion2D-PT-D05N050-CTLFireability-04 2274835 m, 91182 m/sec, 12852780 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/871 12/32 Diffusion2D-PT-D05N050-CTLFireability-04 2734913 m, 92015 m/sec, 15449800 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/871 14/32 Diffusion2D-PT-D05N050-CTLFireability-04 3185336 m, 90084 m/sec, 17983641 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/871 16/32 Diffusion2D-PT-D05N050-CTLFireability-04 3640313 m, 90995 m/sec, 20542181 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/871 17/32 Diffusion2D-PT-D05N050-CTLFireability-04 4088050 m, 89547 m/sec, 23045182 t fired, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 50/871 19/32 Diffusion2D-PT-D05N050-CTLFireability-04 4543419 m, 91073 m/sec, 25619995 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 55/871 21/32 Diffusion2D-PT-D05N050-CTLFireability-04 4989915 m, 89299 m/sec, 28126510 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 60/871 23/32 Diffusion2D-PT-D05N050-CTLFireability-04 5435899 m, 89196 m/sec, 30631424 t fired, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 65/871 25/32 Diffusion2D-PT-D05N050-CTLFireability-04 5883397 m, 89499 m/sec, 33164236 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 70/871 27/32 Diffusion2D-PT-D05N050-CTLFireability-04 6330677 m, 89456 m/sec, 35680457 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 75/871 29/32 Diffusion2D-PT-D05N050-CTLFireability-04 6755237 m, 84912 m/sec, 38050305 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 80/871 30/32 Diffusion2D-PT-D05N050-CTLFireability-04 7175595 m, 84071 m/sec, 40382200 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 85/871 32/32 Diffusion2D-PT-D05N050-CTLFireability-04 7625705 m, 90022 m/sec, 42922102 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 13 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 1 (type EXCL) for 0 Diffusion2D-PT-D05N050-CTLFireability-00
lola: time limit : 1131 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/1131 5/32 Diffusion2D-PT-D05N050-CTLFireability-00 1104402 m, 220880 m/sec, 4647544 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/1131 9/32 Diffusion2D-PT-D05N050-CTLFireability-00 2133667 m, 205853 m/sec, 8964686 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/1131 14/32 Diffusion2D-PT-D05N050-CTLFireability-00 3155847 m, 204436 m/sec, 13261264 t fired, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/1131 18/32 Diffusion2D-PT-D05N050-CTLFireability-00 4164088 m, 201648 m/sec, 17480400 t fired, .
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/1131 22/32 Diffusion2D-PT-D05N050-CTLFireability-00 5158440 m, 198870 m/sec, 21656079 t fired, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/1131 26/32 Diffusion2D-PT-D05N050-CTLFireability-00 6151398 m, 198591 m/sec, 25816331 t fired, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/1131 30/32 Diffusion2D-PT-D05N050-CTLFireability-00 7118038 m, 193328 m/sec, 29869345 t fired, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 1 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 38 (type EXCL) for 37 Diffusion2D-PT-D05N050-CTLFireability-12
lola: time limit : 1677 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-12
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 Diffusion2D-PT-D05N050-CTLFireability-02
lola: time limit : 3355 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for Diffusion2D-PT-D05N050-CTLFireability-02
lola: result : true
lola: markings : 1326
lola: fired transitions : 6326
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N050-CTLFireability-00: CTL unknown AGGR
Diffusion2D-PT-D05N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-02: AGEF true tscc_search
Diffusion2D-PT-D05N050-CTLFireability-03: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-04: CTL unknown AGGR
Diffusion2D-PT-D05N050-CTLFireability-05: DISJ true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-06: CTL unknown AGGR
Diffusion2D-PT-D05N050-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-09: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-10: CTL unknown AGGR
Diffusion2D-PT-D05N050-CTLFireability-12: EFEG true state space /EFEG
Diffusion2D-PT-D05N050-CTLFireability-13: CTL true CTL model checker
Diffusion2D-PT-D05N050-CTLFireability-14: DISJ true CTL model checker
Time elapsed: 245 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Diffusion2D-PT-D05N050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Diffusion2D-PT-D05N050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819413400058"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Diffusion2D-PT-D05N050.tgz
mv Diffusion2D-PT-D05N050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;