fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r134-smll-167819412900514
Last Updated
May 14, 2023

About the Execution of LoLA for DoubleLock-PT-p1s2

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
9334.607 3600000.00 14271364.00 165.60 ???FFT???F?????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r134-smll-167819412900514.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DoubleLock-PT-p1s2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r134-smll-167819412900514

=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.8M
-rw-r--r-- 1 mcc users 7.1K Feb 25 14:26 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 14:26 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 14:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 25 14:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 14:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 184K Feb 25 14:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 14:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 14:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 3.4M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p1s2-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678495727538

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p1s2
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DoubleLock-PT-p1s2
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA DoubleLock-PT-p1s2-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p1s2-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p1s2-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleLock-PT-p1s2-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 6875764 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16163804 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 27 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 256 transitions removed,132 places removed
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 32 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 37 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 23 (type EXCL) for 22 DoubleLock-PT-p1s2-CTLFireability-06
lola: time limit : 209 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 53 (type FNDP) for 37 DoubleLock-PT-p1s2-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 37 DoubleLock-PT-p1s2-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 56 (type SRCH) for 37 DoubleLock-PT-p1s2-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: try reading problem file /home/mcc/execution/CTLFireability-54.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 4/209 1/32 DoubleLock-PT-p1s2-CTLFireability-06 75098 m, 15019 m/sec, 150196 t fired, .
53 EF FNDP 3/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1922 t fired, 7 attempts, .
54 EF STEQ 3/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 3/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 1909 m, 381 m/sec, 1946 t fired, .

Time elapsed: 42 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 9/209 2/32 DoubleLock-PT-p1s2-CTLFireability-06 250103 m, 35001 m/sec, 500205 t fired, .
53 EF FNDP 8/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 7710 t fired, 41 attempts, .
54 EF STEQ 8/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 8/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 14316 m, 2481 m/sec, 14353 t fired, .

Time elapsed: 47 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 14/209 3/32 DoubleLock-PT-p1s2-CTLFireability-06 425282 m, 35035 m/sec, 850563 t fired, .
53 EF FNDP 13/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 13378 t fired, 83 attempts, .
54 EF STEQ 13/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 13/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 26697 m, 2476 m/sec, 26734 t fired, .

Time elapsed: 52 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 19/209 4/32 DoubleLock-PT-p1s2-CTLFireability-06 587803 m, 32504 m/sec, 1175605 t fired, .
53 EF FNDP 18/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 18666 t fired, 122 attempts, .
54 EF STEQ 18/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 18/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 39198 m, 2500 m/sec, 39235 t fired, .

Time elapsed: 57 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 24/209 5/32 DoubleLock-PT-p1s2-CTLFireability-06 762532 m, 34945 m/sec, 1525063 t fired, .
53 EF FNDP 23/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 24473 t fired, 160 attempts, .
54 EF STEQ 23/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 23/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 51643 m, 2489 m/sec, 51680 t fired, .

Time elapsed: 62 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 29/209 6/32 DoubleLock-PT-p1s2-CTLFireability-06 935367 m, 34567 m/sec, 1870733 t fired, .
53 EF FNDP 28/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 30020 t fired, 207 attempts, .
54 EF STEQ 28/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 28/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 64090 m, 2489 m/sec, 64127 t fired, .

Time elapsed: 67 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 34/209 7/32 DoubleLock-PT-p1s2-CTLFireability-06 1103642 m, 33655 m/sec, 2207283 t fired, .
53 EF FNDP 33/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 35635 t fired, 247 attempts, .
54 EF STEQ 33/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 33/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 76507 m, 2483 m/sec, 76544 t fired, .

Time elapsed: 72 secs. Pages in use: 8
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 39/209 9/32 DoubleLock-PT-p1s2-CTLFireability-06 1277975 m, 34866 m/sec, 2555949 t fired, .
53 EF FNDP 38/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 41310 t fired, 295 attempts, .
54 EF STEQ 38/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 38/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 88955 m, 2489 m/sec, 88992 t fired, .

Time elapsed: 77 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 44/209 10/32 DoubleLock-PT-p1s2-CTLFireability-06 1453937 m, 35192 m/sec, 2907873 t fired, .
53 EF FNDP 43/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 46566 t fired, 338 attempts, .
54 EF STEQ 43/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 43/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 100523 m, 2313 m/sec, 100560 t fired, .

Time elapsed: 82 secs. Pages in use: 11
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 49/209 11/32 DoubleLock-PT-p1s2-CTLFireability-06 1630539 m, 35320 m/sec, 3261076 t fired, .
53 EF FNDP 48/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 51847 t fired, 378 attempts, .
54 EF STEQ 48/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 48/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 111968 m, 2289 m/sec, 112005 t fired, .

Time elapsed: 87 secs. Pages in use: 12
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 54/209 12/32 DoubleLock-PT-p1s2-CTLFireability-06 1805972 m, 35086 m/sec, 3611943 t fired, .
53 EF FNDP 53/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 57075 t fired, 421 attempts, .
54 EF STEQ 53/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 53/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 123308 m, 2268 m/sec, 123345 t fired, .

Time elapsed: 92 secs. Pages in use: 13
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 59/209 13/32 DoubleLock-PT-p1s2-CTLFireability-06 1980052 m, 34816 m/sec, 3960104 t fired, .
53 EF FNDP 58/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 62810 t fired, 468 attempts, .
54 EF STEQ 58/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 58/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 135927 m, 2523 m/sec, 135964 t fired, .

Time elapsed: 97 secs. Pages in use: 14
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 64/209 14/32 DoubleLock-PT-p1s2-CTLFireability-06 2155225 m, 35034 m/sec, 4310448 t fired, .
53 EF FNDP 63/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 68407 t fired, 518 attempts, .
54 EF STEQ 63/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 63/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 148241 m, 2462 m/sec, 148278 t fired, .

Time elapsed: 102 secs. Pages in use: 15
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 69/209 15/32 DoubleLock-PT-p1s2-CTLFireability-06 2329378 m, 34830 m/sec, 4658755 t fired, .
53 EF FNDP 68/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 74093 t fired, 568 attempts, .
54 EF STEQ 68/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 68/3561 1/5 DoubleLock-PT-p1s2-CTLFireability-11 160529 m, 2457 m/sec, 160566 t fired, .

Time elapsed: 107 secs. Pages in use: 16
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 74/209 16/32 DoubleLock-PT-p1s2-CTLFireability-06 2503419 m, 34808 m/sec, 5006837 t fired, .
53 EF FNDP 73/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 79745 t fired, 619 attempts, .
54 EF STEQ 73/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 73/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 172822 m, 2458 m/sec, 172859 t fired, .

Time elapsed: 112 secs. Pages in use: 18
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 79/209 17/32 DoubleLock-PT-p1s2-CTLFireability-06 2676906 m, 34697 m/sec, 5353811 t fired, .
53 EF FNDP 78/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 85495 t fired, 668 attempts, .
54 EF STEQ 78/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 78/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 185123 m, 2460 m/sec, 185160 t fired, .

Time elapsed: 117 secs. Pages in use: 19
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 84/209 19/32 DoubleLock-PT-p1s2-CTLFireability-06 2851173 m, 34853 m/sec, 5702345 t fired, .
53 EF FNDP 83/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 91183 t fired, 719 attempts, .
54 EF STEQ 83/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 83/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 196922 m, 2359 m/sec, 196959 t fired, .

Time elapsed: 122 secs. Pages in use: 21
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 89/209 20/32 DoubleLock-PT-p1s2-CTLFireability-06 3026020 m, 34969 m/sec, 6052039 t fired, .
53 EF FNDP 88/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 96986 t fired, 768 attempts, .
54 EF STEQ 88/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 88/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 209316 m, 2478 m/sec, 209353 t fired, .

Time elapsed: 127 secs. Pages in use: 22
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 94/209 21/32 DoubleLock-PT-p1s2-CTLFireability-06 3200960 m, 34988 m/sec, 6401920 t fired, .
53 EF FNDP 93/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 102629 t fired, 821 attempts, .
54 EF STEQ 93/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 93/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 221875 m, 2511 m/sec, 221912 t fired, .

Time elapsed: 132 secs. Pages in use: 23
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 99/209 22/32 DoubleLock-PT-p1s2-CTLFireability-06 3375293 m, 34866 m/sec, 6750585 t fired, .
53 EF FNDP 98/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 108362 t fired, 873 attempts, .
54 EF STEQ 98/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 98/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 234195 m, 2464 m/sec, 234232 t fired, .

Time elapsed: 137 secs. Pages in use: 24
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 104/209 23/32 DoubleLock-PT-p1s2-CTLFireability-06 3549155 m, 34772 m/sec, 7098309 t fired, .
53 EF FNDP 103/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 114039 t fired, 928 attempts, .
54 EF STEQ 103/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 103/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 246391 m, 2439 m/sec, 246428 t fired, .

Time elapsed: 142 secs. Pages in use: 25
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 109/209 24/32 DoubleLock-PT-p1s2-CTLFireability-06 3722457 m, 34660 m/sec, 7444913 t fired, .
53 EF FNDP 108/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 119774 t fired, 982 attempts, .
54 EF STEQ 108/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 108/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 258713 m, 2464 m/sec, 258750 t fired, .

Time elapsed: 147 secs. Pages in use: 26
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 114/209 25/32 DoubleLock-PT-p1s2-CTLFireability-06 3895567 m, 34622 m/sec, 7791133 t fired, .
53 EF FNDP 113/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 125444 t fired, 1036 attempts, .
54 EF STEQ 113/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 113/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 271014 m, 2460 m/sec, 271051 t fired, .

Time elapsed: 152 secs. Pages in use: 27
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 119/209 26/32 DoubleLock-PT-p1s2-CTLFireability-06 4069702 m, 34827 m/sec, 8139404 t fired, .
53 EF FNDP 118/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 131079 t fired, 1094 attempts, .
54 EF STEQ 118/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 118/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 283337 m, 2464 m/sec, 283374 t fired, .

Time elapsed: 157 secs. Pages in use: 28
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 124/209 27/32 DoubleLock-PT-p1s2-CTLFireability-06 4244270 m, 34913 m/sec, 8488539 t fired, .
53 EF FNDP 123/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 136788 t fired, 1148 attempts, .
54 EF STEQ 123/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 123/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 295675 m, 2467 m/sec, 295712 t fired, .

Time elapsed: 162 secs. Pages in use: 29
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 129/209 28/32 DoubleLock-PT-p1s2-CTLFireability-06 4417831 m, 34712 m/sec, 8835661 t fired, .
53 EF FNDP 128/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 142510 t fired, 1204 attempts, .
54 EF STEQ 128/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 128/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 307939 m, 2452 m/sec, 307976 t fired, .

Time elapsed: 167 secs. Pages in use: 30
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 134/209 30/32 DoubleLock-PT-p1s2-CTLFireability-06 4591473 m, 34728 m/sec, 9182945 t fired, .
53 EF FNDP 133/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 148213 t fired, 1260 attempts, .
54 EF STEQ 133/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 133/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 320191 m, 2450 m/sec, 320228 t fired, .

Time elapsed: 172 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 139/209 31/32 DoubleLock-PT-p1s2-CTLFireability-06 4764436 m, 34592 m/sec, 9528871 t fired, .
53 EF FNDP 138/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 154021 t fired, 1311 attempts, .
54 EF STEQ 138/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 138/3561 2/5 DoubleLock-PT-p1s2-CTLFireability-11 332437 m, 2449 m/sec, 332474 t fired, .

Time elapsed: 177 secs. Pages in use: 33
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 144/209 32/32 DoubleLock-PT-p1s2-CTLFireability-06 4937480 m, 34608 m/sec, 9874959 t fired, .
53 EF FNDP 143/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 159768 t fired, 1366 attempts, .
54 EF STEQ 143/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 143/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 344685 m, 2449 m/sec, 344722 t fired, .

Time elapsed: 182 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 23 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 148/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 165457 t fired, 1426 attempts, .
54 EF STEQ 148/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 148/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 357099 m, 2482 m/sec, 357136 t fired, .

Time elapsed: 187 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 52 (type EXCL) for 6 DoubleLock-PT-p1s2-CTLFireability-02
lola: time limit : 213 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 5/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 6686 m, 1337 m/sec, 7420 t fired, .
53 EF FNDP 153/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 171176 t fired, 1481 attempts, .
54 EF STEQ 153/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 153/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 368973 m, 2374 m/sec, 369010 t fired, .

Time elapsed: 192 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 10/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 13526 m, 1368 m/sec, 15020 t fired, .
53 EF FNDP 158/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 176883 t fired, 1538 attempts, .
54 EF STEQ 158/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 158/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 381210 m, 2447 m/sec, 381247 t fired, .

Time elapsed: 197 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 15/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 20367 m, 1368 m/sec, 22621 t fired, .
53 EF FNDP 163/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 182538 t fired, 1597 attempts, .
54 EF STEQ 163/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 163/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 393464 m, 2450 m/sec, 393501 t fired, .

Time elapsed: 202 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 20/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 27209 m, 1368 m/sec, 30224 t fired, .
53 EF FNDP 168/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 188188 t fired, 1658 attempts, .
54 EF STEQ 168/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 168/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 405697 m, 2446 m/sec, 405734 t fired, .

Time elapsed: 207 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 25/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 34068 m, 1371 m/sec, 37845 t fired, .
53 EF FNDP 173/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 193933 t fired, 1715 attempts, .
54 EF STEQ 173/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 173/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 417965 m, 2453 m/sec, 418002 t fired, .

Time elapsed: 212 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 30/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 40915 m, 1369 m/sec, 45452 t fired, .
53 EF FNDP 178/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 199646 t fired, 1772 attempts, .
54 EF STEQ 178/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 178/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 430223 m, 2451 m/sec, 430260 t fired, .

Time elapsed: 217 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 35/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 47755 m, 1368 m/sec, 53053 t fired, .
53 EF FNDP 183/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 205300 t fired, 1830 attempts, .
54 EF STEQ 183/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 183/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 442557 m, 2466 m/sec, 442594 t fired, .

Time elapsed: 222 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 40/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 54382 m, 1325 m/sec, 60415 t fired, .
53 EF FNDP 188/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 210993 t fired, 1891 attempts, .
54 EF STEQ 188/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 188/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 454597 m, 2408 m/sec, 454634 t fired, .

Time elapsed: 227 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 45/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 61233 m, 1370 m/sec, 68028 t fired, .
53 EF FNDP 193/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 216699 t fired, 1947 attempts, .
54 EF STEQ 193/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 193/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 466941 m, 2468 m/sec, 466978 t fired, .

Time elapsed: 232 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 50/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 68091 m, 1371 m/sec, 75648 t fired, .
53 EF FNDP 198/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 222392 t fired, 2007 attempts, .
54 EF STEQ 198/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 198/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 479335 m, 2478 m/sec, 479372 t fired, .

Time elapsed: 237 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 55/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 74947 m, 1371 m/sec, 83266 t fired, .
53 EF FNDP 203/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 228120 t fired, 2067 attempts, .
54 EF STEQ 203/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 203/3561 3/5 DoubleLock-PT-p1s2-CTLFireability-11 491733 m, 2479 m/sec, 491770 t fired, .

Time elapsed: 242 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 60/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 81722 m, 1355 m/sec, 90794 t fired, .
53 EF FNDP 208/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 233843 t fired, 2126 attempts, .
54 EF STEQ 208/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 208/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 504049 m, 2463 m/sec, 504086 t fired, .

Time elapsed: 247 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 65/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 88376 m, 1330 m/sec, 98186 t fired, .
53 EF FNDP 213/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 239573 t fired, 2181 attempts, .
54 EF STEQ 213/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 213/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 516440 m, 2478 m/sec, 516477 t fired, .

Time elapsed: 252 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 70/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 94916 m, 1308 m/sec, 105453 t fired, .
53 EF FNDP 218/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 245261 t fired, 2241 attempts, .
54 EF STEQ 218/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 218/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 528904 m, 2492 m/sec, 528941 t fired, .

Time elapsed: 257 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 75/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 101459 m, 1308 m/sec, 112724 t fired, .
53 EF FNDP 223/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 250893 t fired, 2302 attempts, .
54 EF STEQ 223/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 223/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 541707 m, 2560 m/sec, 541744 t fired, .

Time elapsed: 262 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 80/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 108010 m, 1310 m/sec, 120002 t fired, .
53 EF FNDP 228/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 256595 t fired, 2363 attempts, .
54 EF STEQ 228/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 228/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 554518 m, 2562 m/sec, 554555 t fired, .

Time elapsed: 267 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 85/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 114750 m, 1348 m/sec, 127491 t fired, .
53 EF FNDP 233/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 262260 t fired, 2423 attempts, .
54 EF STEQ 233/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 233/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 566726 m, 2441 m/sec, 566763 t fired, .

Time elapsed: 272 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 90/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 121541 m, 1358 m/sec, 135036 t fired, .
53 EF FNDP 238/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 267951 t fired, 2481 attempts, .
54 EF STEQ 238/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 238/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 578990 m, 2452 m/sec, 579027 t fired, .

Time elapsed: 277 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 95/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 128177 m, 1327 m/sec, 142410 t fired, .
53 EF FNDP 243/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 273525 t fired, 2535 attempts, .
54 EF STEQ 243/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 243/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 591635 m, 2529 m/sec, 591672 t fired, .

Time elapsed: 282 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 100/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 134811 m, 1326 m/sec, 149781 t fired, .
53 EF FNDP 248/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 278953 t fired, 2591 attempts, .
54 EF STEQ 248/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 248/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 604418 m, 2556 m/sec, 604455 t fired, .

Time elapsed: 287 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 105/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 141435 m, 1324 m/sec, 157141 t fired, .
53 EF FNDP 253/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 284275 t fired, 2649 attempts, .
54 EF STEQ 253/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 253/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 617212 m, 2558 m/sec, 617249 t fired, .

Time elapsed: 292 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 110/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 148088 m, 1330 m/sec, 164534 t fired, .
53 EF FNDP 258/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 289571 t fired, 2705 attempts, .
54 EF STEQ 258/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 258/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 630038 m, 2565 m/sec, 630075 t fired, .

Time elapsed: 297 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 115/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 154757 m, 1333 m/sec, 171944 t fired, .
53 EF FNDP 263/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 294958 t fired, 2759 attempts, .
54 EF STEQ 263/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 263/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 642868 m, 2566 m/sec, 642905 t fired, .

Time elapsed: 302 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 120/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 161426 m, 1333 m/sec, 179354 t fired, .
53 EF FNDP 268/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 300348 t fired, 2814 attempts, .
54 EF STEQ 268/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 268/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 655725 m, 2571 m/sec, 655762 t fired, .

Time elapsed: 307 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 125/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 168075 m, 1329 m/sec, 186741 t fired, .
53 EF FNDP 273/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 305649 t fired, 2873 attempts, .
54 EF STEQ 273/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 273/3561 4/5 DoubleLock-PT-p1s2-CTLFireability-11 668509 m, 2556 m/sec, 668546 t fired, .

Time elapsed: 312 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 130/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 174865 m, 1358 m/sec, 194285 t fired, .
53 EF FNDP 278/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 311147 t fired, 2931 attempts, .
54 EF STEQ 278/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 278/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 681094 m, 2517 m/sec, 681131 t fired, .

Time elapsed: 317 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 135/213 1/32 DoubleLock-PT-p1s2-CTLFireability-02 181840 m, 1395 m/sec, 202036 t fired, .
53 EF FNDP 283/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 316733 t fired, 2992 attempts, .
54 EF STEQ 283/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 283/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 693411 m, 2463 m/sec, 693448 t fired, .

Time elapsed: 322 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 140/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 188816 m, 1395 m/sec, 209786 t fired, .
53 EF FNDP 288/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 321970 t fired, 3049 attempts, .
54 EF STEQ 288/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 288/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 705539 m, 2425 m/sec, 705576 t fired, .

Time elapsed: 327 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 145/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 195712 m, 1379 m/sec, 217449 t fired, .
53 EF FNDP 293/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 327559 t fired, 3109 attempts, .
54 EF STEQ 293/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 293/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 717822 m, 2456 m/sec, 717859 t fired, .

Time elapsed: 332 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 150/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 202648 m, 1387 m/sec, 225155 t fired, .
53 EF FNDP 298/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 333134 t fired, 3172 attempts, .
54 EF STEQ 298/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 298/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 730092 m, 2454 m/sec, 730129 t fired, .

Time elapsed: 337 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 155/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 209586 m, 1387 m/sec, 232864 t fired, .
53 EF FNDP 303/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 338727 t fired, 3233 attempts, .
54 EF STEQ 303/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 303/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 742381 m, 2457 m/sec, 742418 t fired, .

Time elapsed: 342 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 160/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 216529 m, 1388 m/sec, 240579 t fired, .
53 EF FNDP 308/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 344334 t fired, 3291 attempts, .
54 EF STEQ 308/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 308/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 754659 m, 2455 m/sec, 754696 t fired, .

Time elapsed: 347 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 165/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 223474 m, 1389 m/sec, 248296 t fired, .
53 EF FNDP 313/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 349992 t fired, 3350 attempts, .
54 EF STEQ 313/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 313/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 766952 m, 2458 m/sec, 766989 t fired, .

Time elapsed: 352 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 170/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 230411 m, 1387 m/sec, 256004 t fired, .
53 EF FNDP 318/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 355604 t fired, 3414 attempts, .
54 EF STEQ 318/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 318/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 779230 m, 2455 m/sec, 779267 t fired, .

Time elapsed: 357 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 175/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 237353 m, 1388 m/sec, 263717 t fired, .
53 EF FNDP 323/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 361216 t fired, 3474 attempts, .
54 EF STEQ 323/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 323/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 791519 m, 2457 m/sec, 791556 t fired, .

Time elapsed: 362 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 180/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 244307 m, 1390 m/sec, 271443 t fired, .
53 EF FNDP 328/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 366748 t fired, 3536 attempts, .
54 EF STEQ 328/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 328/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 803785 m, 2453 m/sec, 803822 t fired, .

Time elapsed: 367 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 185/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 251248 m, 1388 m/sec, 279155 t fired, .
53 EF FNDP 333/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 372282 t fired, 3600 attempts, .
54 EF STEQ 333/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 333/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 816072 m, 2457 m/sec, 816109 t fired, .

Time elapsed: 372 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 3 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 190/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 258190 m, 1388 m/sec, 286869 t fired, .
53 EF FNDP 338/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 377881 t fired, 3662 attempts, .
54 EF STEQ 338/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.
56 EF SRCH 338/3561 5/5 DoubleLock-PT-p1s2-CTLFireability-11 828327 m, 2451 m/sec, 828364 t fired, .

Time elapsed: 377 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 56 (type SRCH) for DoubleLock-PT-p1s2-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 195/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 264805 m, 1323 m/sec, 294219 t fired, .
53 EF FNDP 343/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 383162 t fired, 3723 attempts, .
54 EF STEQ 343/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 382 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 200/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 271788 m, 1396 m/sec, 301977 t fired, .
53 EF FNDP 348/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 388714 t fired, 3782 attempts, .
54 EF STEQ 348/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 387 secs. Pages in use: 35
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 205/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 278775 m, 1397 m/sec, 309741 t fired, .
53 EF FNDP 353/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 394280 t fired, 3843 attempts, .
54 EF STEQ 353/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 392 secs. Pages in use: 35
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 210/213 2/32 DoubleLock-PT-p1s2-CTLFireability-02 285755 m, 1396 m/sec, 317496 t fired, .
53 EF FNDP 358/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 399828 t fired, 3905 attempts, .
54 EF STEQ 358/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 397 secs. Pages in use: 35
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-02 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 2 1 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 363/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 405390 t fired, 3967 attempts, .
54 EF STEQ 363/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 402 secs. Pages in use: 35
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 50 (type EXCL) for 49 DoubleLock-PT-p1s2-CTLFireability-15
lola: time limit : 213 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 52 (type EXCL) for 6 DoubleLock-PT-p1s2-CTLFireability-02
lola: time limit : 3198 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 5/213 2/32 DoubleLock-PT-p1s2-CTLFireability-15 182643 m, 36528 m/sec, 182643 t fired, .
52 EXEF EXCL 5/3198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 5590 m, -56033 m/sec, 6202 t fired, .
53 EF FNDP 368/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 409820 t fired, 4016 attempts, .
54 EF STEQ 368/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 407 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 10/213 3/32 DoubleLock-PT-p1s2-CTLFireability-15 365120 m, 36495 m/sec, 365121 t fired, .
52 EXEF EXCL 10/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 11191 m, 1120 m/sec, 12425 t fired, .
53 EF FNDP 373/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 414231 t fired, 4066 attempts, .
54 EF STEQ 373/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 412 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 15/213 4/32 DoubleLock-PT-p1s2-CTLFireability-15 545183 m, 36012 m/sec, 545183 t fired, .
52 EXEF EXCL 15/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 16545 m, 1070 m/sec, 18375 t fired, .
53 EF FNDP 378/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 418639 t fired, 4115 attempts, .
54 EF STEQ 378/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 417 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 20/213 5/32 DoubleLock-PT-p1s2-CTLFireability-15 737587 m, 38480 m/sec, 737588 t fired, .
52 EXEF EXCL 20/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 21789 m, 1048 m/sec, 24201 t fired, .
53 EF FNDP 383/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 423133 t fired, 4164 attempts, .
54 EF STEQ 383/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 422 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 25/213 6/32 DoubleLock-PT-p1s2-CTLFireability-15 915624 m, 35607 m/sec, 915624 t fired, .
52 EXEF EXCL 25/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 26863 m, 1014 m/sec, 29839 t fired, .
53 EF FNDP 388/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 427681 t fired, 4212 attempts, .
54 EF STEQ 388/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 427 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 30/213 7/32 DoubleLock-PT-p1s2-CTLFireability-15 1096955 m, 36266 m/sec, 1096955 t fired, .
52 EXEF EXCL 30/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 32327 m, 1092 m/sec, 35910 t fired, .
53 EF FNDP 393/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 431988 t fired, 4261 attempts, .
54 EF STEQ 393/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 432 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 35/213 9/32 DoubleLock-PT-p1s2-CTLFireability-15 1279599 m, 36528 m/sec, 1279599 t fired, .
52 EXEF EXCL 35/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 37692 m, 1073 m/sec, 41871 t fired, .
53 EF FNDP 398/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 436218 t fired, 4307 attempts, .
54 EF STEQ 398/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 437 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 40/213 10/32 DoubleLock-PT-p1s2-CTLFireability-15 1460820 m, 36244 m/sec, 1460820 t fired, .
52 EXEF EXCL 40/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 43039 m, 1069 m/sec, 47812 t fired, .
53 EF FNDP 403/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 440598 t fired, 4356 attempts, .
54 EF STEQ 403/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 442 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 45/213 11/32 DoubleLock-PT-p1s2-CTLFireability-15 1639333 m, 35702 m/sec, 1639334 t fired, .
52 EXEF EXCL 45/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 48447 m, 1081 m/sec, 53821 t fired, .
53 EF FNDP 408/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 445279 t fired, 4406 attempts, .
54 EF STEQ 408/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 447 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 50/213 12/32 DoubleLock-PT-p1s2-CTLFireability-15 1837150 m, 39563 m/sec, 1837150 t fired, .
52 EXEF EXCL 50/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 53653 m, 1041 m/sec, 59605 t fired, .
53 EF FNDP 413/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 449978 t fired, 4460 attempts, .
54 EF STEQ 413/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 452 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 55/213 13/32 DoubleLock-PT-p1s2-CTLFireability-15 2004870 m, 33544 m/sec, 2004871 t fired, .
52 EXEF EXCL 55/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 59031 m, 1075 m/sec, 65581 t fired, .
53 EF FNDP 418/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 454335 t fired, 4511 attempts, .
54 EF STEQ 418/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 457 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 60/213 14/32 DoubleLock-PT-p1s2-CTLFireability-15 2200724 m, 39170 m/sec, 2200724 t fired, .
52 EXEF EXCL 60/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 64354 m, 1064 m/sec, 71496 t fired, .
53 EF FNDP 423/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 458687 t fired, 4555 attempts, .
54 EF STEQ 423/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 462 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 65/213 16/32 DoubleLock-PT-p1s2-CTLFireability-15 2374323 m, 34719 m/sec, 2374323 t fired, .
52 EXEF EXCL 65/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 69733 m, 1075 m/sec, 77473 t fired, .
53 EF FNDP 428/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 462999 t fired, 4605 attempts, .
54 EF STEQ 428/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 467 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 70/213 17/32 DoubleLock-PT-p1s2-CTLFireability-15 2564110 m, 37957 m/sec, 2564110 t fired, .
52 EXEF EXCL 70/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 75241 m, 1101 m/sec, 83593 t fired, .
53 EF FNDP 433/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 467103 t fired, 4651 attempts, .
54 EF STEQ 433/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 472 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 75/213 18/32 DoubleLock-PT-p1s2-CTLFireability-15 2755012 m, 38180 m/sec, 2755012 t fired, .
52 EXEF EXCL 75/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 80544 m, 1060 m/sec, 89484 t fired, .
53 EF FNDP 438/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 471494 t fired, 4697 attempts, .
54 EF STEQ 438/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 477 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 80/213 19/32 DoubleLock-PT-p1s2-CTLFireability-15 2935095 m, 36016 m/sec, 2935095 t fired, .
52 EXEF EXCL 80/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 86119 m, 1115 m/sec, 95679 t fired, .
53 EF FNDP 443/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 475911 t fired, 4743 attempts, .
54 EF STEQ 443/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 482 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 85/213 20/32 DoubleLock-PT-p1s2-CTLFireability-15 3126691 m, 38319 m/sec, 3126692 t fired, .
52 EXEF EXCL 85/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 91334 m, 1043 m/sec, 101474 t fired, .
53 EF FNDP 448/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 480259 t fired, 4794 attempts, .
54 EF STEQ 448/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 487 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 90/213 21/32 DoubleLock-PT-p1s2-CTLFireability-15 3310710 m, 36803 m/sec, 3310710 t fired, .
52 EXEF EXCL 90/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 96822 m, 1097 m/sec, 107571 t fired, .
53 EF FNDP 453/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 484489 t fired, 4841 attempts, .
54 EF STEQ 453/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 492 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 95/213 23/32 DoubleLock-PT-p1s2-CTLFireability-15 3497149 m, 37287 m/sec, 3497149 t fired, .
52 EXEF EXCL 95/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 102478 m, 1131 m/sec, 113855 t fired, .
53 EF FNDP 458/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 488789 t fired, 4891 attempts, .
54 EF STEQ 458/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 497 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 100/213 24/32 DoubleLock-PT-p1s2-CTLFireability-15 3680102 m, 36590 m/sec, 3680102 t fired, .
52 EXEF EXCL 100/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 107812 m, 1066 m/sec, 119782 t fired, .
53 EF FNDP 463/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 493316 t fired, 4943 attempts, .
54 EF STEQ 463/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 502 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 105/213 25/32 DoubleLock-PT-p1s2-CTLFireability-15 3861303 m, 36240 m/sec, 3861303 t fired, .
52 EXEF EXCL 105/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 113366 m, 1110 m/sec, 125954 t fired, .
53 EF FNDP 468/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 497700 t fired, 4992 attempts, .
54 EF STEQ 468/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 507 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 110/213 26/32 DoubleLock-PT-p1s2-CTLFireability-15 4044595 m, 36658 m/sec, 4044595 t fired, .
52 EXEF EXCL 110/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 118531 m, 1033 m/sec, 131692 t fired, .
53 EF FNDP 473/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 502073 t fired, 5036 attempts, .
54 EF STEQ 473/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 512 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 115/213 27/32 DoubleLock-PT-p1s2-CTLFireability-15 4225740 m, 36229 m/sec, 4225740 t fired, .
52 EXEF EXCL 115/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 123714 m, 1036 m/sec, 137451 t fired, .
53 EF FNDP 478/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 506720 t fired, 5088 attempts, .
54 EF STEQ 478/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 517 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 120/213 28/32 DoubleLock-PT-p1s2-CTLFireability-15 4411066 m, 37065 m/sec, 4411066 t fired, .
52 EXEF EXCL 120/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 129355 m, 1128 m/sec, 143719 t fired, .
53 EF FNDP 483/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 511063 t fired, 5137 attempts, .
54 EF STEQ 483/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 522 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 125/213 30/32 DoubleLock-PT-p1s2-CTLFireability-15 4598283 m, 37443 m/sec, 4598283 t fired, .
52 EXEF EXCL 125/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 134460 m, 1021 m/sec, 149391 t fired, .
53 EF FNDP 488/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 515456 t fired, 5189 attempts, .
54 EF STEQ 488/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 527 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 130/213 31/32 DoubleLock-PT-p1s2-CTLFireability-15 4795712 m, 39485 m/sec, 4795712 t fired, .
52 EXEF EXCL 130/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 139970 m, 1102 m/sec, 155513 t fired, .
53 EF FNDP 493/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 519638 t fired, 5237 attempts, .
54 EF STEQ 493/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 532 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 135/213 32/32 DoubleLock-PT-p1s2-CTLFireability-15 4973923 m, 35642 m/sec, 4973923 t fired, .
52 EXEF EXCL 135/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 145180 m, 1042 m/sec, 161302 t fired, .
53 EF FNDP 498/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 524132 t fired, 5285 attempts, .
54 EF STEQ 498/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 537 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 50 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 140/199 1/5 DoubleLock-PT-p1s2-CTLFireability-02 151450 m, 1254 m/sec, 168268 t fired, .
53 EF FNDP 503/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 529073 t fired, 5340 attempts, .
54 EF STEQ 503/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 542 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 145/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 158330 m, 1376 m/sec, 175913 t fired, .
53 EF FNDP 508/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 534404 t fired, 5400 attempts, .
54 EF STEQ 508/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 547 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 150/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 165219 m, 1377 m/sec, 183567 t fired, .
53 EF FNDP 513/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 539717 t fired, 5463 attempts, .
54 EF STEQ 513/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 552 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 155/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 172100 m, 1376 m/sec, 191213 t fired, .
53 EF FNDP 518/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 545094 t fired, 5523 attempts, .
54 EF STEQ 518/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 557 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 160/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 178976 m, 1375 m/sec, 198854 t fired, .
53 EF FNDP 523/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 550473 t fired, 5583 attempts, .
54 EF STEQ 523/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 562 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 165/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 185856 m, 1376 m/sec, 206497 t fired, .
53 EF FNDP 528/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 555767 t fired, 5645 attempts, .
54 EF STEQ 528/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 567 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 170/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 192727 m, 1374 m/sec, 214132 t fired, .
53 EF FNDP 533/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 561110 t fired, 5710 attempts, .
54 EF STEQ 533/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 572 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 175/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 199616 m, 1377 m/sec, 221786 t fired, .
53 EF FNDP 538/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 566477 t fired, 5769 attempts, .
54 EF STEQ 538/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 577 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 180/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 206495 m, 1375 m/sec, 229430 t fired, .
53 EF FNDP 543/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 571833 t fired, 5827 attempts, .
54 EF STEQ 543/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 582 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 185/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 213381 m, 1377 m/sec, 237081 t fired, .
53 EF FNDP 548/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 577217 t fired, 5889 attempts, .
54 EF STEQ 548/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 587 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 190/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 220265 m, 1376 m/sec, 244730 t fired, .
53 EF FNDP 553/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 582552 t fired, 5951 attempts, .
54 EF STEQ 553/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 592 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 195/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 227138 m, 1374 m/sec, 252366 t fired, .
53 EF FNDP 558/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 587935 t fired, 6010 attempts, .
54 EF STEQ 558/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 597 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 200/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 234022 m, 1376 m/sec, 260015 t fired, .
53 EF FNDP 563/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 593313 t fired, 6065 attempts, .
54 EF STEQ 563/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 602 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 205/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 240906 m, 1376 m/sec, 267664 t fired, .
53 EF FNDP 568/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 598651 t fired, 6128 attempts, .
54 EF STEQ 568/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 607 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 210/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 247781 m, 1375 m/sec, 275303 t fired, .
53 EF FNDP 573/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 604017 t fired, 6189 attempts, .
54 EF STEQ 573/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 612 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-02 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 2 1 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 578/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 609350 t fired, 6252 attempts, .
54 EF STEQ 578/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 617 secs. Pages in use: 36
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 47 (type EXCL) for 46 DoubleLock-PT-p1s2-CTLFireability-14
lola: time limit : 213 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 52 (type EXCL) for 6 DoubleLock-PT-p1s2-CTLFireability-02
lola: time limit : 2983 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 5/213 2/32 DoubleLock-PT-p1s2-CTLFireability-14 193332 m, 38666 m/sec, 193331 t fired, .
52 EXEF EXCL 5/2983 1/5 DoubleLock-PT-p1s2-CTLFireability-02 5002 m, -48555 m/sec, 5548 t fired, .
53 EF FNDP 583/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 613857 t fired, 6300 attempts, .
54 EF STEQ 583/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 622 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 10/213 3/32 DoubleLock-PT-p1s2-CTLFireability-14 379178 m, 37169 m/sec, 379177 t fired, .
52 EXEF EXCL 10/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 10562 m, 1112 m/sec, 11726 t fired, .
53 EF FNDP 588/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 617943 t fired, 6348 attempts, .
54 EF STEQ 588/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 627 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 15/213 4/32 DoubleLock-PT-p1s2-CTLFireability-14 555598 m, 35284 m/sec, 555597 t fired, .
52 EXEF EXCL 15/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 16120 m, 1111 m/sec, 17902 t fired, .
53 EF FNDP 593/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 622116 t fired, 6399 attempts, .
54 EF STEQ 593/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 632 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 20/213 5/32 DoubleLock-PT-p1s2-CTLFireability-14 742546 m, 37389 m/sec, 742545 t fired, .
52 EXEF EXCL 20/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 21854 m, 1146 m/sec, 24273 t fired, .
53 EF FNDP 598/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 626151 t fired, 6447 attempts, .
54 EF STEQ 598/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 637 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 25/213 6/32 DoubleLock-PT-p1s2-CTLFireability-14 919515 m, 35393 m/sec, 919514 t fired, .
52 EXEF EXCL 25/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 27128 m, 1054 m/sec, 30134 t fired, .
53 EF FNDP 603/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 630588 t fired, 6501 attempts, .
54 EF STEQ 603/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 642 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 30/213 7/32 DoubleLock-PT-p1s2-CTLFireability-14 1099039 m, 35904 m/sec, 1099038 t fired, .
52 EXEF EXCL 30/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 32142 m, 1002 m/sec, 35704 t fired, .
53 EF FNDP 608/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 635016 t fired, 6553 attempts, .
54 EF STEQ 608/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 647 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 35/213 9/32 DoubleLock-PT-p1s2-CTLFireability-14 1288049 m, 37802 m/sec, 1288049 t fired, .
52 EXEF EXCL 35/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 37622 m, 1096 m/sec, 41793 t fired, .
53 EF FNDP 613/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 639409 t fired, 6602 attempts, .
54 EF STEQ 613/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 652 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 40/213 10/32 DoubleLock-PT-p1s2-CTLFireability-14 1472133 m, 36816 m/sec, 1472133 t fired, .
52 EXEF EXCL 40/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 42873 m, 1050 m/sec, 47628 t fired, .
53 EF FNDP 618/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 643704 t fired, 6650 attempts, .
54 EF STEQ 618/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 657 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 45/213 11/32 DoubleLock-PT-p1s2-CTLFireability-14 1650592 m, 35691 m/sec, 1650591 t fired, .
52 EXEF EXCL 45/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 48069 m, 1039 m/sec, 53401 t fired, .
53 EF FNDP 623/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 648027 t fired, 6700 attempts, .
54 EF STEQ 623/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 662 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 50/213 12/32 DoubleLock-PT-p1s2-CTLFireability-14 1824646 m, 34810 m/sec, 1824645 t fired, .
52 EXEF EXCL 50/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 53415 m, 1069 m/sec, 59341 t fired, .
53 EF FNDP 628/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 652397 t fired, 6749 attempts, .
54 EF STEQ 628/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 667 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 55/213 13/32 DoubleLock-PT-p1s2-CTLFireability-14 2004816 m, 36034 m/sec, 2004815 t fired, .
52 EXEF EXCL 55/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 58660 m, 1049 m/sec, 65169 t fired, .
53 EF FNDP 633/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 656580 t fired, 6795 attempts, .
54 EF STEQ 633/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 672 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 60/213 14/32 DoubleLock-PT-p1s2-CTLFireability-14 2187702 m, 36577 m/sec, 2187702 t fired, .
52 EXEF EXCL 60/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 64098 m, 1087 m/sec, 71211 t fired, .
53 EF FNDP 638/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 660778 t fired, 6842 attempts, .
54 EF STEQ 638/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 677 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 65/213 16/32 DoubleLock-PT-p1s2-CTLFireability-14 2374408 m, 37341 m/sec, 2374407 t fired, .
52 EXEF EXCL 65/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 69440 m, 1068 m/sec, 77147 t fired, .
53 EF FNDP 643/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 665192 t fired, 6891 attempts, .
54 EF STEQ 643/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 682 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 70/213 17/32 DoubleLock-PT-p1s2-CTLFireability-14 2564760 m, 38070 m/sec, 2564760 t fired, .
52 EXEF EXCL 70/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 74947 m, 1101 m/sec, 83266 t fired, .
53 EF FNDP 648/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 669545 t fired, 6940 attempts, .
54 EF STEQ 648/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 687 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 75/213 18/32 DoubleLock-PT-p1s2-CTLFireability-14 2742253 m, 35498 m/sec, 2742253 t fired, .
52 EXEF EXCL 75/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 80568 m, 1124 m/sec, 89511 t fired, .
53 EF FNDP 653/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 673752 t fired, 6989 attempts, .
54 EF STEQ 653/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 692 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 80/213 19/32 DoubleLock-PT-p1s2-CTLFireability-14 2926798 m, 36909 m/sec, 2926797 t fired, .
52 EXEF EXCL 80/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 86148 m, 1116 m/sec, 95711 t fired, .
53 EF FNDP 658/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 678069 t fired, 7039 attempts, .
54 EF STEQ 658/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 697 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 85/213 20/32 DoubleLock-PT-p1s2-CTLFireability-14 3112826 m, 37205 m/sec, 3112825 t fired, .
52 EXEF EXCL 85/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 91033 m, 977 m/sec, 101139 t fired, .
53 EF FNDP 663/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 682474 t fired, 7085 attempts, .
54 EF STEQ 663/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 702 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 90/213 21/32 DoubleLock-PT-p1s2-CTLFireability-14 3293727 m, 36180 m/sec, 3293726 t fired, .
52 EXEF EXCL 90/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 96358 m, 1065 m/sec, 107056 t fired, .
53 EF FNDP 668/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 687005 t fired, 7137 attempts, .
54 EF STEQ 668/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 707 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 95/213 22/32 DoubleLock-PT-p1s2-CTLFireability-14 3471057 m, 35466 m/sec, 3471056 t fired, .
52 EXEF EXCL 95/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 101912 m, 1110 m/sec, 113226 t fired, .
53 EF FNDP 673/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 691483 t fired, 7186 attempts, .
54 EF STEQ 673/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 712 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 100/213 24/32 DoubleLock-PT-p1s2-CTLFireability-14 3658999 m, 37588 m/sec, 3658998 t fired, .
52 EXEF EXCL 100/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 107047 m, 1027 m/sec, 118933 t fired, .
53 EF FNDP 678/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 695821 t fired, 7236 attempts, .
54 EF STEQ 678/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 717 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 105/213 25/32 DoubleLock-PT-p1s2-CTLFireability-14 3846174 m, 37435 m/sec, 3846173 t fired, .
52 EXEF EXCL 105/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 112336 m, 1057 m/sec, 124809 t fired, .
53 EF FNDP 683/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 700308 t fired, 7288 attempts, .
54 EF STEQ 683/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 722 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 110/213 26/32 DoubleLock-PT-p1s2-CTLFireability-14 4034333 m, 37631 m/sec, 4034332 t fired, .
52 EXEF EXCL 110/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 117534 m, 1039 m/sec, 130584 t fired, .
53 EF FNDP 688/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 704824 t fired, 7338 attempts, .
54 EF STEQ 688/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 727 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 115/213 27/32 DoubleLock-PT-p1s2-CTLFireability-14 4218318 m, 36797 m/sec, 4218317 t fired, .
52 EXEF EXCL 115/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 122711 m, 1035 m/sec, 136337 t fired, .
53 EF FNDP 693/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 709160 t fired, 7388 attempts, .
54 EF STEQ 693/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 732 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 120/213 28/32 DoubleLock-PT-p1s2-CTLFireability-14 4403446 m, 37025 m/sec, 4403445 t fired, .
52 EXEF EXCL 120/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 128219 m, 1101 m/sec, 142457 t fired, .
53 EF FNDP 698/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 713522 t fired, 7435 attempts, .
54 EF STEQ 698/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 737 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 125/213 30/32 DoubleLock-PT-p1s2-CTLFireability-14 4580130 m, 35336 m/sec, 4580129 t fired, .
52 EXEF EXCL 125/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 133808 m, 1117 m/sec, 148667 t fired, .
53 EF FNDP 703/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 717644 t fired, 7487 attempts, .
54 EF STEQ 703/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 742 secs. Pages in use: 38
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 130/213 31/32 DoubleLock-PT-p1s2-CTLFireability-14 4755105 m, 34995 m/sec, 4755104 t fired, .
52 EXEF EXCL 130/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 139362 m, 1110 m/sec, 154837 t fired, .
53 EF FNDP 708/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 722113 t fired, 7535 attempts, .
54 EF STEQ 708/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 747 secs. Pages in use: 39
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 135/213 32/32 DoubleLock-PT-p1s2-CTLFireability-14 4932684 m, 35515 m/sec, 4932683 t fired, .
52 EXEF EXCL 135/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 144933 m, 1114 m/sec, 161028 t fired, .
53 EF FNDP 713/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 726221 t fired, 7585 attempts, .
54 EF STEQ 713/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 752 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 47 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 140/198 1/5 DoubleLock-PT-p1s2-CTLFireability-02 150845 m, 1182 m/sec, 167597 t fired, .
53 EF FNDP 718/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 731112 t fired, 7645 attempts, .
54 EF STEQ 718/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 757 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 145/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 157738 m, 1378 m/sec, 175255 t fired, .
53 EF FNDP 723/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 736737 t fired, 7709 attempts, .
54 EF STEQ 723/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 762 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 150/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 164628 m, 1378 m/sec, 182911 t fired, .
53 EF FNDP 728/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 742312 t fired, 7778 attempts, .
54 EF STEQ 728/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 767 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 155/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 171515 m, 1377 m/sec, 190563 t fired, .
53 EF FNDP 733/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 747876 t fired, 7847 attempts, .
54 EF STEQ 733/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 772 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 160/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 178404 m, 1377 m/sec, 198217 t fired, .
53 EF FNDP 738/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 753484 t fired, 7913 attempts, .
54 EF STEQ 738/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 777 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 165/213 1/5 DoubleLock-PT-p1s2-CTLFireability-02 185282 m, 1375 m/sec, 205860 t fired, .
53 EF FNDP 743/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 759133 t fired, 7975 attempts, .
54 EF STEQ 743/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 782 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 170/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 192165 m, 1376 m/sec, 213507 t fired, .
53 EF FNDP 748/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 764737 t fired, 8042 attempts, .
54 EF STEQ 748/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 787 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 175/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 199052 m, 1377 m/sec, 221160 t fired, .
53 EF FNDP 753/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 770380 t fired, 8109 attempts, .
54 EF STEQ 753/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 792 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 180/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 205941 m, 1377 m/sec, 228814 t fired, .
53 EF FNDP 758/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 775975 t fired, 8173 attempts, .
54 EF STEQ 758/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 797 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 185/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 212832 m, 1378 m/sec, 236471 t fired, .
53 EF FNDP 763/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 781544 t fired, 8237 attempts, .
54 EF STEQ 763/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 802 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 190/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 219718 m, 1377 m/sec, 244123 t fired, .
53 EF FNDP 768/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 787155 t fired, 8301 attempts, .
54 EF STEQ 768/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 807 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 195/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 226603 m, 1377 m/sec, 251773 t fired, .
53 EF FNDP 773/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 792785 t fired, 8366 attempts, .
54 EF STEQ 773/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 812 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 200/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 233493 m, 1378 m/sec, 259428 t fired, .
53 EF FNDP 778/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 798460 t fired, 8426 attempts, .
54 EF STEQ 778/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 817 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 205/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 240376 m, 1376 m/sec, 267076 t fired, .
53 EF FNDP 783/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 804064 t fired, 8490 attempts, .
54 EF STEQ 783/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 822 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 210/213 2/5 DoubleLock-PT-p1s2-CTLFireability-02 247265 m, 1377 m/sec, 274730 t fired, .
53 EF FNDP 788/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 809670 t fired, 8556 attempts, .
54 EF STEQ 788/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 827 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-02 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 2 1 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 793/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 815248 t fired, 8620 attempts, .
54 EF STEQ 793/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 832 secs. Pages in use: 40
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 44 (type EXCL) for 43 DoubleLock-PT-p1s2-CTLFireability-13
lola: time limit : 212 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 52 (type EXCL) for 6 DoubleLock-PT-p1s2-CTLFireability-02
lola: time limit : 2768 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 5/212 3/32 DoubleLock-PT-p1s2-CTLFireability-13 316410 m, 63282 m/sec, 316409 t fired, .
52 EXEF EXCL 5/2768 1/5 DoubleLock-PT-p1s2-CTLFireability-02 5270 m, -48399 m/sec, 5846 t fired, .
53 EF FNDP 798/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 820075 t fired, 8675 attempts, .
54 EF STEQ 798/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 837 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 10/212 5/32 DoubleLock-PT-p1s2-CTLFireability-13 637132 m, 64144 m/sec, 637131 t fired, .
52 EXEF EXCL 10/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 11092 m, 1164 m/sec, 12316 t fired, .
53 EF FNDP 803/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 824202 t fired, 8726 attempts, .
54 EF STEQ 803/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 842 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 15/212 7/32 DoubleLock-PT-p1s2-CTLFireability-13 964332 m, 65440 m/sec, 964332 t fired, .
52 EXEF EXCL 15/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 16191 m, 1019 m/sec, 17981 t fired, .
53 EF FNDP 808/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 828361 t fired, 8777 attempts, .
54 EF STEQ 808/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 847 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 20/212 8/32 DoubleLock-PT-p1s2-CTLFireability-13 1262037 m, 59541 m/sec, 1262036 t fired, .
52 EXEF EXCL 20/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 21782 m, 1118 m/sec, 24194 t fired, .
53 EF FNDP 813/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 832736 t fired, 8828 attempts, .
54 EF STEQ 813/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 852 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 25/212 10/32 DoubleLock-PT-p1s2-CTLFireability-13 1578017 m, 63196 m/sec, 1578016 t fired, .
52 EXEF EXCL 25/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 27043 m, 1052 m/sec, 30039 t fired, .
53 EF FNDP 818/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 837205 t fired, 8878 attempts, .
54 EF STEQ 818/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 857 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 30/212 12/32 DoubleLock-PT-p1s2-CTLFireability-13 1888748 m, 62146 m/sec, 1888748 t fired, .
52 EXEF EXCL 30/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 32427 m, 1076 m/sec, 36021 t fired, .
53 EF FNDP 823/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 841466 t fired, 8928 attempts, .
54 EF STEQ 823/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 862 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 35/212 14/32 DoubleLock-PT-p1s2-CTLFireability-13 2194034 m, 61057 m/sec, 2194033 t fired, .
52 EXEF EXCL 35/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 37572 m, 1029 m/sec, 41737 t fired, .
53 EF FNDP 828/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 845793 t fired, 8979 attempts, .
54 EF STEQ 828/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 867 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 40/212 16/32 DoubleLock-PT-p1s2-CTLFireability-13 2482193 m, 57631 m/sec, 2482192 t fired, .
52 EXEF EXCL 40/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 43159 m, 1117 m/sec, 47945 t fired, .
53 EF FNDP 833/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 850123 t fired, 9027 attempts, .
54 EF STEQ 833/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 872 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 45/212 18/32 DoubleLock-PT-p1s2-CTLFireability-13 2777491 m, 59059 m/sec, 2777491 t fired, .
52 EXEF EXCL 45/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 48538 m, 1075 m/sec, 53923 t fired, .
53 EF FNDP 838/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 854461 t fired, 9079 attempts, .
54 EF STEQ 838/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 877 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 50/212 20/32 DoubleLock-PT-p1s2-CTLFireability-13 3086454 m, 61792 m/sec, 3086453 t fired, .
52 EXEF EXCL 50/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 54008 m, 1094 m/sec, 60000 t fired, .
53 EF FNDP 843/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 858690 t fired, 9131 attempts, .
54 EF STEQ 843/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 882 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 55/212 22/32 DoubleLock-PT-p1s2-CTLFireability-13 3386913 m, 60091 m/sec, 3386912 t fired, .
52 EXEF EXCL 55/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 59249 m, 1048 m/sec, 65823 t fired, .
53 EF FNDP 848/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 863088 t fired, 9187 attempts, .
54 EF STEQ 848/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 887 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 60/212 24/32 DoubleLock-PT-p1s2-CTLFireability-13 3692553 m, 61128 m/sec, 3692552 t fired, .
52 EXEF EXCL 60/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 64550 m, 1060 m/sec, 71714 t fired, .
53 EF FNDP 853/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 867266 t fired, 9237 attempts, .
54 EF STEQ 853/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 892 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 65/212 26/32 DoubleLock-PT-p1s2-CTLFireability-13 3998216 m, 61132 m/sec, 3998216 t fired, .
52 EXEF EXCL 65/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 69906 m, 1071 m/sec, 77664 t fired, .
53 EF FNDP 858/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 871650 t fired, 9287 attempts, .
54 EF STEQ 858/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 897 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 70/212 28/32 DoubleLock-PT-p1s2-CTLFireability-13 4308701 m, 62097 m/sec, 4308701 t fired, .
52 EXEF EXCL 70/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 75234 m, 1065 m/sec, 83584 t fired, .
53 EF FNDP 863/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 875894 t fired, 9337 attempts, .
54 EF STEQ 863/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 902 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 75/212 30/32 DoubleLock-PT-p1s2-CTLFireability-13 4609069 m, 60073 m/sec, 4609069 t fired, .
52 EXEF EXCL 75/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 80476 m, 1048 m/sec, 89409 t fired, .
53 EF FNDP 868/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 880360 t fired, 9390 attempts, .
54 EF STEQ 868/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 907 secs. Pages in use: 41
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 80/212 32/32 DoubleLock-PT-p1s2-CTLFireability-13 4910876 m, 60361 m/sec, 4910875 t fired, .
52 EXEF EXCL 80/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 86044 m, 1113 m/sec, 95596 t fired, .
53 EF FNDP 873/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 884960 t fired, 9443 attempts, .
54 EF STEQ 873/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 912 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 44 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 85/197 1/5 DoubleLock-PT-p1s2-CTLFireability-02 92124 m, 1216 m/sec, 102351 t fired, .
53 EF FNDP 878/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 889994 t fired, 9502 attempts, .
54 EF STEQ 878/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 917 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 90/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 98778 m, 1330 m/sec, 109744 t fired, .
53 EF FNDP 883/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 895558 t fired, 9567 attempts, .
54 EF STEQ 883/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 922 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 95/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 105428 m, 1330 m/sec, 117134 t fired, .
53 EF FNDP 888/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 901187 t fired, 9628 attempts, .
54 EF STEQ 888/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 927 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 100/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 112106 m, 1335 m/sec, 124553 t fired, .
53 EF FNDP 893/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 906518 t fired, 9686 attempts, .
54 EF STEQ 893/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 932 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 105/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 118762 m, 1331 m/sec, 131949 t fired, .
53 EF FNDP 898/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 912096 t fired, 9755 attempts, .
54 EF STEQ 898/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 937 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 110/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 125420 m, 1331 m/sec, 139346 t fired, .
53 EF FNDP 903/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 917703 t fired, 9822 attempts, .
54 EF STEQ 903/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 942 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 115/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 132077 m, 1331 m/sec, 146744 t fired, .
53 EF FNDP 908/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 923204 t fired, 9887 attempts, .
54 EF STEQ 908/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 947 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 120/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 138751 m, 1334 m/sec, 154159 t fired, .
53 EF FNDP 913/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 928708 t fired, 9950 attempts, .
54 EF STEQ 913/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 952 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 125/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 145249 m, 1299 m/sec, 161379 t fired, .
53 EF FNDP 918/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 934220 t fired, 10015 attempts, .
54 EF STEQ 918/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 957 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 130/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 151816 m, 1313 m/sec, 168676 t fired, .
53 EF FNDP 923/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 939767 t fired, 10080 attempts, .
54 EF STEQ 923/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 962 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 135/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 158390 m, 1314 m/sec, 175980 t fired, .
53 EF FNDP 928/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 945396 t fired, 10147 attempts, .
54 EF STEQ 928/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 967 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 140/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 164960 m, 1314 m/sec, 183280 t fired, .
53 EF FNDP 933/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 951024 t fired, 10209 attempts, .
54 EF STEQ 933/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 972 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 145/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 171528 m, 1313 m/sec, 190579 t fired, .
53 EF FNDP 938/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 956612 t fired, 10273 attempts, .
54 EF STEQ 938/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 977 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 150/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 178097 m, 1313 m/sec, 197876 t fired, .
53 EF FNDP 943/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 962218 t fired, 10339 attempts, .
54 EF STEQ 943/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 982 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 155/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 184666 m, 1313 m/sec, 205175 t fired, .
53 EF FNDP 948/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 967822 t fired, 10403 attempts, .
54 EF STEQ 948/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 987 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 160/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 191233 m, 1313 m/sec, 212473 t fired, .
53 EF FNDP 953/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 973390 t fired, 10468 attempts, .
54 EF STEQ 953/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 992 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 165/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 197803 m, 1314 m/sec, 219772 t fired, .
53 EF FNDP 958/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 978924 t fired, 10537 attempts, .
54 EF STEQ 958/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 997 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 170/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 204551 m, 1349 m/sec, 227270 t fired, .
53 EF FNDP 963/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 983660 t fired, 10596 attempts, .
54 EF STEQ 963/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1002 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 175/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 210752 m, 1240 m/sec, 234160 t fired, .
53 EF FNDP 968/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 988821 t fired, 10657 attempts, .
54 EF STEQ 968/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1007 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 180/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 217401 m, 1329 m/sec, 241548 t fired, .
53 EF FNDP 973/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 994392 t fired, 10724 attempts, .
54 EF STEQ 973/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1012 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 185/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 224042 m, 1328 m/sec, 248927 t fired, .
53 EF FNDP 978/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 999994 t fired, 10788 attempts, .
54 EF STEQ 978/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1017 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 190/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 230681 m, 1327 m/sec, 256304 t fired, .
53 EF FNDP 983/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1005622 t fired, 10855 attempts, .
54 EF STEQ 983/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1022 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 195/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 237335 m, 1330 m/sec, 263696 t fired, .
53 EF FNDP 988/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1011222 t fired, 10920 attempts, .
54 EF STEQ 988/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1027 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 200/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 243848 m, 1302 m/sec, 270933 t fired, .
53 EF FNDP 993/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1016425 t fired, 10983 attempts, .
54 EF STEQ 993/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1032 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 205/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 250451 m, 1320 m/sec, 278270 t fired, .
53 EF FNDP 998/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1021495 t fired, 11040 attempts, .
54 EF STEQ 998/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1037 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 210/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 256999 m, 1309 m/sec, 285545 t fired, .
53 EF FNDP 1003/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1027079 t fired, 11108 attempts, .
54 EF STEQ 1003/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1042 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-02 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 2 1 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 1008/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1032659 t fired, 11174 attempts, .
54 EF STEQ 1008/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1047 secs. Pages in use: 43
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 41 (type EXCL) for 40 DoubleLock-PT-p1s2-CTLFireability-12
lola: time limit : 212 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 52 (type EXCL) for 6 DoubleLock-PT-p1s2-CTLFireability-02
lola: time limit : 2553 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/212 2/32 DoubleLock-PT-p1s2-CTLFireability-12 205665 m, 41133 m/sec, 205664 t fired, .
52 EXEF EXCL 5/2553 1/5 DoubleLock-PT-p1s2-CTLFireability-02 4761 m, -50447 m/sec, 5281 t fired, .
53 EF FNDP 1013/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1036528 t fired, 11219 attempts, .
54 EF STEQ 1013/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1052 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/212 3/32 DoubleLock-PT-p1s2-CTLFireability-12 393517 m, 37570 m/sec, 393516 t fired, .
52 EXEF EXCL 10/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 10208 m, 1089 m/sec, 11333 t fired, .
53 EF FNDP 1018/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1040946 t fired, 11271 attempts, .
54 EF STEQ 1018/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1057 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/212 4/32 DoubleLock-PT-p1s2-CTLFireability-12 584271 m, 38150 m/sec, 584270 t fired, .
52 EXEF EXCL 15/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 15318 m, 1022 m/sec, 17011 t fired, .
53 EF FNDP 1023/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1045270 t fired, 11322 attempts, .
54 EF STEQ 1023/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1062 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/212 5/32 DoubleLock-PT-p1s2-CTLFireability-12 759189 m, 34983 m/sec, 759188 t fired, .
52 EXEF EXCL 20/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 20379 m, 1012 m/sec, 22635 t fired, .
53 EF FNDP 1028/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1049705 t fired, 11375 attempts, .
54 EF STEQ 1028/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1067 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/212 7/32 DoubleLock-PT-p1s2-CTLFireability-12 948390 m, 37840 m/sec, 948389 t fired, .
52 EXEF EXCL 25/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 25887 m, 1101 m/sec, 28755 t fired, .
53 EF FNDP 1033/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1054039 t fired, 11425 attempts, .
54 EF STEQ 1033/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1072 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/212 8/32 DoubleLock-PT-p1s2-CTLFireability-12 1135784 m, 37478 m/sec, 1135784 t fired, .
52 EXEF EXCL 30/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 31431 m, 1108 m/sec, 34914 t fired, .
53 EF FNDP 1038/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1058273 t fired, 11473 attempts, .
54 EF STEQ 1038/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1077 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 35/212 9/32 DoubleLock-PT-p1s2-CTLFireability-12 1318925 m, 36628 m/sec, 1318924 t fired, .
52 EXEF EXCL 35/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 37050 m, 1123 m/sec, 41157 t fired, .
53 EF FNDP 1043/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1062533 t fired, 11523 attempts, .
54 EF STEQ 1043/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1082 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 40/212 10/32 DoubleLock-PT-p1s2-CTLFireability-12 1512907 m, 38796 m/sec, 1512906 t fired, .
52 EXEF EXCL 40/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 42473 m, 1084 m/sec, 47183 t fired, .
53 EF FNDP 1048/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1066719 t fired, 11571 attempts, .
54 EF STEQ 1048/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1087 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 45/212 11/32 DoubleLock-PT-p1s2-CTLFireability-12 1701615 m, 37741 m/sec, 1701614 t fired, .
52 EXEF EXCL 45/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 47988 m, 1103 m/sec, 53311 t fired, .
53 EF FNDP 1053/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1070752 t fired, 11617 attempts, .
54 EF STEQ 1053/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1092 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 50/212 12/32 DoubleLock-PT-p1s2-CTLFireability-12 1891577 m, 37992 m/sec, 1891576 t fired, .
52 EXEF EXCL 50/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 53394 m, 1081 m/sec, 59317 t fired, .
53 EF FNDP 1058/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1075137 t fired, 11666 attempts, .
54 EF STEQ 1058/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1097 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 55/212 14/32 DoubleLock-PT-p1s2-CTLFireability-12 2082639 m, 38212 m/sec, 2082638 t fired, .
52 EXEF EXCL 55/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 58557 m, 1032 m/sec, 65055 t fired, .
53 EF FNDP 1063/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1079454 t fired, 11713 attempts, .
54 EF STEQ 1063/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1102 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 60/212 15/32 DoubleLock-PT-p1s2-CTLFireability-12 2268827 m, 37237 m/sec, 2268827 t fired, .
52 EXEF EXCL 60/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 63999 m, 1088 m/sec, 71101 t fired, .
53 EF FNDP 1068/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1083485 t fired, 11763 attempts, .
54 EF STEQ 1068/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1107 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 65/212 16/32 DoubleLock-PT-p1s2-CTLFireability-12 2460289 m, 38292 m/sec, 2460288 t fired, .
52 EXEF EXCL 65/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 69198 m, 1039 m/sec, 76878 t fired, .
53 EF FNDP 1073/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1088004 t fired, 11819 attempts, .
54 EF STEQ 1073/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1112 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 70/212 17/32 DoubleLock-PT-p1s2-CTLFireability-12 2652264 m, 38395 m/sec, 2652264 t fired, .
52 EXEF EXCL 70/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 74563 m, 1073 m/sec, 82839 t fired, .
53 EF FNDP 1078/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1092480 t fired, 11873 attempts, .
54 EF STEQ 1078/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1117 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 75/212 18/32 DoubleLock-PT-p1s2-CTLFireability-12 2833471 m, 36241 m/sec, 2833470 t fired, .
52 EXEF EXCL 75/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 80235 m, 1134 m/sec, 89141 t fired, .
53 EF FNDP 1083/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1096728 t fired, 11925 attempts, .
54 EF STEQ 1083/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1122 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 80/212 20/32 DoubleLock-PT-p1s2-CTLFireability-12 3024197 m, 38145 m/sec, 3024196 t fired, .
52 EXEF EXCL 80/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 85485 m, 1050 m/sec, 94974 t fired, .
53 EF FNDP 1088/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1101164 t fired, 11978 attempts, .
54 EF STEQ 1088/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1127 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 85/212 21/32 DoubleLock-PT-p1s2-CTLFireability-12 3213511 m, 37862 m/sec, 3213510 t fired, .
52 EXEF EXCL 85/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 90792 m, 1061 m/sec, 100871 t fired, .
53 EF FNDP 1093/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1105491 t fired, 12028 attempts, .
54 EF STEQ 1093/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1132 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 90/212 22/32 DoubleLock-PT-p1s2-CTLFireability-12 3398315 m, 36960 m/sec, 3398314 t fired, .
52 EXEF EXCL 90/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 96244 m, 1090 m/sec, 106929 t fired, .
53 EF FNDP 1098/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1109846 t fired, 12080 attempts, .
54 EF STEQ 1098/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1137 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 95/212 23/32 DoubleLock-PT-p1s2-CTLFireability-12 3581674 m, 36671 m/sec, 3581673 t fired, .
52 EXEF EXCL 95/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 101719 m, 1095 m/sec, 113012 t fired, .
53 EF FNDP 1103/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1114035 t fired, 12129 attempts, .
54 EF STEQ 1103/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1142 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 100/212 24/32 DoubleLock-PT-p1s2-CTLFireability-12 3765735 m, 36812 m/sec, 3765734 t fired, .
52 EXEF EXCL 100/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 107006 m, 1057 m/sec, 118886 t fired, .
53 EF FNDP 1108/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1118366 t fired, 12181 attempts, .
54 EF STEQ 1108/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1147 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 105/212 26/32 DoubleLock-PT-p1s2-CTLFireability-12 3950994 m, 37051 m/sec, 3950994 t fired, .
52 EXEF EXCL 105/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 112587 m, 1116 m/sec, 125088 t fired, .
53 EF FNDP 1113/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1122531 t fired, 12230 attempts, .
54 EF STEQ 1113/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1152 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 110/212 27/32 DoubleLock-PT-p1s2-CTLFireability-12 4138261 m, 37453 m/sec, 4138260 t fired, .
52 EXEF EXCL 110/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 117918 m, 1066 m/sec, 131011 t fired, .
53 EF FNDP 1118/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1126998 t fired, 12283 attempts, .
54 EF STEQ 1118/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1157 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 115/212 28/32 DoubleLock-PT-p1s2-CTLFireability-12 4324022 m, 37152 m/sec, 4324021 t fired, .
52 EXEF EXCL 115/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 123295 m, 1075 m/sec, 136985 t fired, .
53 EF FNDP 1123/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1131469 t fired, 12337 attempts, .
54 EF STEQ 1123/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1162 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 120/212 29/32 DoubleLock-PT-p1s2-CTLFireability-12 4511603 m, 37516 m/sec, 4511602 t fired, .
52 EXEF EXCL 120/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 128474 m, 1035 m/sec, 142740 t fired, .
53 EF FNDP 1128/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1135956 t fired, 12391 attempts, .
54 EF STEQ 1128/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1167 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 125/212 30/32 DoubleLock-PT-p1s2-CTLFireability-12 4694867 m, 36652 m/sec, 4694867 t fired, .
52 EXEF EXCL 125/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 133448 m, 994 m/sec, 148267 t fired, .
53 EF FNDP 1133/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1140169 t fired, 12442 attempts, .
54 EF STEQ 1133/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1172 secs. Pages in use: 44
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 130/212 31/32 DoubleLock-PT-p1s2-CTLFireability-12 4881259 m, 37278 m/sec, 4881258 t fired, .
52 EXEF EXCL 130/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 138705 m, 1051 m/sec, 154107 t fired, .
53 EF FNDP 1138/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1144548 t fired, 12496 attempts, .
54 EF STEQ 1138/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1177 secs. Pages in use: 45
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 41 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 135/196 1/5 DoubleLock-PT-p1s2-CTLFireability-02 144254 m, 1109 m/sec, 160274 t fired, .
53 EF FNDP 1143/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1149073 t fired, 12544 attempts, .
54 EF STEQ 1143/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1182 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 140/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 150896 m, 1328 m/sec, 167654 t fired, .
53 EF FNDP 1148/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1154674 t fired, 12609 attempts, .
54 EF STEQ 1148/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1187 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 145/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 157529 m, 1326 m/sec, 175023 t fired, .
53 EF FNDP 1153/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1160338 t fired, 12673 attempts, .
54 EF STEQ 1153/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1192 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 150/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 164159 m, 1326 m/sec, 182390 t fired, .
53 EF FNDP 1158/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1165993 t fired, 12738 attempts, .
54 EF STEQ 1158/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1197 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 155/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 170789 m, 1326 m/sec, 189756 t fired, .
53 EF FNDP 1163/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1171614 t fired, 12808 attempts, .
54 EF STEQ 1163/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1202 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 160/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 177425 m, 1327 m/sec, 197130 t fired, .
53 EF FNDP 1168/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1177291 t fired, 12873 attempts, .
54 EF STEQ 1168/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1207 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 165/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 184127 m, 1340 m/sec, 204576 t fired, .
53 EF FNDP 1173/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1182889 t fired, 12940 attempts, .
54 EF STEQ 1173/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1212 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 170/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 190802 m, 1335 m/sec, 211994 t fired, .
53 EF FNDP 1178/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1188561 t fired, 13008 attempts, .
54 EF STEQ 1178/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1217 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 175/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 197436 m, 1326 m/sec, 219364 t fired, .
53 EF FNDP 1183/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1194176 t fired, 13078 attempts, .
54 EF STEQ 1183/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1222 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 180/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 204064 m, 1325 m/sec, 226729 t fired, .
53 EF FNDP 1188/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1199781 t fired, 13142 attempts, .
54 EF STEQ 1188/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1227 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 185/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 210692 m, 1325 m/sec, 234093 t fired, .
53 EF FNDP 1193/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1205417 t fired, 13209 attempts, .
54 EF STEQ 1193/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1232 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 190/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 217325 m, 1326 m/sec, 241463 t fired, .
53 EF FNDP 1198/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1211052 t fired, 13280 attempts, .
54 EF STEQ 1198/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1237 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 195/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 223957 m, 1326 m/sec, 248833 t fired, .
53 EF FNDP 1203/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1216716 t fired, 13347 attempts, .
54 EF STEQ 1203/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1242 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 200/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 230588 m, 1326 m/sec, 256200 t fired, .
53 EF FNDP 1208/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1222378 t fired, 13413 attempts, .
54 EF STEQ 1208/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1247 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 205/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 237222 m, 1326 m/sec, 263571 t fired, .
53 EF FNDP 1213/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1228007 t fired, 13480 attempts, .
54 EF STEQ 1213/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1252 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 210/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 243853 m, 1326 m/sec, 270939 t fired, .
53 EF FNDP 1218/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1233694 t fired, 13548 attempts, .
54 EF STEQ 1218/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1257 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-02 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 2 1 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 1223/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1239313 t fired, 13614 attempts, .
54 EF STEQ 1223/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1262 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 35 (type EXCL) for 34 DoubleLock-PT-p1s2-CTLFireability-10
lola: time limit : 212 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 52 (type EXCL) for 6 DoubleLock-PT-p1s2-CTLFireability-02
lola: time limit : 2338 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 5/212 1/32 DoubleLock-PT-p1s2-CTLFireability-10 155125 m, 31025 m/sec, 155124 t fired, .
52 EXEF EXCL 5/2338 1/5 DoubleLock-PT-p1s2-CTLFireability-02 5387 m, -47693 m/sec, 5976 t fired, .
53 EF FNDP 1228/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1243877 t fired, 13670 attempts, .
54 EF STEQ 1228/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1267 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 10/212 2/32 DoubleLock-PT-p1s2-CTLFireability-10 311504 m, 31275 m/sec, 311503 t fired, .
52 EXEF EXCL 10/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 10813 m, 1085 m/sec, 12005 t fired, .
53 EF FNDP 1233/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1248046 t fired, 13719 attempts, .
54 EF STEQ 1233/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1272 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 15/212 4/32 DoubleLock-PT-p1s2-CTLFireability-10 479857 m, 33670 m/sec, 479856 t fired, .
52 EXEF EXCL 15/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 16337 m, 1104 m/sec, 18143 t fired, .
53 EF FNDP 1238/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1252082 t fired, 13769 attempts, .
54 EF STEQ 1238/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1277 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 20/212 5/32 DoubleLock-PT-p1s2-CTLFireability-10 644734 m, 32975 m/sec, 644733 t fired, .
52 EXEF EXCL 20/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 21894 m, 1111 m/sec, 24318 t fired, .
53 EF FNDP 1243/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1256385 t fired, 13824 attempts, .
54 EF STEQ 1243/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1282 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 25/212 6/32 DoubleLock-PT-p1s2-CTLFireability-10 809977 m, 33048 m/sec, 809976 t fired, .
52 EXEF EXCL 25/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 27363 m, 1093 m/sec, 30394 t fired, .
53 EF FNDP 1248/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1260707 t fired, 13877 attempts, .
54 EF STEQ 1248/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1287 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 30/212 7/32 DoubleLock-PT-p1s2-CTLFireability-10 970689 m, 32142 m/sec, 970688 t fired, .
52 EXEF EXCL 30/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 32616 m, 1050 m/sec, 36231 t fired, .
53 EF FNDP 1253/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1265063 t fired, 13930 attempts, .
54 EF STEQ 1253/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1292 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 35/212 8/32 DoubleLock-PT-p1s2-CTLFireability-10 1133871 m, 32636 m/sec, 1133870 t fired, .
52 EXEF EXCL 35/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 38020 m, 1080 m/sec, 42235 t fired, .
53 EF FNDP 1258/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1269467 t fired, 13981 attempts, .
54 EF STEQ 1258/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1297 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 40/212 9/32 DoubleLock-PT-p1s2-CTLFireability-10 1298460 m, 32917 m/sec, 1298460 t fired, .
52 EXEF EXCL 40/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 43307 m, 1057 m/sec, 48110 t fired, .
53 EF FNDP 1263/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1273813 t fired, 14032 attempts, .
54 EF STEQ 1263/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1302 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 45/212 10/32 DoubleLock-PT-p1s2-CTLFireability-10 1463810 m, 33070 m/sec, 1463810 t fired, .
52 EXEF EXCL 45/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 48730 m, 1084 m/sec, 54136 t fired, .
53 EF FNDP 1268/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1278281 t fired, 14088 attempts, .
54 EF STEQ 1268/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1307 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 50/212 11/32 DoubleLock-PT-p1s2-CTLFireability-10 1631674 m, 33572 m/sec, 1631673 t fired, .
52 EXEF EXCL 50/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 54193 m, 1092 m/sec, 60205 t fired, .
53 EF FNDP 1273/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1282743 t fired, 14141 attempts, .
54 EF STEQ 1273/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1312 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 55/212 12/32 DoubleLock-PT-p1s2-CTLFireability-10 1794872 m, 32639 m/sec, 1794871 t fired, .
52 EXEF EXCL 55/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 59658 m, 1093 m/sec, 66277 t fired, .
53 EF FNDP 1278/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1287035 t fired, 14189 attempts, .
54 EF STEQ 1278/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1317 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 60/212 13/32 DoubleLock-PT-p1s2-CTLFireability-10 1964436 m, 33912 m/sec, 1964435 t fired, .
52 EXEF EXCL 60/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 64720 m, 1012 m/sec, 71902 t fired, .
53 EF FNDP 1283/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1291248 t fired, 14235 attempts, .
54 EF STEQ 1283/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1322 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 65/212 14/32 DoubleLock-PT-p1s2-CTLFireability-10 2128825 m, 32877 m/sec, 2128824 t fired, .
52 EXEF EXCL 65/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 70177 m, 1091 m/sec, 77965 t fired, .
53 EF FNDP 1288/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1295609 t fired, 14289 attempts, .
54 EF STEQ 1288/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1327 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 70/212 15/32 DoubleLock-PT-p1s2-CTLFireability-10 2288710 m, 31977 m/sec, 2288709 t fired, .
52 EXEF EXCL 70/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 75799 m, 1124 m/sec, 84212 t fired, .
53 EF FNDP 1293/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1299665 t fired, 14336 attempts, .
54 EF STEQ 1293/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1332 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 75/212 16/32 DoubleLock-PT-p1s2-CTLFireability-10 2444781 m, 31214 m/sec, 2444780 t fired, .
52 EXEF EXCL 75/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 81297 m, 1099 m/sec, 90321 t fired, .
53 EF FNDP 1298/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1304105 t fired, 14385 attempts, .
54 EF STEQ 1298/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1337 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 80/212 17/32 DoubleLock-PT-p1s2-CTLFireability-10 2608836 m, 32811 m/sec, 2608835 t fired, .
52 EXEF EXCL 80/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 86528 m, 1046 m/sec, 96134 t fired, .
53 EF FNDP 1303/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1308172 t fired, 14433 attempts, .
54 EF STEQ 1303/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1342 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 85/212 18/32 DoubleLock-PT-p1s2-CTLFireability-10 2770105 m, 32253 m/sec, 2770105 t fired, .
52 EXEF EXCL 85/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 91705 m, 1035 m/sec, 101885 t fired, .
53 EF FNDP 1308/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1312444 t fired, 14484 attempts, .
54 EF STEQ 1308/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1347 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 90/212 19/32 DoubleLock-PT-p1s2-CTLFireability-10 2926992 m, 31377 m/sec, 2926991 t fired, .
52 EXEF EXCL 90/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 97112 m, 1081 m/sec, 107894 t fired, .
53 EF FNDP 1313/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1316777 t fired, 14537 attempts, .
54 EF STEQ 1313/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1352 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 95/212 20/32 DoubleLock-PT-p1s2-CTLFireability-10 3089914 m, 32584 m/sec, 3089913 t fired, .
52 EXEF EXCL 95/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 102817 m, 1141 m/sec, 114232 t fired, .
53 EF FNDP 1318/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1320703 t fired, 14581 attempts, .
54 EF STEQ 1318/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1357 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 100/212 21/32 DoubleLock-PT-p1s2-CTLFireability-10 3242132 m, 30443 m/sec, 3242131 t fired, .
52 EXEF EXCL 100/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 108125 m, 1061 m/sec, 120130 t fired, .
53 EF FNDP 1323/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1325155 t fired, 14634 attempts, .
54 EF STEQ 1323/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1362 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 105/212 22/32 DoubleLock-PT-p1s2-CTLFireability-10 3402516 m, 32076 m/sec, 3402516 t fired, .
52 EXEF EXCL 105/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 113547 m, 1084 m/sec, 126154 t fired, .
53 EF FNDP 1328/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1329448 t fired, 14688 attempts, .
54 EF STEQ 1328/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1367 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 110/212 23/32 DoubleLock-PT-p1s2-CTLFireability-10 3565942 m, 32685 m/sec, 3565941 t fired, .
52 EXEF EXCL 110/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 118933 m, 1077 m/sec, 132139 t fired, .
53 EF FNDP 1333/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1333692 t fired, 14740 attempts, .
54 EF STEQ 1333/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1372 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 115/212 24/32 DoubleLock-PT-p1s2-CTLFireability-10 3733700 m, 33551 m/sec, 3733699 t fired, .
52 EXEF EXCL 115/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 124351 m, 1083 m/sec, 138159 t fired, .
53 EF FNDP 1338/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1338026 t fired, 14792 attempts, .
54 EF STEQ 1338/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1377 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 120/212 25/32 DoubleLock-PT-p1s2-CTLFireability-10 3892402 m, 31740 m/sec, 3892401 t fired, .
52 EXEF EXCL 120/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 129794 m, 1088 m/sec, 144206 t fired, .
53 EF FNDP 1343/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1342674 t fired, 14844 attempts, .
54 EF STEQ 1343/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1382 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 125/212 26/32 DoubleLock-PT-p1s2-CTLFireability-10 4054109 m, 32341 m/sec, 4054108 t fired, .
52 EXEF EXCL 125/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 135118 m, 1064 m/sec, 150122 t fired, .
53 EF FNDP 1348/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1347217 t fired, 14897 attempts, .
54 EF STEQ 1348/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1387 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 130/212 27/32 DoubleLock-PT-p1s2-CTLFireability-10 4218216 m, 32821 m/sec, 4218215 t fired, .
52 EXEF EXCL 130/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 140635 m, 1103 m/sec, 156253 t fired, .
53 EF FNDP 1353/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1351637 t fired, 14950 attempts, .
54 EF STEQ 1353/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1392 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 135/212 28/32 DoubleLock-PT-p1s2-CTLFireability-10 4373586 m, 31074 m/sec, 4373585 t fired, .
52 EXEF EXCL 135/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 146009 m, 1074 m/sec, 162224 t fired, .
53 EF FNDP 1358/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1355870 t fired, 14999 attempts, .
54 EF STEQ 1358/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1397 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 140/212 29/32 DoubleLock-PT-p1s2-CTLFireability-10 4526075 m, 30497 m/sec, 4526074 t fired, .
52 EXEF EXCL 140/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 151441 m, 1086 m/sec, 168259 t fired, .
53 EF FNDP 1363/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1360127 t fired, 15049 attempts, .
54 EF STEQ 1363/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1402 secs. Pages in use: 47
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 145/212 30/32 DoubleLock-PT-p1s2-CTLFireability-10 4685903 m, 31965 m/sec, 4685902 t fired, .
52 EXEF EXCL 145/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 156864 m, 1084 m/sec, 174285 t fired, .
53 EF FNDP 1368/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1364520 t fired, 15101 attempts, .
54 EF STEQ 1368/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1407 secs. Pages in use: 48
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 150/212 31/32 DoubleLock-PT-p1s2-CTLFireability-10 4842892 m, 31397 m/sec, 4842891 t fired, .
52 EXEF EXCL 150/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 162502 m, 1127 m/sec, 180549 t fired, .
53 EF FNDP 1373/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1368877 t fired, 15151 attempts, .
54 EF STEQ 1373/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1412 secs. Pages in use: 49
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 155/212 32/32 DoubleLock-PT-p1s2-CTLFireability-10 5008457 m, 33113 m/sec, 5008456 t fired, .
52 EXEF EXCL 155/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 167685 m, 1036 m/sec, 186307 t fired, .
53 EF FNDP 1378/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1373222 t fired, 15202 attempts, .
54 EF STEQ 1378/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1417 secs. Pages in use: 50
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 35 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 160/194 1/5 DoubleLock-PT-p1s2-CTLFireability-02 174008 m, 1264 m/sec, 193334 t fired, .
53 EF FNDP 1383/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1378461 t fired, 15264 attempts, .
54 EF STEQ 1383/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1422 secs. Pages in use: 50
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 165/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 180676 m, 1333 m/sec, 200743 t fired, .
53 EF FNDP 1388/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1384014 t fired, 15329 attempts, .
54 EF STEQ 1388/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1427 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 170/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 187340 m, 1332 m/sec, 208146 t fired, .
53 EF FNDP 1393/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1389588 t fired, 15396 attempts, .
54 EF STEQ 1393/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1432 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 175/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 194010 m, 1334 m/sec, 215557 t fired, .
53 EF FNDP 1398/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1395125 t fired, 15462 attempts, .
54 EF STEQ 1398/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1437 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 180/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 200680 m, 1334 m/sec, 222969 t fired, .
53 EF FNDP 1403/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1400694 t fired, 15527 attempts, .
54 EF STEQ 1403/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1442 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 185/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 207343 m, 1332 m/sec, 230372 t fired, .
53 EF FNDP 1408/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1406194 t fired, 15593 attempts, .
54 EF STEQ 1408/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1447 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 190/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 214009 m, 1333 m/sec, 237778 t fired, .
53 EF FNDP 1413/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1411765 t fired, 15661 attempts, .
54 EF STEQ 1413/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1452 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 195/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 220672 m, 1332 m/sec, 245182 t fired, .
53 EF FNDP 1418/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1417294 t fired, 15721 attempts, .
54 EF STEQ 1418/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1457 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 200/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 227343 m, 1334 m/sec, 252594 t fired, .
53 EF FNDP 1423/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1422877 t fired, 15787 attempts, .
54 EF STEQ 1423/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1462 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 205/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 234014 m, 1334 m/sec, 260006 t fired, .
53 EF FNDP 1428/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1428445 t fired, 15855 attempts, .
54 EF STEQ 1428/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1467 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 210/212 2/5 DoubleLock-PT-p1s2-CTLFireability-02 240681 m, 1333 m/sec, 267414 t fired, .
53 EF FNDP 1433/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1434016 t fired, 15922 attempts, .
54 EF STEQ 1433/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1472 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-02 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 0 0 2 1 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 1438/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1439577 t fired, 15986 attempts, .
54 EF STEQ 1438/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1477 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 32 (type EXCL) for 31 DoubleLock-PT-p1s2-CTLFireability-09
lola: time limit : 212 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 52 (type EXCL) for 6 DoubleLock-PT-p1s2-CTLFireability-02
lola: time limit : 2123 sec
lola: memory limit: 5 pages
lola: FINISHED task # 32 (type EXCL) for DoubleLock-PT-p1s2-CTLFireability-09
lola: result : false
lola: markings : 131
lola: fired transitions : 261
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 5/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 6634 m, -46809 m/sec, 7363 t fired, .
53 EF FNDP 1443/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1445088 t fired, 16056 attempts, .
54 EF STEQ 1443/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1482 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 10/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 13195 m, 1312 m/sec, 14653 t fired, .
53 EF FNDP 1448/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1450619 t fired, 16123 attempts, .
54 EF STEQ 1448/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1487 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 15/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 19628 m, 1286 m/sec, 21800 t fired, .
53 EF FNDP 1453/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1456112 t fired, 16187 attempts, .
54 EF STEQ 1453/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1492 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 20/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 26188 m, 1312 m/sec, 29089 t fired, .
53 EF FNDP 1458/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1461477 t fired, 16252 attempts, .
54 EF STEQ 1458/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1497 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 25/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 32686 m, 1299 m/sec, 36309 t fired, .
53 EF FNDP 1463/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1466755 t fired, 16314 attempts, .
54 EF STEQ 1463/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1502 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 30/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 39256 m, 1314 m/sec, 43609 t fired, .
53 EF FNDP 1468/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1472002 t fired, 16373 attempts, .
54 EF STEQ 1468/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1507 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 35/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 45697 m, 1288 m/sec, 50765 t fired, .
53 EF FNDP 1473/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1477281 t fired, 16437 attempts, .
54 EF STEQ 1473/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1512 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 40/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 52174 m, 1295 m/sec, 57962 t fired, .
53 EF FNDP 1478/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1482519 t fired, 16501 attempts, .
54 EF STEQ 1478/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1517 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 45/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 58757 m, 1316 m/sec, 65276 t fired, .
53 EF FNDP 1483/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1487777 t fired, 16564 attempts, .
54 EF STEQ 1483/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1522 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 50/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 65278 m, 1304 m/sec, 72523 t fired, .
53 EF FNDP 1488/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1493115 t fired, 16628 attempts, .
54 EF STEQ 1488/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1527 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 55/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 71878 m, 1320 m/sec, 79855 t fired, .
53 EF FNDP 1493/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1498479 t fired, 16691 attempts, .
54 EF STEQ 1493/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1532 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 60/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 78474 m, 1319 m/sec, 87184 t fired, .
53 EF FNDP 1498/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1503749 t fired, 16753 attempts, .
54 EF STEQ 1498/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1537 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 65/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 85072 m, 1319 m/sec, 94516 t fired, .
53 EF FNDP 1503/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1509041 t fired, 16815 attempts, .
54 EF STEQ 1503/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1542 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 70/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 91670 m, 1319 m/sec, 101846 t fired, .
53 EF FNDP 1508/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1514290 t fired, 16877 attempts, .
54 EF STEQ 1508/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1547 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 75/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 98258 m, 1317 m/sec, 109166 t fired, .
53 EF FNDP 1513/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1519558 t fired, 16940 attempts, .
54 EF STEQ 1513/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1552 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 80/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 104861 m, 1320 m/sec, 116504 t fired, .
53 EF FNDP 1518/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1524832 t fired, 17002 attempts, .
54 EF STEQ 1518/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1557 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EXEF EXCL 85/212 1/5 DoubleLock-PT-p1s2-CTLFireability-02 111457 m, 1319 m/sec, 123832 t fired, .
53 EF FNDP 1523/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 1530119 t fired, 17062 attempts, .
54 EF STEQ 1523/3561 0/5 DoubleLock-PT-p1s2-CTLFireability-11 sara is running.

Time elapsed: 1562 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s2-CTLFireability-09: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DoubleLock-PT-p1s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s2-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-11: EF 0 1 2 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p1s2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p1s2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r134-smll-167819412900514"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p1s2.tgz
mv DoubleLock-PT-p1s2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;