fond

jQuery Multi Level CSS Menu Css3Menu.com

Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r103-tall-167814478800790
Last Updated
May 14, 2023

About the Execution of LoLa+red for DLCround-PT-13b

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2937.340 232121.00 600838.00 280.10 TTTTTTTFFTFTFTFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478800790.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-13b, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478800790
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.5M
-rw-r--r-- 1 mcc users 6.3K Feb 25 18:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Feb 25 18:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 25 18:45 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 18:45 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 18:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Feb 25 18:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 18:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 18:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 2.1M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-13b-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1678279837979

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-13b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 12:50:39] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-08 12:50:39] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 12:50:39] [INFO ] Load time of PNML (sax parser for PT used): 240 ms
[2023-03-08 12:50:39] [INFO ] Transformed 5343 places.
[2023-03-08 12:50:39] [INFO ] Transformed 8727 transitions.
[2023-03-08 12:50:39] [INFO ] Found NUPN structural information;
[2023-03-08 12:50:40] [INFO ] Parsed PT model containing 5343 places and 8727 transitions and 24849 arcs in 601 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 22 ms.
Working with output stream class java.io.PrintStream
FORMULA DLCround-PT-13b-ReachabilityCardinality-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-13b-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-13b-ReachabilityCardinality-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 431 ms. (steps per millisecond=23 ) properties (out of 13) seen :4
FORMULA DLCround-PT-13b-ReachabilityCardinality-14 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-13b-ReachabilityCardinality-12 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-13b-ReachabilityCardinality-08 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-13b-ReachabilityCardinality-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 9) seen :0
Running SMT prover for 9 properties.
// Phase 1: matrix 8727 rows 5343 cols
[2023-03-08 12:50:41] [INFO ] Computed 312 place invariants in 73 ms
[2023-03-08 12:50:42] [INFO ] After 1518ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:9
[2023-03-08 12:50:44] [INFO ] [Nat]Absence check using 312 positive place invariants in 339 ms returned sat
[2023-03-08 12:50:51] [INFO ] After 6650ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :9
[2023-03-08 12:50:53] [INFO ] Deduced a trap composed of 271 places in 1251 ms of which 8 ms to minimize.
[2023-03-08 12:50:54] [INFO ] Deduced a trap composed of 171 places in 1037 ms of which 2 ms to minimize.
[2023-03-08 12:50:54] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 3149 ms
[2023-03-08 12:50:58] [INFO ] Deduced a trap composed of 190 places in 2123 ms of which 3 ms to minimize.
[2023-03-08 12:51:01] [INFO ] Deduced a trap composed of 301 places in 2137 ms of which 3 ms to minimize.
[2023-03-08 12:51:03] [INFO ] Deduced a trap composed of 269 places in 2075 ms of which 3 ms to minimize.
[2023-03-08 12:51:05] [INFO ] Deduced a trap composed of 153 places in 1900 ms of which 3 ms to minimize.
[2023-03-08 12:51:07] [INFO ] Deduced a trap composed of 278 places in 1890 ms of which 3 ms to minimize.
[2023-03-08 12:51:13] [INFO ] Deduced a trap composed of 12 places in 5186 ms of which 5 ms to minimize.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineWithTraps(DeadlockTester.java:1255)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineResultsWithTraps(DeadlockTester.java:736)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:656)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:902)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-08 12:51:13] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-08 12:51:13] [INFO ] After 30260ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:9
FORMULA DLCround-PT-13b-ReachabilityCardinality-13 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-13b-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-13b-ReachabilityCardinality-04 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-13b-ReachabilityCardinality-01 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-13b-ReachabilityCardinality-15 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 5 properties in 850 ms.
Support contains 81 out of 5343 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 5343/5343 places, 8727/8727 transitions.
Graph (trivial) has 4728 edges and 5343 vertex of which 778 / 5343 are part of one of the 60 SCC in 23 ms
Free SCC test removed 718 places
Drop transitions removed 804 transitions
Reduce isomorphic transitions removed 804 transitions.
Drop transitions removed 1829 transitions
Trivial Post-agglo rules discarded 1829 transitions
Performed 1829 trivial Post agglomeration. Transition count delta: 1829
Iterating post reduction 0 with 1829 rules applied. Total rules applied 1830 place count 4625 transition count 6094
Reduce places removed 1829 places and 0 transitions.
Ensure Unique test removed 51 transitions
Reduce isomorphic transitions removed 51 transitions.
Drop transitions removed 37 transitions
Trivial Post-agglo rules discarded 37 transitions
Performed 37 trivial Post agglomeration. Transition count delta: 37
Iterating post reduction 1 with 1917 rules applied. Total rules applied 3747 place count 2796 transition count 6006
Reduce places removed 37 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 2 with 44 rules applied. Total rules applied 3791 place count 2759 transition count 5999
Reduce places removed 3 places and 0 transitions.
Performed 35 Post agglomeration using F-continuation condition.Transition count delta: 35
Iterating post reduction 3 with 38 rules applied. Total rules applied 3829 place count 2756 transition count 5964
Reduce places removed 35 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 4 with 37 rules applied. Total rules applied 3866 place count 2721 transition count 5962
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 3867 place count 2720 transition count 5962
Performed 38 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 38 Pre rules applied. Total rules applied 3867 place count 2720 transition count 5924
Deduced a syphon composed of 38 places in 40 ms
Reduce places removed 38 places and 0 transitions.
Iterating global reduction 6 with 76 rules applied. Total rules applied 3943 place count 2682 transition count 5924
Discarding 698 places :
Symmetric choice reduction at 6 with 698 rule applications. Total rules 4641 place count 1984 transition count 5226
Iterating global reduction 6 with 698 rules applied. Total rules applied 5339 place count 1984 transition count 5226
Performed 293 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 293 Pre rules applied. Total rules applied 5339 place count 1984 transition count 4933
Deduced a syphon composed of 293 places in 37 ms
Reduce places removed 293 places and 0 transitions.
Iterating global reduction 6 with 586 rules applied. Total rules applied 5925 place count 1691 transition count 4933
Discarding 87 places :
Symmetric choice reduction at 6 with 87 rule applications. Total rules 6012 place count 1604 transition count 3469
Iterating global reduction 6 with 87 rules applied. Total rules applied 6099 place count 1604 transition count 3469
Ensure Unique test removed 25 transitions
Reduce isomorphic transitions removed 25 transitions.
Iterating post reduction 6 with 25 rules applied. Total rules applied 6124 place count 1604 transition count 3444
Performed 413 Post agglomeration using F-continuation condition with reduction of 10 identical transitions.
Deduced a syphon composed of 413 places in 3 ms
Reduce places removed 413 places and 0 transitions.
Iterating global reduction 7 with 826 rules applied. Total rules applied 6950 place count 1191 transition count 3021
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 7 with 13 rules applied. Total rules applied 6963 place count 1191 transition count 3008
Discarding 3 places :
Symmetric choice reduction at 8 with 3 rule applications. Total rules 6966 place count 1188 transition count 2957
Iterating global reduction 8 with 3 rules applied. Total rules applied 6969 place count 1188 transition count 2957
Performed 67 Post agglomeration using F-continuation condition.Transition count delta: -551
Deduced a syphon composed of 67 places in 2 ms
Reduce places removed 67 places and 0 transitions.
Iterating global reduction 8 with 134 rules applied. Total rules applied 7103 place count 1121 transition count 3508
Drop transitions removed 66 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 68 transitions.
Iterating post reduction 8 with 68 rules applied. Total rules applied 7171 place count 1121 transition count 3440
Discarding 2 places :
Symmetric choice reduction at 9 with 2 rule applications. Total rules 7173 place count 1119 transition count 3378
Iterating global reduction 9 with 2 rules applied. Total rules applied 7175 place count 1119 transition count 3378
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 9 with 2 rules applied. Total rules applied 7177 place count 1119 transition count 3376
Drop transitions removed 85 transitions
Redundant transition composition rules discarded 85 transitions
Iterating global reduction 10 with 85 rules applied. Total rules applied 7262 place count 1119 transition count 3291
Discarding 18 places :
Symmetric choice reduction at 10 with 18 rule applications. Total rules 7280 place count 1101 transition count 3273
Iterating global reduction 10 with 18 rules applied. Total rules applied 7298 place count 1101 transition count 3273
Discarding 18 places :
Symmetric choice reduction at 10 with 18 rule applications. Total rules 7316 place count 1083 transition count 2916
Iterating global reduction 10 with 18 rules applied. Total rules applied 7334 place count 1083 transition count 2916
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 10 with 18 rules applied. Total rules applied 7352 place count 1083 transition count 2898
Performed 15 Post agglomeration using F-continuation condition.Transition count delta: 15
Deduced a syphon composed of 15 places in 2 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 11 with 30 rules applied. Total rules applied 7382 place count 1068 transition count 2883
Discarding 14 places :
Symmetric choice reduction at 11 with 14 rule applications. Total rules 7396 place count 1054 transition count 2603
Iterating global reduction 11 with 14 rules applied. Total rules applied 7410 place count 1054 transition count 2603
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 11 with 13 rules applied. Total rules applied 7423 place count 1054 transition count 2590
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -14
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 12 with 4 rules applied. Total rules applied 7427 place count 1052 transition count 2604
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 12 with 2 rules applied. Total rules applied 7429 place count 1052 transition count 2602
Drop transitions removed 15 transitions
Redundant transition composition rules discarded 15 transitions
Iterating global reduction 13 with 15 rules applied. Total rules applied 7444 place count 1052 transition count 2587
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -14
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 13 with 4 rules applied. Total rules applied 7448 place count 1050 transition count 2601
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 13 with 2 rules applied. Total rules applied 7450 place count 1050 transition count 2599
Drop transitions removed 14 transitions
Redundant transition composition rules discarded 14 transitions
Iterating global reduction 14 with 14 rules applied. Total rules applied 7464 place count 1050 transition count 2585
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -14
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 14 with 4 rules applied. Total rules applied 7468 place count 1048 transition count 2599
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 14 with 2 rules applied. Total rules applied 7470 place count 1048 transition count 2597
Drop transitions removed 14 transitions
Redundant transition composition rules discarded 14 transitions
Iterating global reduction 15 with 14 rules applied. Total rules applied 7484 place count 1048 transition count 2583
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 15 with 4 rules applied. Total rules applied 7488 place count 1046 transition count 2600
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 15 with 2 rules applied. Total rules applied 7490 place count 1046 transition count 2598
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 16 with 10 rules applied. Total rules applied 7500 place count 1046 transition count 2588
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -12
Deduced a syphon composed of 1 places in 3 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 16 with 2 rules applied. Total rules applied 7502 place count 1045 transition count 2600
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 16 with 1 rules applied. Total rules applied 7503 place count 1045 transition count 2599
Free-agglomeration rule applied 496 times with reduction of 190 identical transitions.
Iterating global reduction 17 with 496 rules applied. Total rules applied 7999 place count 1045 transition count 1913
Reduce places removed 496 places and 0 transitions.
Drop transitions removed 649 transitions
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 659 transitions.
Graph (complete) has 1592 edges and 549 vertex of which 492 are kept as prefixes of interest. Removing 57 places using SCC suffix rule.1 ms
Discarding 57 places :
Also discarding 0 output transitions
Iterating post reduction 17 with 1156 rules applied. Total rules applied 9155 place count 492 transition count 1254
Drop transitions removed 24 transitions
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 41 transitions.
Iterating post reduction 18 with 41 rules applied. Total rules applied 9196 place count 492 transition count 1213
Discarding 101 places :
Symmetric choice reduction at 19 with 101 rule applications. Total rules 9297 place count 391 transition count 1031
Iterating global reduction 19 with 101 rules applied. Total rules applied 9398 place count 391 transition count 1031
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -12
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 19 with 2 rules applied. Total rules applied 9400 place count 390 transition count 1043
Drop transitions removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 19 with 7 rules applied. Total rules applied 9407 place count 390 transition count 1036
Drop transitions removed 120 transitions
Redundant transition composition rules discarded 120 transitions
Iterating global reduction 20 with 120 rules applied. Total rules applied 9527 place count 390 transition count 916
Reduce places removed 1 places and 0 transitions.
Graph (complete) has 1163 edges and 389 vertex of which 385 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.1 ms
Discarding 4 places :
Also discarding 0 output transitions
Iterating post reduction 20 with 2 rules applied. Total rules applied 9529 place count 385 transition count 916
Drop transitions removed 4 transitions
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 21 with 9 rules applied. Total rules applied 9538 place count 385 transition count 907
Discarding 6 places :
Symmetric choice reduction at 22 with 6 rule applications. Total rules 9544 place count 379 transition count 896
Iterating global reduction 22 with 6 rules applied. Total rules applied 9550 place count 379 transition count 896
Free-agglomeration rule applied 2 times.
Iterating global reduction 22 with 2 rules applied. Total rules applied 9552 place count 379 transition count 894
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 22 with 2 rules applied. Total rules applied 9554 place count 377 transition count 894
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 23 with 1 rules applied. Total rules applied 9555 place count 377 transition count 902
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 23 with 9 rules applied. Total rules applied 9564 place count 376 transition count 894
Partial Free-agglomeration rule applied 4 times.
Drop transitions removed 4 transitions
Iterating global reduction 24 with 4 rules applied. Total rules applied 9568 place count 376 transition count 894
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 24 with 2 rules applied. Total rules applied 9570 place count 376 transition count 892
Applied a total of 9570 rules in 2120 ms. Remains 376 /5343 variables (removed 4967) and now considering 892/8727 (removed 7835) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2121 ms. Remains : 376/5343 places, 892/8727 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 90 ms. (steps per millisecond=111 ) properties (out of 4) seen :3
FORMULA DLCround-PT-13b-ReachabilityCardinality-07 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-13b-ReachabilityCardinality-03 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-13b-ReachabilityCardinality-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-08 12:51:16] [INFO ] Flow matrix only has 610 transitions (discarded 282 similar events)
// Phase 1: matrix 610 rows 376 cols
[2023-03-08 12:51:16] [INFO ] Computed 157 place invariants in 13 ms
[2023-03-08 12:51:16] [INFO ] After 49ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 12:51:16] [INFO ] [Nat]Absence check using 157 positive place invariants in 25 ms returned sat
[2023-03-08 12:51:16] [INFO ] After 165ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 12:51:16] [INFO ] State equation strengthened by 148 read => feed constraints.
[2023-03-08 12:51:16] [INFO ] After 55ms SMT Verify possible using 148 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-08 12:51:16] [INFO ] After 98ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 34 ms.
[2023-03-08 12:51:16] [INFO ] After 385ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 6 ms.
Support contains 16 out of 376 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 376/376 places, 892/892 transitions.
Graph (trivial) has 143 edges and 376 vertex of which 10 / 376 are part of one of the 4 SCC in 1 ms
Free SCC test removed 6 places
Drop transitions removed 12 transitions
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 20 transitions.
Graph (complete) has 1102 edges and 370 vertex of which 347 are kept as prefixes of interest. Removing 23 places using SCC suffix rule.0 ms
Discarding 23 places :
Also discarding 17 output transitions
Drop transitions removed 17 transitions
Drop transitions removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded 12 transitions
Performed 12 trivial Post agglomeration. Transition count delta: 12
Iterating post reduction 0 with 20 rules applied. Total rules applied 22 place count 347 transition count 835
Reduce places removed 12 places and 0 transitions.
Iterating post reduction 1 with 12 rules applied. Total rules applied 34 place count 335 transition count 835
Performed 14 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 14 Pre rules applied. Total rules applied 34 place count 335 transition count 821
Deduced a syphon composed of 14 places in 1 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 2 with 28 rules applied. Total rules applied 62 place count 321 transition count 821
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 64 place count 321 transition count 819
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 71 place count 314 transition count 808
Iterating global reduction 3 with 7 rules applied. Total rules applied 78 place count 314 transition count 808
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 3 with 18 rules applied. Total rules applied 96 place count 314 transition count 790
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 97 place count 313 transition count 789
Iterating global reduction 4 with 1 rules applied. Total rules applied 98 place count 313 transition count 789
Performed 29 Post agglomeration using F-continuation condition with reduction of 2 identical transitions.
Deduced a syphon composed of 29 places in 0 ms
Reduce places removed 29 places and 0 transitions.
Iterating global reduction 4 with 58 rules applied. Total rules applied 156 place count 284 transition count 758
Drop transitions removed 95 transitions
Ensure Unique test removed 27 transitions
Reduce isomorphic transitions removed 122 transitions.
Graph (complete) has 822 edges and 284 vertex of which 274 are kept as prefixes of interest. Removing 10 places using SCC suffix rule.0 ms
Discarding 10 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 123 rules applied. Total rules applied 279 place count 274 transition count 636
Drop transitions removed 4 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 5 with 6 rules applied. Total rules applied 285 place count 274 transition count 630
Discarding 25 places :
Symmetric choice reduction at 6 with 25 rule applications. Total rules 310 place count 249 transition count 597
Iterating global reduction 6 with 25 rules applied. Total rules applied 335 place count 249 transition count 597
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: -68
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 6 with 20 rules applied. Total rules applied 355 place count 239 transition count 665
Drop transitions removed 40 transitions
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 45 transitions.
Iterating post reduction 6 with 45 rules applied. Total rules applied 400 place count 239 transition count 620
Renaming transitions due to excessive name length > 1024 char.
Discarding 1 places :
Symmetric choice reduction at 7 with 1 rule applications. Total rules 401 place count 238 transition count 599
Iterating global reduction 7 with 1 rules applied. Total rules applied 402 place count 238 transition count 599
Drop transitions removed 37 transitions
Redundant transition composition rules discarded 37 transitions
Iterating global reduction 7 with 37 rules applied. Total rules applied 439 place count 238 transition count 562
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 440 place count 237 transition count 562
Discarding 2 places :
Symmetric choice reduction at 8 with 2 rule applications. Total rules 442 place count 235 transition count 548
Iterating global reduction 8 with 2 rules applied. Total rules applied 444 place count 235 transition count 548
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 8 with 10 rules applied. Total rules applied 454 place count 235 transition count 538
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -20
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 9 with 4 rules applied. Total rules applied 458 place count 233 transition count 558
Drop transitions removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 9 with 12 rules applied. Total rules applied 470 place count 233 transition count 546
Drop transitions removed 8 transitions
Redundant transition composition rules discarded 8 transitions
Iterating global reduction 10 with 8 rules applied. Total rules applied 478 place count 233 transition count 538
Free-agglomeration rule applied 10 times with reduction of 1 identical transitions.
Iterating global reduction 10 with 10 rules applied. Total rules applied 488 place count 233 transition count 527
Reduce places removed 10 places and 0 transitions.
Drop transitions removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 10 with 29 rules applied. Total rules applied 517 place count 223 transition count 508
Discarding 3 places :
Symmetric choice reduction at 11 with 3 rule applications. Total rules 520 place count 220 transition count 505
Iterating global reduction 11 with 3 rules applied. Total rules applied 523 place count 220 transition count 505
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 525 place count 219 transition count 504
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 11 with 5 rules applied. Total rules applied 530 place count 219 transition count 499
Partial Free-agglomeration rule applied 5 times.
Drop transitions removed 5 transitions
Iterating global reduction 12 with 5 rules applied. Total rules applied 535 place count 219 transition count 499
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 12 with 5 rules applied. Total rules applied 540 place count 219 transition count 494
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 12 with 10 rules applied. Total rules applied 550 place count 214 transition count 489
Applied a total of 550 rules in 118 ms. Remains 214 /376 variables (removed 162) and now considering 489/892 (removed 403) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 118 ms. Remains : 214/376 places, 489/892 transitions.
Finished random walk after 255 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=127 )
FORMULA DLCround-PT-13b-ReachabilityCardinality-11 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
All properties solved without resorting to model-checking.
Total runtime 37324 ms.
starting LoLA
BK_INPUT DLCround-PT-13b
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA DLCround-PT-13b-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678280070100

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
DLCround-PT-13b-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
DLCround-PT-13b-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
DLCround-PT-13b-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
DLCround-PT-13b-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 75 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 62 (type EXCL) for 6 DLCround-PT-13b-ReachabilityCardinality-02
lola: time limit : 195 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 58 (type FNDP) for 6 DLCround-PT-13b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 6 DLCround-PT-13b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SRCH) for 6 DLCround-PT-13b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 58 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 59 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 61 (type SRCH) for DLCround-PT-13b-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 62 (type EXCL) for DLCround-PT-13b-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 66 (type EXCL) for 12 DLCround-PT-13b-ReachabilityCardinality-04
lola: time limit : 207 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 15 DLCround-PT-13b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type FNDP) for 42 DLCround-PT-13b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 42 DLCround-PT-13b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 48 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-05
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 50 (type FNDP) for 30 DLCround-PT-13b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 56 (type FNDP) for 12 DLCround-PT-13b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-54.sara.memory pages used : 0

sara: place or transition ordering is non-deterministic

lola: CANCELED task # 54 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 57 (type EQUN) for 12 DLCround-PT-13b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type SRCH) for 12 DLCround-PT-13b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-59.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 59 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-02
lola: result : true
lola: FINISHED task # 54 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-14
lola: result : true
lola: FINISHED task # 56 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-04
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 57 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 65 (type SRCH) for DLCround-PT-13b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 66 (type EXCL) for DLCround-PT-13b-ReachabilityCardinality-04 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-57.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 57 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-04
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 110 (type EXCL) for 33 DLCround-PT-13b-ReachabilityCardinality-11
lola: time limit : 440 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 106 (type FNDP) for 33 DLCround-PT-13b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 107 (type EQUN) for 33 DLCround-PT-13b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 109 (type SRCH) for 33 DLCround-PT-13b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 109 (type SRCH) for DLCround-PT-13b-ReachabilityCardinality-11
lola: result : true
lola: markings : 20
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 106 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 107 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 110 (type EXCL) for DLCround-PT-13b-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 121 (type EXCL) for 39 DLCround-PT-13b-ReachabilityCardinality-13
lola: time limit : 352 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 90 (type FNDP) for 36 DLCround-PT-13b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 96 (type EQUN) for 36 DLCround-PT-13b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 114 (type SRCH) for 36 DLCround-PT-13b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 106 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 18
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 90 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 96 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 114 (type SRCH) for DLCround-PT-13b-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 105 (type FNDP) for 27 DLCround-PT-13b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 112 (type EQUN) for 27 DLCround-PT-13b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 126 (type SRCH) for 27 DLCround-PT-13b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 121 (type EXCL) for DLCround-PT-13b-ReachabilityCardinality-13
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 123 (type EXCL) for 24 DLCround-PT-13b-ReachabilityCardinality-08
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: time limit : 440 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-96.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-107.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 96 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-12
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-112.sara.
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 3 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 1/319 0/5 DLCround-PT-13b-ReachabilityCardinality-09 143701 t fired, 1 attempts, .
112 EF STEQ 1/319 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 1/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 1540 m, 308 m/sec, 2645 t fired, .
126 EF SRCH 1/351 1/5 DLCround-PT-13b-ReachabilityCardinality-09 64115 m, 12823 m/sec, 103039 t fired, .

Time elapsed: 80 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 3 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 6/319 0/5 DLCround-PT-13b-ReachabilityCardinality-09 914456 t fired, 1 attempts, .
112 EF STEQ 6/319 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 6/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 12145 m, 2121 m/sec, 22245 t fired, .
126 EF SRCH 6/351 3/5 DLCround-PT-13b-ReachabilityCardinality-09 536031 m, 94383 m/sec, 882018 t fired, .

Time elapsed: 85 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 3 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 11/314 0/5 DLCround-PT-13b-ReachabilityCardinality-09 1657326 t fired, 2 attempts, .
112 EF STEQ 11/314 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 11/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 22517 m, 2074 m/sec, 41243 t fired, .
126 EF SRCH 11/346 5/5 DLCround-PT-13b-ReachabilityCardinality-09 993149 m, 91423 m/sec, 1674016 t fired, .

Time elapsed: 90 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 126 (type SRCH) for DLCround-PT-13b-ReachabilityCardinality-09 (memory limit exceeded)

lola: FINISHED task # 107 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-11
lola: result : true
lola: LAUNCH task # 144 (type FNDP) for 0 DLCround-PT-13b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 16/337 0/5 DLCround-PT-13b-ReachabilityCardinality-09 2129177 t fired, 3 attempts, .
112 EF STEQ 16/337 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 16/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 35020 m, 2500 m/sec, 64346 t fired, .
144 EF FNDP 1/318 0/5 DLCround-PT-13b-ReachabilityCardinality-00 131801 t fired, 1 attempts, .

Time elapsed: 95 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 21/336 0/5 DLCround-PT-13b-ReachabilityCardinality-09 2348021 t fired, 3 attempts, .
112 EF STEQ 21/336 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 21/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 47784 m, 2552 m/sec, 88274 t fired, .
144 EF FNDP 6/317 0/5 DLCround-PT-13b-ReachabilityCardinality-00 948187 t fired, 1 attempts, .

Time elapsed: 100 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 26/331 0/5 DLCround-PT-13b-ReachabilityCardinality-09 2535326 t fired, 3 attempts, .
112 EF STEQ 26/331 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 26/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 60559 m, 2555 m/sec, 112505 t fired, .
144 EF FNDP 11/312 0/5 DLCround-PT-13b-ReachabilityCardinality-00 1542501 t fired, 2 attempts, .

Time elapsed: 105 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 31/326 0/5 DLCround-PT-13b-ReachabilityCardinality-09 2723987 t fired, 3 attempts, .
112 EF STEQ 31/326 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 31/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 73284 m, 2545 m/sec, 136605 t fired, .
144 EF FNDP 16/307 0/5 DLCround-PT-13b-ReachabilityCardinality-00 2045991 t fired, 3 attempts, .

Time elapsed: 110 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 36/321 0/5 DLCround-PT-13b-ReachabilityCardinality-09 2904827 t fired, 3 attempts, .
112 EF STEQ 36/321 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 36/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 85968 m, 2536 m/sec, 160610 t fired, .
144 EF FNDP 21/302 0/5 DLCround-PT-13b-ReachabilityCardinality-00 2534571 t fired, 3 attempts, .

Time elapsed: 115 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 41/316 0/5 DLCround-PT-13b-ReachabilityCardinality-09 3110985 t fired, 4 attempts, .
112 EF STEQ 41/316 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 41/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 98660 m, 2538 m/sec, 184527 t fired, .
144 EF FNDP 26/297 0/5 DLCround-PT-13b-ReachabilityCardinality-00 3002240 t fired, 4 attempts, .

Time elapsed: 120 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 46/311 0/5 DLCround-PT-13b-ReachabilityCardinality-09 3287056 t fired, 4 attempts, .
112 EF STEQ 46/311 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 46/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 111356 m, 2539 m/sec, 208510 t fired, .
144 EF FNDP 31/292 0/5 DLCround-PT-13b-ReachabilityCardinality-00 3454432 t fired, 4 attempts, .

Time elapsed: 125 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 51/306 0/5 DLCround-PT-13b-ReachabilityCardinality-09 3454280 t fired, 4 attempts, .
112 EF STEQ 51/306 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 51/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 124066 m, 2542 m/sec, 232521 t fired, .
144 EF FNDP 36/287 0/5 DLCround-PT-13b-ReachabilityCardinality-00 3875420 t fired, 4 attempts, .

Time elapsed: 130 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 56/301 0/5 DLCround-PT-13b-ReachabilityCardinality-09 3618709 t fired, 4 attempts, .
112 EF STEQ 56/301 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 56/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 136719 m, 2530 m/sec, 256646 t fired, .
144 EF FNDP 41/282 0/5 DLCround-PT-13b-ReachabilityCardinality-00 4278311 t fired, 5 attempts, .

Time elapsed: 135 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 61/296 0/5 DLCround-PT-13b-ReachabilityCardinality-09 3781698 t fired, 4 attempts, .
112 EF STEQ 61/296 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 61/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 149369 m, 2530 m/sec, 280629 t fired, .
144 EF FNDP 46/277 0/5 DLCround-PT-13b-ReachabilityCardinality-00 4671137 t fired, 5 attempts, .

Time elapsed: 140 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 66/291 0/5 DLCround-PT-13b-ReachabilityCardinality-09 3940233 t fired, 4 attempts, .
112 EF STEQ 66/291 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 66/440 1/32 DLCround-PT-13b-ReachabilityCardinality-08 162126 m, 2551 m/sec, 304434 t fired, .
144 EF FNDP 51/272 0/5 DLCround-PT-13b-ReachabilityCardinality-00 5056703 t fired, 6 attempts, .

Time elapsed: 145 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 71/286 0/5 DLCround-PT-13b-ReachabilityCardinality-09 4102576 t fired, 5 attempts, .
112 EF STEQ 71/286 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 71/440 2/32 DLCround-PT-13b-ReachabilityCardinality-08 174993 m, 2573 m/sec, 328050 t fired, .
144 EF FNDP 56/267 0/5 DLCround-PT-13b-ReachabilityCardinality-00 5421603 t fired, 6 attempts, .

Time elapsed: 150 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 76/281 0/5 DLCround-PT-13b-ReachabilityCardinality-09 4259005 t fired, 5 attempts, .
112 EF STEQ 76/281 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 76/440 2/32 DLCround-PT-13b-ReachabilityCardinality-08 187759 m, 2553 m/sec, 351835 t fired, .
144 EF FNDP 61/262 0/5 DLCround-PT-13b-ReachabilityCardinality-00 5766620 t fired, 6 attempts, .

Time elapsed: 155 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 81/276 0/5 DLCround-PT-13b-ReachabilityCardinality-09 4413214 t fired, 5 attempts, .
112 EF STEQ 81/276 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 81/440 2/32 DLCround-PT-13b-ReachabilityCardinality-08 200444 m, 2537 m/sec, 375984 t fired, .
144 EF FNDP 66/257 0/5 DLCround-PT-13b-ReachabilityCardinality-00 6103243 t fired, 7 attempts, .

Time elapsed: 160 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 86/271 0/5 DLCround-PT-13b-ReachabilityCardinality-09 4561881 t fired, 5 attempts, .
112 EF STEQ 86/271 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 86/440 2/32 DLCround-PT-13b-ReachabilityCardinality-08 213140 m, 2539 m/sec, 399953 t fired, .
144 EF FNDP 71/252 0/5 DLCround-PT-13b-ReachabilityCardinality-00 6435708 t fired, 7 attempts, .

Time elapsed: 165 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 91/266 0/5 DLCround-PT-13b-ReachabilityCardinality-09 4706001 t fired, 5 attempts, .
112 EF STEQ 91/266 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 91/440 2/32 DLCround-PT-13b-ReachabilityCardinality-08 225752 m, 2522 m/sec, 424206 t fired, .
144 EF FNDP 76/247 0/5 DLCround-PT-13b-ReachabilityCardinality-00 6761561 t fired, 7 attempts, .

Time elapsed: 170 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 96/261 0/5 DLCround-PT-13b-ReachabilityCardinality-09 4846426 t fired, 5 attempts, .
112 EF STEQ 96/261 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 96/440 2/32 DLCround-PT-13b-ReachabilityCardinality-08 238514 m, 2552 m/sec, 448017 t fired, .
144 EF FNDP 81/242 0/5 DLCround-PT-13b-ReachabilityCardinality-00 7078785 t fired, 8 attempts, .

Time elapsed: 175 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-09: AG 0 2 2 0 1 0 1 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
105 EF FNDP 101/256 0/5 DLCround-PT-13b-ReachabilityCardinality-09 4986600 t fired, 5 attempts, .
112 EF STEQ 101/256 0/5 DLCround-PT-13b-ReachabilityCardinality-09 sara is running.
123 EF EXCL 101/440 2/32 DLCround-PT-13b-ReachabilityCardinality-08 251248 m, 2546 m/sec, 471801 t fired, .
144 EF FNDP 86/237 0/5 DLCround-PT-13b-ReachabilityCardinality-00 7389380 t fired, 8 attempts, .

Time elapsed: 180 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16

lola: FINISHED task # 112 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-09
lola: result : false
lola: CANCELED task # 105 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 95 (type FNDP) for 21 DLCround-PT-13b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 124 (type EQUN) for 21 DLCround-PT-13b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 105 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-09
lola: result : unknown
lola: fired transitions : 5001802
lola: tried executions : 7
lola: time used : 102.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 95 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 192
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 124 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 82 (type FNDP) for 9 DLCround-PT-13b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type EQUN) for 9 DLCround-PT-13b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 82 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-03
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 83 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 140 (type FNDP) for 3 DLCround-PT-13b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 142 (type EQUN) for 3 DLCround-PT-13b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 140 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 453
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 142 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 102 (type FNDP) for 18 DLCround-PT-13b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type EQUN) for 18 DLCround-PT-13b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-142.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-83.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-116.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-124.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-03: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-07: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-09: AG true state equation
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-06: AG 0 3 2 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
102 EF FNDP 4/569 0/5 DLCround-PT-13b-ReachabilityCardinality-06 448932 t fired, 1 attempts, .
116 EF STEQ 4/683 0/5 DLCround-PT-13b-ReachabilityCardinality-06 sara is running.
123 EF EXCL 106/880 2/32 DLCround-PT-13b-ReachabilityCardinality-08 258994 m, 1549 m/sec, 486315 t fired, .
144 EF FNDP 91/614 0/5 DLCround-PT-13b-ReachabilityCardinality-00 7573496 t fired, 8 attempts, .

Time elapsed: 185 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16

lola: FINISHED task # 116 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-06
lola: result : false
lola: CANCELED task # 102 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 92 (type FNDP) for 45 DLCround-PT-13b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type EQUN) for 45 DLCround-PT-13b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 102 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-06
lola: result : unknown
lola: fired transitions : 892627
lola: tried executions : 2
lola: time used : 8.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 92 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-15
lola: result : true
lola: fired transitions : 5
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 103 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 145 (type EQUN) for 0 DLCround-PT-13b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 149 (type SRCH) for 0 DLCround-PT-13b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-103.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-145.sara.

sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-03: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-06: AG true state equation
DLCround-PT-13b-ReachabilityCardinality-07: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-09: AG true state equation
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-ReachabilityCardinality-00: AG 0 2 3 0 1 0 0 0
DLCround-PT-13b-ReachabilityCardinality-08: AG 0 4 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
123 EF EXCL 111/1760 2/32 DLCround-PT-13b-ReachabilityCardinality-08 265704 m, 1342 m/sec, 499053 t fired, .
144 EF FNDP 96/1658 0/5 DLCround-PT-13b-ReachabilityCardinality-00 7728990 t fired, 8 attempts, .
145 EF STEQ 1/1137 0/5 DLCround-PT-13b-ReachabilityCardinality-00 sara is running.
149 EF SRCH 1/1137 1/5 DLCround-PT-13b-ReachabilityCardinality-00 56431 m, 11286 m/sec, 121305 t fired, .

Time elapsed: 190 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 142 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-01
lola: result : true
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 145 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-00
lola: result : false
lola: CANCELED task # 144 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 149 (type SRCH) for DLCround-PT-13b-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 89 (type FNDP) for 24 DLCround-PT-13b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 98 (type EQUN) for 24 DLCround-PT-13b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 122 (type SRCH) for 24 DLCround-PT-13b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 144 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-00
lola: result : unknown
lola: fired transitions : 7797307
lola: tried executions : 9
lola: time used : 98.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 122 (type SRCH) for DLCround-PT-13b-ReachabilityCardinality-08
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 89 (type FNDP) for DLCround-PT-13b-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 98 (type EQUN) for DLCround-PT-13b-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 123 (type EXCL) for DLCround-PT-13b-ReachabilityCardinality-08 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-ReachabilityCardinality-00: AG true state equation
DLCround-PT-13b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-02: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-03: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-05: EF true findpath
DLCround-PT-13b-ReachabilityCardinality-06: AG true state equation
DLCround-PT-13b-ReachabilityCardinality-07: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-08: AG false tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-09: AG true state equation
DLCround-PT-13b-ReachabilityCardinality-10: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-11: EF true tandem / insertion
DLCround-PT-13b-ReachabilityCardinality-12: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-13: EF true tandem / relaxed
DLCround-PT-13b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-13b-ReachabilityCardinality-15: AG false findpath


Time elapsed: 192 secs. Pages in use: 6

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-13b"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-13b, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478800790"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-13b.tgz
mv DLCround-PT-13b execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;