Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478700730.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-10a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478700730
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.3K Feb 25 19:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 25 19:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 25 19:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 25 19:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 20:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 114K Feb 25 20:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 25 20:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 115K Feb 25 20:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 660K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-10a-CTLFireability-00
FORMULA_NAME DLCround-PT-10a-CTLFireability-01
FORMULA_NAME DLCround-PT-10a-CTLFireability-02
FORMULA_NAME DLCround-PT-10a-CTLFireability-03
FORMULA_NAME DLCround-PT-10a-CTLFireability-04
FORMULA_NAME DLCround-PT-10a-CTLFireability-05
FORMULA_NAME DLCround-PT-10a-CTLFireability-06
FORMULA_NAME DLCround-PT-10a-CTLFireability-07
FORMULA_NAME DLCround-PT-10a-CTLFireability-08
FORMULA_NAME DLCround-PT-10a-CTLFireability-09
FORMULA_NAME DLCround-PT-10a-CTLFireability-10
FORMULA_NAME DLCround-PT-10a-CTLFireability-11
FORMULA_NAME DLCround-PT-10a-CTLFireability-12
FORMULA_NAME DLCround-PT-10a-CTLFireability-13
FORMULA_NAME DLCround-PT-10a-CTLFireability-14
FORMULA_NAME DLCround-PT-10a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678277482586

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-10a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 12:11:24] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 12:11:24] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 12:11:24] [INFO ] Load time of PNML (sax parser for PT used): 127 ms
[2023-03-08 12:11:24] [INFO ] Transformed 337 places.
[2023-03-08 12:11:24] [INFO ] Transformed 2605 transitions.
[2023-03-08 12:11:24] [INFO ] Found NUPN structural information;
[2023-03-08 12:11:24] [INFO ] Parsed PT model containing 337 places and 2605 transitions and 10130 arcs in 205 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 1 formulas.
Ensure Unique test removed 247 transitions
Reduce redundant transitions removed 247 transitions.
FORMULA DLCround-PT-10a-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 133 out of 337 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 337/337 places, 2358/2358 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 323 transition count 2150
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 323 transition count 2150
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 29 place count 323 transition count 2149
Drop transitions removed 718 transitions
Redundant transition composition rules discarded 718 transitions
Iterating global reduction 1 with 718 rules applied. Total rules applied 747 place count 323 transition count 1431
Applied a total of 747 rules in 97 ms. Remains 323 /337 variables (removed 14) and now considering 1431/2358 (removed 927) transitions.
[2023-03-08 12:11:24] [INFO ] Flow matrix only has 203 transitions (discarded 1228 similar events)
// Phase 1: matrix 203 rows 323 cols
[2023-03-08 12:11:24] [INFO ] Computed 213 place invariants in 14 ms
[2023-03-08 12:11:25] [INFO ] Implicit Places using invariants in 792 ms returned [125, 129, 130, 132, 133, 135, 136, 137, 139, 140, 141, 144, 147, 148, 149, 150, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 163, 165, 166, 167, 169, 170, 172, 173, 174, 175, 178, 181, 182, 183, 184, 185, 187, 189, 191, 194, 195, 197, 199, 201, 202, 203, 205, 206, 208, 210, 211, 213, 214, 215, 218, 220, 222, 223, 224, 226, 227, 229, 233, 235, 236, 237, 239, 241, 242, 247, 248, 249, 250, 251, 254, 255, 259, 261, 263, 268, 269, 273, 275, 276, 277, 278, 281, 282, 283, 285, 286, 287, 288, 289, 291, 293, 295, 296, 298, 299, 300, 303, 305, 306, 307, 308, 309, 310, 312, 313, 315, 316, 317, 318, 319, 320, 322]
Discarding 123 places :
Ensure Unique test removed 665 transitions
Reduce isomorphic transitions removed 665 transitions.
Implicit Place search using SMT only with invariants took 828 ms to find 123 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 200/337 places, 766/2358 transitions.
Drop transitions removed 496 transitions
Redundant transition composition rules discarded 496 transitions
Iterating global reduction 0 with 496 rules applied. Total rules applied 496 place count 200 transition count 270
Applied a total of 496 rules in 12 ms. Remains 200 /200 variables (removed 0) and now considering 270/766 (removed 496) transitions.
[2023-03-08 12:11:25] [INFO ] Flow matrix only has 203 transitions (discarded 67 similar events)
// Phase 1: matrix 203 rows 200 cols
[2023-03-08 12:11:25] [INFO ] Computed 90 place invariants in 2 ms
[2023-03-08 12:11:25] [INFO ] Implicit Places using invariants in 68 ms returned []
[2023-03-08 12:11:25] [INFO ] Flow matrix only has 203 transitions (discarded 67 similar events)
[2023-03-08 12:11:25] [INFO ] Invariant cache hit.
[2023-03-08 12:11:25] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-08 12:11:25] [INFO ] Implicit Places using invariants and state equation in 134 ms returned []
Implicit Place search using SMT with State Equation took 204 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 200/337 places, 270/2358 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 1143 ms. Remains : 200/337 places, 270/2358 transitions.
Support contains 133 out of 200 places after structural reductions.
[2023-03-08 12:11:25] [INFO ] Flatten gal took : 38 ms
[2023-03-08 12:11:25] [INFO ] Flatten gal took : 29 ms
[2023-03-08 12:11:25] [INFO ] Input system was already deterministic with 270 transitions.
Support contains 131 out of 200 places (down from 133) after GAL structural reductions.
Finished random walk after 1337 steps, including 0 resets, run visited all 71 properties in 72 ms. (steps per millisecond=18 )
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 17 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 29 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 270 transitions.
Computed a total of 76 stabilizing places and 1 stable transitions
Graph (complete) has 359 edges and 200 vertex of which 125 are kept as prefixes of interest. Removing 75 places using SCC suffix rule.3 ms
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 72 places and 0 transitions.
Iterating post reduction 0 with 72 rules applied. Total rules applied 72 place count 128 transition count 270
Discarding 15 places :
Symmetric choice reduction at 1 with 15 rule applications. Total rules 87 place count 113 transition count 240
Iterating global reduction 1 with 15 rules applied. Total rules applied 102 place count 113 transition count 240
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 105 place count 113 transition count 237
Applied a total of 105 rules in 6 ms. Remains 113 /200 variables (removed 87) and now considering 237/270 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 113/200 places, 237/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 237 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Graph (trivial) has 246 edges and 200 vertex of which 109 / 200 are part of one of the 14 SCC in 2 ms
Free SCC test removed 95 places
Ensure Unique test removed 221 transitions
Reduce isomorphic transitions removed 221 transitions.
Graph (complete) has 138 edges and 105 vertex of which 34 are kept as prefixes of interest. Removing 71 places using SCC suffix rule.0 ms
Discarding 71 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 34 transition count 48
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 2 rules applied. Total rules applied 5 place count 33 transition count 47
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 6 place count 32 transition count 47
Discarding 10 places :
Symmetric choice reduction at 3 with 10 rule applications. Total rules 16 place count 22 transition count 36
Iterating global reduction 3 with 10 rules applied. Total rules applied 26 place count 22 transition count 36
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 28 place count 22 transition count 34
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 30 place count 21 transition count 33
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 5 with 2 rules applied. Total rules applied 32 place count 21 transition count 31
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 5 with 1 rules applied. Total rules applied 33 place count 21 transition count 31
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 34 place count 20 transition count 30
Iterating global reduction 5 with 1 rules applied. Total rules applied 35 place count 20 transition count 30
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 36 place count 20 transition count 29
Applied a total of 36 rules in 22 ms. Remains 20 /200 variables (removed 180) and now considering 29/270 (removed 241) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 20/200 places, 29/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 29 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 71 places and 0 transitions.
Iterating post reduction 0 with 71 rules applied. Total rules applied 71 place count 129 transition count 270
Discarding 13 places :
Symmetric choice reduction at 1 with 13 rule applications. Total rules 84 place count 116 transition count 244
Iterating global reduction 1 with 13 rules applied. Total rules applied 97 place count 116 transition count 244
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 99 place count 116 transition count 242
Applied a total of 99 rules in 6 ms. Remains 116 /200 variables (removed 84) and now considering 242/270 (removed 28) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 116/200 places, 242/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 242 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Graph (trivial) has 252 edges and 200 vertex of which 109 / 200 are part of one of the 15 SCC in 1 ms
Free SCC test removed 94 places
Ensure Unique test removed 219 transitions
Reduce isomorphic transitions removed 219 transitions.
Graph (complete) has 140 edges and 106 vertex of which 34 are kept as prefixes of interest. Removing 72 places using SCC suffix rule.1 ms
Discarding 72 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 34 transition count 49
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 32 transition count 49
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 18 place count 20 transition count 36
Iterating global reduction 2 with 12 rules applied. Total rules applied 30 place count 20 transition count 36
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 2 with 3 rules applied. Total rules applied 33 place count 20 transition count 33
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 34 place count 20 transition count 33
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 35 place count 19 transition count 32
Iterating global reduction 2 with 1 rules applied. Total rules applied 36 place count 19 transition count 32
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 37 place count 19 transition count 31
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 38 place count 19 transition count 30
Applied a total of 38 rules in 11 ms. Remains 19 /200 variables (removed 181) and now considering 30/270 (removed 240) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 19/200 places, 30/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Graph (trivial) has 266 edges and 200 vertex of which 123 / 200 are part of one of the 15 SCC in 0 ms
Free SCC test removed 108 places
Ensure Unique test removed 251 transitions
Reduce isomorphic transitions removed 251 transitions.
Graph (complete) has 108 edges and 92 vertex of which 18 are kept as prefixes of interest. Removing 74 places using SCC suffix rule.0 ms
Discarding 74 places :
Also discarding 0 output transitions
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 15 place count 5 transition count 6
Iterating global reduction 0 with 13 rules applied. Total rules applied 28 place count 5 transition count 6
Applied a total of 28 rules in 1 ms. Remains 5 /200 variables (removed 195) and now considering 6/270 (removed 264) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 5/200 places, 6/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 2 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=1 )
FORMULA DLCround-PT-10a-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Graph (trivial) has 267 edges and 200 vertex of which 123 / 200 are part of one of the 15 SCC in 0 ms
Free SCC test removed 108 places
Ensure Unique test removed 252 transitions
Reduce isomorphic transitions removed 252 transitions.
Graph (complete) has 107 edges and 92 vertex of which 18 are kept as prefixes of interest. Removing 74 places using SCC suffix rule.0 ms
Discarding 74 places :
Also discarding 0 output transitions
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 15 place count 5 transition count 5
Iterating global reduction 0 with 13 rules applied. Total rules applied 28 place count 5 transition count 5
Applied a total of 28 rules in 2 ms. Remains 5 /200 variables (removed 195) and now considering 5/270 (removed 265) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 5/200 places, 5/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 72 places and 0 transitions.
Iterating post reduction 0 with 72 rules applied. Total rules applied 72 place count 128 transition count 270
Discarding 15 places :
Symmetric choice reduction at 1 with 15 rule applications. Total rules 87 place count 113 transition count 240
Iterating global reduction 1 with 15 rules applied. Total rules applied 102 place count 113 transition count 240
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 105 place count 113 transition count 237
Applied a total of 105 rules in 19 ms. Remains 113 /200 variables (removed 87) and now considering 237/270 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 19 ms. Remains : 113/200 places, 237/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 10 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 237 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 52 places and 0 transitions.
Iterating post reduction 0 with 52 rules applied. Total rules applied 52 place count 148 transition count 270
Discarding 12 places :
Symmetric choice reduction at 1 with 12 rule applications. Total rules 64 place count 136 transition count 246
Iterating global reduction 1 with 12 rules applied. Total rules applied 76 place count 136 transition count 246
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 78 place count 136 transition count 244
Applied a total of 78 rules in 2 ms. Remains 136 /200 variables (removed 64) and now considering 244/270 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 136/200 places, 244/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 244 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 70 places and 0 transitions.
Iterating post reduction 0 with 70 rules applied. Total rules applied 70 place count 130 transition count 270
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 84 place count 116 transition count 242
Iterating global reduction 1 with 14 rules applied. Total rules applied 98 place count 116 transition count 242
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 101 place count 116 transition count 239
Applied a total of 101 rules in 4 ms. Remains 116 /200 variables (removed 84) and now considering 239/270 (removed 31) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 116/200 places, 239/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 10 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 239 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 72 places and 0 transitions.
Iterating post reduction 0 with 72 rules applied. Total rules applied 72 place count 128 transition count 270
Discarding 15 places :
Symmetric choice reduction at 1 with 15 rule applications. Total rules 87 place count 113 transition count 240
Iterating global reduction 1 with 15 rules applied. Total rules applied 102 place count 113 transition count 240
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 105 place count 113 transition count 237
Applied a total of 105 rules in 10 ms. Remains 113 /200 variables (removed 87) and now considering 237/270 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 113/200 places, 237/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 237 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Graph (trivial) has 249 edges and 200 vertex of which 109 / 200 are part of one of the 15 SCC in 1 ms
Free SCC test removed 94 places
Ensure Unique test removed 220 transitions
Reduce isomorphic transitions removed 220 transitions.
Graph (complete) has 139 edges and 106 vertex of which 34 are kept as prefixes of interest. Removing 72 places using SCC suffix rule.0 ms
Discarding 72 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 34 transition count 49
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 2 rules applied. Total rules applied 5 place count 33 transition count 48
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 6 place count 32 transition count 48
Discarding 12 places :
Symmetric choice reduction at 3 with 12 rule applications. Total rules 18 place count 20 transition count 35
Iterating global reduction 3 with 12 rules applied. Total rules applied 30 place count 20 transition count 35
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 3 with 3 rules applied. Total rules applied 33 place count 20 transition count 32
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 34 place count 20 transition count 32
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 35 place count 19 transition count 31
Iterating global reduction 3 with 1 rules applied. Total rules applied 36 place count 19 transition count 31
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 37 place count 19 transition count 30
Applied a total of 37 rules in 5 ms. Remains 19 /200 variables (removed 181) and now considering 30/270 (removed 240) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 19/200 places, 30/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 66 places and 0 transitions.
Iterating post reduction 0 with 66 rules applied. Total rules applied 66 place count 134 transition count 270
Discarding 12 places :
Symmetric choice reduction at 1 with 12 rule applications. Total rules 78 place count 122 transition count 246
Iterating global reduction 1 with 12 rules applied. Total rules applied 90 place count 122 transition count 246
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 92 place count 122 transition count 244
Applied a total of 92 rules in 2 ms. Remains 122 /200 variables (removed 78) and now considering 244/270 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 122/200 places, 244/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 244 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 68 places and 0 transitions.
Iterating post reduction 0 with 68 rules applied. Total rules applied 68 place count 132 transition count 270
Discarding 13 places :
Symmetric choice reduction at 1 with 13 rule applications. Total rules 81 place count 119 transition count 244
Iterating global reduction 1 with 13 rules applied. Total rules applied 94 place count 119 transition count 244
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 96 place count 119 transition count 242
Applied a total of 96 rules in 4 ms. Remains 119 /200 variables (removed 81) and now considering 242/270 (removed 28) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 119/200 places, 242/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 242 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 75 places and 0 transitions.
Iterating post reduction 0 with 75 rules applied. Total rules applied 75 place count 125 transition count 270
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 91 place count 109 transition count 238
Iterating global reduction 1 with 16 rules applied. Total rules applied 107 place count 109 transition count 238
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 110 place count 109 transition count 235
Applied a total of 110 rules in 3 ms. Remains 109 /200 variables (removed 91) and now considering 235/270 (removed 35) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 109/200 places, 235/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 24 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 235 transitions.
Starting structural reductions in LTL mode, iteration 0 : 200/200 places, 270/270 transitions.
Reduce places removed 58 places and 0 transitions.
Iterating post reduction 0 with 58 rules applied. Total rules applied 58 place count 142 transition count 270
Discarding 13 places :
Symmetric choice reduction at 1 with 13 rule applications. Total rules 71 place count 129 transition count 244
Iterating global reduction 1 with 13 rules applied. Total rules applied 84 place count 129 transition count 244
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 86 place count 129 transition count 242
Applied a total of 86 rules in 3 ms. Remains 129 /200 variables (removed 71) and now considering 242/270 (removed 28) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 129/200 places, 242/270 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 19 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:11:26] [INFO ] Input system was already deterministic with 242 transitions.
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:11:26] [INFO ] Flatten gal took : 16 ms
[2023-03-08 12:11:26] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 7 ms.
[2023-03-08 12:11:27] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 200 places, 270 transitions and 629 arcs took 1 ms.
Total runtime 2745 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCround-PT-10a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA DLCround-PT-10a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-10a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678277694764

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-10a-CTLFireability-01
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 4 (type EXCL) for DLCround-PT-10a-CTLFireability-01
lola: result : false
lola: markings : 241
lola: fired transitions : 12358
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 41 (type EXCL) for 38 DLCround-PT-10a-CTLFireability-11
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 41 (type EXCL) for DLCround-PT-10a-CTLFireability-11
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 38 DLCround-PT-10a-CTLFireability-11
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for DLCround-PT-10a-CTLFireability-11
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 DLCround-PT-10a-CTLFireability-09
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for DLCround-PT-10a-CTLFireability-09
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 DLCround-PT-10a-CTLFireability-06
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 70 (type FNDP) for 31 DLCround-PT-10a-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type EQUN) for 31 DLCround-PT-10a-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SRCH) for 31 DLCround-PT-10a-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 73 (type SRCH) for DLCround-PT-10a-CTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 70 (type FNDP) for DLCround-PT-10a-CTLFireability-10
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 71 (type EQUN) for DLCround-PT-10a-CTLFireability-10 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: try reading problem file /home/mcc/execution/376/CTLFireability-71.sara.

lola: FINISHED task # 71 (type EQUN) for DLCround-PT-10a-CTLFireability-10
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 3 0 0 9 0 0 0
DLCround-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/257 5/32 DLCround-PT-10a-CTLFireability-06 921418 m, 184283 m/sec, 4586610 t fired, .

Time elapsed: 5 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 3 0 0 9 0 0 0
DLCround-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/257 9/32 DLCround-PT-10a-CTLFireability-06 1766979 m, 169112 m/sec, 8889354 t fired, .

Time elapsed: 10 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 3 0 0 9 0 0 0
DLCround-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/257 12/32 DLCround-PT-10a-CTLFireability-06 2593570 m, 165318 m/sec, 13106554 t fired, .

Time elapsed: 15 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 3 0 0 9 0 0 0
DLCround-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/257 16/32 DLCround-PT-10a-CTLFireability-06 3364180 m, 154122 m/sec, 17070493 t fired, .

Time elapsed: 20 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 3 0 0 9 0 0 0
DLCround-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/257 20/32 DLCround-PT-10a-CTLFireability-06 4147248 m, 156613 m/sec, 21100940 t fired, .

Time elapsed: 25 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 3 0 0 9 0 0 0
DLCround-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 30/257 23/32 DLCround-PT-10a-CTLFireability-06 4926616 m, 155873 m/sec, 25128710 t fired, .

Time elapsed: 30 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 3 0 0 9 0 0 0
DLCround-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 35/257 27/32 DLCround-PT-10a-CTLFireability-06 5717374 m, 158151 m/sec, 29165481 t fired, .

Time elapsed: 35 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 3 0 0 9 0 0 0
DLCround-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 40/257 30/32 DLCround-PT-10a-CTLFireability-06 6466390 m, 149803 m/sec, 33051464 t fired, .

Time elapsed: 40 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 16 (type EXCL) for DLCround-PT-10a-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 3 0 0 9 0 0 0
DLCround-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 68 (type EXCL) for 67 DLCround-PT-10a-CTLFireability-14
lola: time limit : 273 sec
lola: memory limit: 32 pages
lola: FINISHED task # 68 (type EXCL) for DLCround-PT-10a-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 65 (type EXCL) for 64 DLCround-PT-10a-CTLFireability-13
lola: time limit : 296 sec
lola: memory limit: 32 pages
lola: FINISHED task # 65 (type EXCL) for DLCround-PT-10a-CTLFireability-13
lola: result : true
lola: markings : 39
lola: fired transitions : 63
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type EXCL) for 61 DLCround-PT-10a-CTLFireability-12
lola: time limit : 323 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for DLCround-PT-10a-CTLFireability-12
lola: result : true
lola: markings : 2
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 38 DLCround-PT-10a-CTLFireability-11
lola: time limit : 355 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for DLCround-PT-10a-CTLFireability-11
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 38 DLCround-PT-10a-CTLFireability-11
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for DLCround-PT-10a-CTLFireability-11
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 21 DLCround-PT-10a-CTLFireability-08
lola: time limit : 444 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for DLCround-PT-10a-CTLFireability-08
lola: result : false
lola: markings : 16072
lola: fired transitions : 57986
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 21 DLCround-PT-10a-CTLFireability-08
lola: time limit : 507 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for DLCround-PT-10a-CTLFireability-08
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 DLCround-PT-10a-CTLFireability-07
lola: time limit : 592 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/592 5/32 DLCround-PT-10a-CTLFireability-07 1137635 m, 227527 m/sec, 4413258 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/592 10/32 DLCround-PT-10a-CTLFireability-07 2177173 m, 207907 m/sec, 8476773 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/592 15/32 DLCround-PT-10a-CTLFireability-07 3235188 m, 211603 m/sec, 12617400 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/592 19/32 DLCround-PT-10a-CTLFireability-07 4236210 m, 200204 m/sec, 16605030 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/592 23/32 DLCround-PT-10a-CTLFireability-07 5198786 m, 192515 m/sec, 20432487 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/592 27/32 DLCround-PT-10a-CTLFireability-07 6139630 m, 188168 m/sec, 24184996 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/592 31/32 DLCround-PT-10a-CTLFireability-07 7054309 m, 182935 m/sec, 27885687 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 19 (type EXCL) for DLCround-PT-10a-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 7 (type EXCL) for 6 DLCround-PT-10a-CTLFireability-02
lola: time limit : 703 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/703 6/32 DLCround-PT-10a-CTLFireability-02 1137604 m, 227520 m/sec, 4382397 t fired, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/703 10/32 DLCround-PT-10a-CTLFireability-02 2159267 m, 204332 m/sec, 8400413 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/703 14/32 DLCround-PT-10a-CTLFireability-02 3084541 m, 185054 m/sec, 12073102 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/703 18/32 DLCround-PT-10a-CTLFireability-02 3897426 m, 162577 m/sec, 15867819 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/703 21/32 DLCround-PT-10a-CTLFireability-02 4496499 m, 119814 m/sec, 19596642 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/703 24/32 DLCround-PT-10a-CTLFireability-02 5252177 m, 151135 m/sec, 23044171 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/703 26/32 DLCround-PT-10a-CTLFireability-02 5713119 m, 92188 m/sec, 26741613 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/703 28/32 DLCround-PT-10a-CTLFireability-02 6147578 m, 86891 m/sec, 30304965 t fired, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/703 31/32 DLCround-PT-10a-CTLFireability-02 6650460 m, 100576 m/sec, 33950750 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 7 (type EXCL) for DLCround-PT-10a-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-10a-CTLFireability-00
lola: time limit : 866 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/866 4/32 DLCround-PT-10a-CTLFireability-00 653725 m, 130745 m/sec, 3676381 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/866 6/32 DLCround-PT-10a-CTLFireability-00 1215115 m, 112278 m/sec, 7035082 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/866 9/32 DLCround-PT-10a-CTLFireability-00 1789276 m, 114832 m/sec, 10314819 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/866 12/32 DLCround-PT-10a-CTLFireability-00 2303572 m, 102859 m/sec, 13572551 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/866 14/32 DLCround-PT-10a-CTLFireability-00 2804998 m, 100285 m/sec, 16651012 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/866 17/32 DLCround-PT-10a-CTLFireability-00 3366168 m, 112234 m/sec, 19981787 t fired, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/866 19/32 DLCround-PT-10a-CTLFireability-00 3824115 m, 91589 m/sec, 23007043 t fired, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/866 21/32 DLCround-PT-10a-CTLFireability-00 4281333 m, 91443 m/sec, 26052213 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/866 23/32 DLCround-PT-10a-CTLFireability-00 4739045 m, 91542 m/sec, 29031886 t fired, .

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/866 25/32 DLCround-PT-10a-CTLFireability-00 5211285 m, 94448 m/sec, 32007981 t fired, .

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/866 27/32 DLCround-PT-10a-CTLFireability-00 5721640 m, 102071 m/sec, 34833449 t fired, .

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 60/866 29/32 DLCround-PT-10a-CTLFireability-00 6176374 m, 90946 m/sec, 37744410 t fired, .

Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 65/866 32/32 DLCround-PT-10a-CTLFireability-00 6664764 m, 97678 m/sec, 40890121 t fired, .

Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 1 (type EXCL) for DLCround-PT-10a-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-10a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-10a-CTLFireability-11: CONJ 0 1 0 0 11 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 13 (type EXCL) for 12 DLCround-PT-10a-CTLFireability-05
lola: time limit : 1131 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for DLCround-PT-10a-CTLFireability-05
lola: result : true
lola: markings : 3
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 38 DLCround-PT-10a-CTLFireability-11
lola: time limit : 1697 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for DLCround-PT-10a-CTLFireability-11
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 DLCround-PT-10a-CTLFireability-03
lola: time limit : 3395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for DLCround-PT-10a-CTLFireability-03
lola: result : false
lola: markings : 121
lola: fired transitions : 2518
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10a-CTLFireability-00: CTL unknown AGGR
DLCround-PT-10a-CTLFireability-01: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-02: CTL unknown AGGR
DLCround-PT-10a-CTLFireability-03: CTL false CTL model checker
DLCround-PT-10a-CTLFireability-05: AGEF true tscc_search
DLCround-PT-10a-CTLFireability-06: CTL unknown AGGR
DLCround-PT-10a-CTLFireability-07: CTL unknown AGGR
DLCround-PT-10a-CTLFireability-08: DISJ true state space /EXEF
DLCround-PT-10a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-10: DISJ true findpath
DLCround-PT-10a-CTLFireability-11: CONJ true CONJ
DLCround-PT-10a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-10a-CTLFireability-14: CTL true CTL model checker


Time elapsed: 205 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-10a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-10a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478700730"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-10a.tgz
mv DLCround-PT-10a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;