About the Execution of LoLa+red for DLCround-PT-07b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 9392.212 | 653058.00 | 662676.00 | 1915.10 | ??FTT?T????F?F?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478600690.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-07b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478600690
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 7.4K Feb 25 18:21 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 25 18:21 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 18:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 25 18:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.3K Feb 25 18:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 93K Feb 25 18:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 18:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 25 18:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 963K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-07b-CTLFireability-00
FORMULA_NAME DLCround-PT-07b-CTLFireability-01
FORMULA_NAME DLCround-PT-07b-CTLFireability-02
FORMULA_NAME DLCround-PT-07b-CTLFireability-03
FORMULA_NAME DLCround-PT-07b-CTLFireability-04
FORMULA_NAME DLCround-PT-07b-CTLFireability-05
FORMULA_NAME DLCround-PT-07b-CTLFireability-06
FORMULA_NAME DLCround-PT-07b-CTLFireability-07
FORMULA_NAME DLCround-PT-07b-CTLFireability-08
FORMULA_NAME DLCround-PT-07b-CTLFireability-09
FORMULA_NAME DLCround-PT-07b-CTLFireability-10
FORMULA_NAME DLCround-PT-07b-CTLFireability-11
FORMULA_NAME DLCround-PT-07b-CTLFireability-12
FORMULA_NAME DLCround-PT-07b-CTLFireability-13
FORMULA_NAME DLCround-PT-07b-CTLFireability-14
FORMULA_NAME DLCround-PT-07b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678274127926
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-07b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 11:15:29] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 11:15:29] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 11:15:29] [INFO ] Load time of PNML (sax parser for PT used): 144 ms
[2023-03-08 11:15:29] [INFO ] Transformed 2703 places.
[2023-03-08 11:15:29] [INFO ] Transformed 4071 transitions.
[2023-03-08 11:15:29] [INFO ] Found NUPN structural information;
[2023-03-08 11:15:29] [INFO ] Parsed PT model containing 2703 places and 4071 transitions and 11073 arcs in 263 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 118 out of 2703 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 2703/2703 places, 4071/4071 transitions.
Discarding 460 places :
Symmetric choice reduction at 0 with 460 rule applications. Total rules 460 place count 2243 transition count 3611
Iterating global reduction 0 with 460 rules applied. Total rules applied 920 place count 2243 transition count 3611
Discarding 346 places :
Symmetric choice reduction at 0 with 346 rule applications. Total rules 1266 place count 1897 transition count 3265
Iterating global reduction 0 with 346 rules applied. Total rules applied 1612 place count 1897 transition count 3265
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 1620 place count 1897 transition count 3257
Discarding 46 places :
Symmetric choice reduction at 1 with 46 rule applications. Total rules 1666 place count 1851 transition count 3177
Iterating global reduction 1 with 46 rules applied. Total rules applied 1712 place count 1851 transition count 3177
Discarding 32 places :
Symmetric choice reduction at 1 with 32 rule applications. Total rules 1744 place count 1819 transition count 3145
Iterating global reduction 1 with 32 rules applied. Total rules applied 1776 place count 1819 transition count 3145
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 1780 place count 1819 transition count 3141
Discarding 16 places :
Symmetric choice reduction at 2 with 16 rule applications. Total rules 1796 place count 1803 transition count 3125
Iterating global reduction 2 with 16 rules applied. Total rules applied 1812 place count 1803 transition count 3125
Discarding 16 places :
Symmetric choice reduction at 2 with 16 rule applications. Total rules 1828 place count 1787 transition count 3109
Iterating global reduction 2 with 16 rules applied. Total rules applied 1844 place count 1787 transition count 3109
Discarding 16 places :
Symmetric choice reduction at 2 with 16 rule applications. Total rules 1860 place count 1771 transition count 3093
Iterating global reduction 2 with 16 rules applied. Total rules applied 1876 place count 1771 transition count 3093
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 1885 place count 1762 transition count 3084
Iterating global reduction 2 with 9 rules applied. Total rules applied 1894 place count 1762 transition count 3084
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 1900 place count 1756 transition count 3078
Iterating global reduction 2 with 6 rules applied. Total rules applied 1906 place count 1756 transition count 3078
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 1912 place count 1750 transition count 3072
Iterating global reduction 2 with 6 rules applied. Total rules applied 1918 place count 1750 transition count 3072
Applied a total of 1918 rules in 1077 ms. Remains 1750 /2703 variables (removed 953) and now considering 3072/4071 (removed 999) transitions.
// Phase 1: matrix 3072 rows 1750 cols
[2023-03-08 11:15:30] [INFO ] Computed 132 place invariants in 48 ms
[2023-03-08 11:15:31] [INFO ] Implicit Places using invariants in 698 ms returned []
[2023-03-08 11:15:31] [INFO ] Invariant cache hit.
[2023-03-08 11:15:32] [INFO ] Implicit Places using invariants and state equation in 1373 ms returned []
Implicit Place search using SMT with State Equation took 2096 ms to find 0 implicit places.
[2023-03-08 11:15:32] [INFO ] Invariant cache hit.
[2023-03-08 11:15:34] [INFO ] Dead Transitions using invariants and state equation in 1243 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1750/2703 places, 3072/4071 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4421 ms. Remains : 1750/2703 places, 3072/4071 transitions.
Support contains 118 out of 1750 places after structural reductions.
[2023-03-08 11:15:34] [INFO ] Flatten gal took : 189 ms
[2023-03-08 11:15:34] [INFO ] Flatten gal took : 100 ms
[2023-03-08 11:15:34] [INFO ] Input system was already deterministic with 3072 transitions.
Support contains 109 out of 1750 places (down from 118) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 474 ms. (steps per millisecond=21 ) properties (out of 63) seen :48
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0
Running SMT prover for 15 properties.
[2023-03-08 11:15:35] [INFO ] Invariant cache hit.
[2023-03-08 11:15:36] [INFO ] [Real]Absence check using 132 positive place invariants in 99 ms returned sat
[2023-03-08 11:15:36] [INFO ] After 783ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:15
[2023-03-08 11:15:36] [INFO ] [Nat]Absence check using 132 positive place invariants in 87 ms returned sat
[2023-03-08 11:15:39] [INFO ] After 1881ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :15
[2023-03-08 11:15:41] [INFO ] After 4003ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :15
Attempting to minimize the solution found.
Minimization took 1096 ms.
[2023-03-08 11:15:42] [INFO ] After 6193ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :15
Fused 15 Parikh solutions to 13 different solutions.
Parikh walk visited 11 properties in 441 ms.
Support contains 7 out of 1750 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Graph (trivial) has 1559 edges and 1750 vertex of which 436 / 1750 are part of one of the 34 SCC in 7 ms
Free SCC test removed 402 places
Drop transitions removed 456 transitions
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 468 transitions.
Drop transitions removed 289 transitions
Trivial Post-agglo rules discarded 289 transitions
Performed 289 trivial Post agglomeration. Transition count delta: 289
Iterating post reduction 0 with 289 rules applied. Total rules applied 290 place count 1348 transition count 2315
Reduce places removed 289 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Drop transitions removed 24 transitions
Trivial Post-agglo rules discarded 24 transitions
Performed 24 trivial Post agglomeration. Transition count delta: 24
Iterating post reduction 1 with 325 rules applied. Total rules applied 615 place count 1059 transition count 2279
Reduce places removed 24 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 25 rules applied. Total rules applied 640 place count 1035 transition count 2278
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 641 place count 1034 transition count 2278
Performed 126 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 126 Pre rules applied. Total rules applied 641 place count 1034 transition count 2152
Deduced a syphon composed of 126 places in 6 ms
Reduce places removed 126 places and 0 transitions.
Iterating global reduction 4 with 252 rules applied. Total rules applied 893 place count 908 transition count 2152
Discarding 81 places :
Symmetric choice reduction at 4 with 81 rule applications. Total rules 974 place count 827 transition count 1763
Iterating global reduction 4 with 81 rules applied. Total rules applied 1055 place count 827 transition count 1763
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 1059 place count 827 transition count 1759
Performed 20 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 20 Pre rules applied. Total rules applied 1059 place count 827 transition count 1739
Deduced a syphon composed of 20 places in 6 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 5 with 40 rules applied. Total rules applied 1099 place count 807 transition count 1739
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 1100 place count 806 transition count 1728
Iterating global reduction 5 with 1 rules applied. Total rules applied 1101 place count 806 transition count 1728
Performed 299 Post agglomeration using F-continuation condition with reduction of 6 identical transitions.
Deduced a syphon composed of 299 places in 0 ms
Reduce places removed 299 places and 0 transitions.
Iterating global reduction 5 with 598 rules applied. Total rules applied 1699 place count 507 transition count 1423
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 5 with 8 rules applied. Total rules applied 1707 place count 507 transition count 1415
Renaming transitions due to excessive name length > 1024 char.
Discarding 27 places :
Symmetric choice reduction at 6 with 27 rule applications. Total rules 1734 place count 480 transition count 1130
Iterating global reduction 6 with 27 rules applied. Total rules applied 1761 place count 480 transition count 1130
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Iterating post reduction 6 with 21 rules applied. Total rules applied 1782 place count 480 transition count 1109
Performed 35 Post agglomeration using F-continuation condition.Transition count delta: -303
Deduced a syphon composed of 35 places in 1 ms
Reduce places removed 35 places and 0 transitions.
Iterating global reduction 7 with 70 rules applied. Total rules applied 1852 place count 445 transition count 1412
Drop transitions removed 13 transitions
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 7 with 17 rules applied. Total rules applied 1869 place count 445 transition count 1395
Discarding 18 places :
Symmetric choice reduction at 8 with 18 rule applications. Total rules 1887 place count 427 transition count 1018
Iterating global reduction 8 with 18 rules applied. Total rules applied 1905 place count 427 transition count 1018
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 8 with 17 rules applied. Total rules applied 1922 place count 427 transition count 1001
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -19
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 9 with 6 rules applied. Total rules applied 1928 place count 424 transition count 1020
Drop transitions removed 109 transitions
Redundant transition composition rules discarded 109 transitions
Iterating global reduction 9 with 109 rules applied. Total rules applied 2037 place count 424 transition count 911
Discarding 8 places :
Symmetric choice reduction at 9 with 8 rule applications. Total rules 2045 place count 416 transition count 822
Iterating global reduction 9 with 8 rules applied. Total rules applied 2053 place count 416 transition count 822
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 9 with 8 rules applied. Total rules applied 2061 place count 416 transition count 814
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -29
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 10 with 8 rules applied. Total rules applied 2069 place count 412 transition count 843
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 10 with 5 rules applied. Total rules applied 2074 place count 412 transition count 838
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 11 with 21 rules applied. Total rules applied 2095 place count 412 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -26
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 11 with 8 rules applied. Total rules applied 2103 place count 408 transition count 843
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 11 with 6 rules applied. Total rules applied 2109 place count 408 transition count 837
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 12 with 20 rules applied. Total rules applied 2129 place count 408 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -27
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 12 with 8 rules applied. Total rules applied 2137 place count 404 transition count 844
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 12 with 6 rules applied. Total rules applied 2143 place count 404 transition count 838
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 13 with 21 rules applied. Total rules applied 2164 place count 404 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -26
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 13 with 8 rules applied. Total rules applied 2172 place count 400 transition count 843
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 13 with 6 rules applied. Total rules applied 2178 place count 400 transition count 837
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 14 with 20 rules applied. Total rules applied 2198 place count 400 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -27
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 14 with 8 rules applied. Total rules applied 2206 place count 396 transition count 844
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 14 with 6 rules applied. Total rules applied 2212 place count 396 transition count 838
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 15 with 21 rules applied. Total rules applied 2233 place count 396 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -26
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 15 with 8 rules applied. Total rules applied 2241 place count 392 transition count 843
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 15 with 6 rules applied. Total rules applied 2247 place count 392 transition count 837
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 16 with 20 rules applied. Total rules applied 2267 place count 392 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -27
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 16 with 8 rules applied. Total rules applied 2275 place count 388 transition count 844
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 16 with 6 rules applied. Total rules applied 2281 place count 388 transition count 838
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 17 with 21 rules applied. Total rules applied 2302 place count 388 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -26
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 17 with 8 rules applied. Total rules applied 2310 place count 384 transition count 843
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 17 with 6 rules applied. Total rules applied 2316 place count 384 transition count 837
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 18 with 20 rules applied. Total rules applied 2336 place count 384 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -27
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 18 with 8 rules applied. Total rules applied 2344 place count 380 transition count 844
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 18 with 6 rules applied. Total rules applied 2350 place count 380 transition count 838
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 19 with 21 rules applied. Total rules applied 2371 place count 380 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -26
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 19 with 8 rules applied. Total rules applied 2379 place count 376 transition count 843
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 19 with 6 rules applied. Total rules applied 2385 place count 376 transition count 837
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 20 with 20 rules applied. Total rules applied 2405 place count 376 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -27
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 20 with 8 rules applied. Total rules applied 2413 place count 372 transition count 844
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 20 with 6 rules applied. Total rules applied 2419 place count 372 transition count 838
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 21 with 21 rules applied. Total rules applied 2440 place count 372 transition count 817
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -32
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 21 with 8 rules applied. Total rules applied 2448 place count 368 transition count 849
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 21 with 6 rules applied. Total rules applied 2454 place count 368 transition count 843
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 22 with 20 rules applied. Total rules applied 2474 place count 368 transition count 823
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -30
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 22 with 8 rules applied. Total rules applied 2482 place count 364 transition count 853
Drop transitions removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 22 with 7 rules applied. Total rules applied 2489 place count 364 transition count 846
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 23 with 20 rules applied. Total rules applied 2509 place count 364 transition count 826
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -29
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 23 with 8 rules applied. Total rules applied 2517 place count 360 transition count 855
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 23 with 5 rules applied. Total rules applied 2522 place count 360 transition count 850
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 24 with 21 rules applied. Total rules applied 2543 place count 360 transition count 829
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -27
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 24 with 8 rules applied. Total rules applied 2551 place count 356 transition count 856
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 24 with 6 rules applied. Total rules applied 2557 place count 356 transition count 850
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 25 with 21 rules applied. Total rules applied 2578 place count 356 transition count 829
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -23
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 25 with 8 rules applied. Total rules applied 2586 place count 352 transition count 852
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 25 with 4 rules applied. Total rules applied 2590 place count 352 transition count 848
Drop transitions removed 19 transitions
Redundant transition composition rules discarded 19 transitions
Iterating global reduction 26 with 19 rules applied. Total rules applied 2609 place count 352 transition count 829
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -22
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 26 with 8 rules applied. Total rules applied 2617 place count 348 transition count 851
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 26 with 4 rules applied. Total rules applied 2621 place count 348 transition count 847
Drop transitions removed 19 transitions
Redundant transition composition rules discarded 19 transitions
Iterating global reduction 27 with 19 rules applied. Total rules applied 2640 place count 348 transition count 828
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -19
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 27 with 8 rules applied. Total rules applied 2648 place count 344 transition count 847
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 27 with 4 rules applied. Total rules applied 2652 place count 344 transition count 843
Drop transitions removed 19 transitions
Redundant transition composition rules discarded 19 transitions
Iterating global reduction 28 with 19 rules applied. Total rules applied 2671 place count 344 transition count 824
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -18
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 28 with 8 rules applied. Total rules applied 2679 place count 340 transition count 842
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 28 with 3 rules applied. Total rules applied 2682 place count 340 transition count 839
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 29 with 17 rules applied. Total rules applied 2699 place count 340 transition count 822
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 29 with 6 rules applied. Total rules applied 2705 place count 337 transition count 839
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 29 with 3 rules applied. Total rules applied 2708 place count 337 transition count 836
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 30 with 17 rules applied. Total rules applied 2725 place count 337 transition count 819
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 30 with 6 rules applied. Total rules applied 2731 place count 334 transition count 836
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 30 with 3 rules applied. Total rules applied 2734 place count 334 transition count 833
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 31 with 17 rules applied. Total rules applied 2751 place count 334 transition count 816
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 31 with 6 rules applied. Total rules applied 2757 place count 331 transition count 833
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 31 with 3 rules applied. Total rules applied 2760 place count 331 transition count 830
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 32 with 17 rules applied. Total rules applied 2777 place count 331 transition count 813
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 32 with 6 rules applied. Total rules applied 2783 place count 328 transition count 830
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 32 with 3 rules applied. Total rules applied 2786 place count 328 transition count 827
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 33 with 17 rules applied. Total rules applied 2803 place count 328 transition count 810
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 33 with 6 rules applied. Total rules applied 2809 place count 325 transition count 827
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 33 with 3 rules applied. Total rules applied 2812 place count 325 transition count 824
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 34 with 17 rules applied. Total rules applied 2829 place count 325 transition count 807
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 34 with 6 rules applied. Total rules applied 2835 place count 322 transition count 824
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 34 with 3 rules applied. Total rules applied 2838 place count 322 transition count 821
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 35 with 17 rules applied. Total rules applied 2855 place count 322 transition count 804
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 35 with 6 rules applied. Total rules applied 2861 place count 319 transition count 821
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 35 with 3 rules applied. Total rules applied 2864 place count 319 transition count 818
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 36 with 17 rules applied. Total rules applied 2881 place count 319 transition count 801
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 36 with 6 rules applied. Total rules applied 2887 place count 316 transition count 818
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 36 with 3 rules applied. Total rules applied 2890 place count 316 transition count 815
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 37 with 17 rules applied. Total rules applied 2907 place count 316 transition count 798
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -20
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 37 with 6 rules applied. Total rules applied 2913 place count 313 transition count 818
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 37 with 3 rules applied. Total rules applied 2916 place count 313 transition count 815
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 38 with 17 rules applied. Total rules applied 2933 place count 313 transition count 798
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -26
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 38 with 6 rules applied. Total rules applied 2939 place count 310 transition count 824
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 38 with 3 rules applied. Total rules applied 2942 place count 310 transition count 821
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 39 with 17 rules applied. Total rules applied 2959 place count 310 transition count 804
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -26
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 39 with 6 rules applied. Total rules applied 2965 place count 307 transition count 830
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 39 with 3 rules applied. Total rules applied 2968 place count 307 transition count 827
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 40 with 17 rules applied. Total rules applied 2985 place count 307 transition count 810
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 40 with 6 rules applied. Total rules applied 2991 place count 304 transition count 827
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 40 with 3 rules applied. Total rules applied 2994 place count 304 transition count 824
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 41 with 17 rules applied. Total rules applied 3011 place count 304 transition count 807
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -17
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 41 with 6 rules applied. Total rules applied 3017 place count 301 transition count 824
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 41 with 3 rules applied. Total rules applied 3020 place count 301 transition count 821
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 42 with 17 rules applied. Total rules applied 3037 place count 301 transition count 804
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -3
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 42 with 2 rules applied. Total rules applied 3039 place count 300 transition count 807
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 42 with 1 rules applied. Total rules applied 3040 place count 300 transition count 806
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 43 with 3 rules applied. Total rules applied 3043 place count 300 transition count 803
Free-agglomeration rule applied 30 times.
Iterating global reduction 43 with 30 rules applied. Total rules applied 3073 place count 300 transition count 773
Reduce places removed 30 places and 0 transitions.
Drop transitions removed 252 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 253 transitions.
Graph (complete) has 807 edges and 270 vertex of which 202 are kept as prefixes of interest. Removing 68 places using SCC suffix rule.1 ms
Discarding 68 places :
Also discarding 0 output transitions
Iterating post reduction 43 with 284 rules applied. Total rules applied 3357 place count 202 transition count 520
Drop transitions removed 68 transitions
Reduce isomorphic transitions removed 68 transitions.
Iterating post reduction 44 with 68 rules applied. Total rules applied 3425 place count 202 transition count 452
Drop transitions removed 45 transitions
Redundant transition composition rules discarded 45 transitions
Iterating global reduction 45 with 45 rules applied. Total rules applied 3470 place count 202 transition count 407
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 45 with 1 rules applied. Total rules applied 3471 place count 201 transition count 406
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 45 with 5 rules applied. Total rules applied 3476 place count 196 transition count 406
Performed 20 Post agglomeration using F-continuation condition.Transition count delta: 20
Deduced a syphon composed of 20 places in 0 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 46 with 60 rules applied. Total rules applied 3536 place count 156 transition count 386
Drop transitions removed 20 transitions
Ensure Unique test removed 36 transitions
Reduce isomorphic transitions removed 56 transitions.
Iterating post reduction 46 with 56 rules applied. Total rules applied 3592 place count 156 transition count 330
Performed 36 Post agglomeration using F-continuation condition.Transition count delta: 36
Deduced a syphon composed of 36 places in 0 ms
Reduce places removed 71 places and 0 transitions.
Iterating global reduction 47 with 107 rules applied. Total rules applied 3699 place count 85 transition count 294
Drop transitions removed 50 transitions
Ensure Unique test removed 57 transitions
Reduce isomorphic transitions removed 107 transitions.
Graph (trivial) has 14 edges and 85 vertex of which 8 / 85 are part of one of the 4 SCC in 0 ms
Free SCC test removed 4 places
Iterating post reduction 47 with 108 rules applied. Total rules applied 3807 place count 81 transition count 187
Reduce places removed 3 places and 0 transitions.
Drop transitions removed 32 transitions
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 50 transitions.
Graph (complete) has 159 edges and 78 vertex of which 60 are kept as prefixes of interest. Removing 18 places using SCC suffix rule.0 ms
Discarding 18 places :
Also discarding 9 output transitions
Drop transitions removed 9 transitions
Iterating post reduction 48 with 54 rules applied. Total rules applied 3861 place count 60 transition count 128
Drop transitions removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 49 with 9 rules applied. Total rules applied 3870 place count 60 transition count 119
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 50 with 27 rules applied. Total rules applied 3897 place count 42 transition count 110
Drop transitions removed 6 transitions
Ensure Unique test removed 24 transitions
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 50 with 30 rules applied. Total rules applied 3927 place count 42 transition count 80
Drop transitions removed 34 transitions
Redundant transition composition rules discarded 34 transitions
Iterating global reduction 51 with 34 rules applied. Total rules applied 3961 place count 42 transition count 46
Graph (complete) has 74 edges and 42 vertex of which 24 are kept as prefixes of interest. Removing 18 places using SCC suffix rule.0 ms
Discarding 18 places :
Also discarding 0 output transitions
Iterating post reduction 51 with 1 rules applied. Total rules applied 3962 place count 24 transition count 46
Drop transitions removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 52 with 22 rules applied. Total rules applied 3984 place count 24 transition count 24
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 53 with 1 rules applied. Total rules applied 3985 place count 23 transition count 24
Free-agglomeration rule applied 4 times.
Iterating global reduction 54 with 4 rules applied. Total rules applied 3989 place count 23 transition count 20
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 54 with 4 rules applied. Total rules applied 3993 place count 19 transition count 20
Applied a total of 3993 rules in 1515 ms. Remains 19 /1750 variables (removed 1731) and now considering 20/3072 (removed 3052) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1515 ms. Remains : 19/1750 places, 20/3072 transitions.
Finished random walk after 45 steps, including 0 resets, run visited all 4 properties in 1 ms. (steps per millisecond=45 )
[2023-03-08 11:15:44] [INFO ] Flatten gal took : 74 ms
[2023-03-08 11:15:44] [INFO ] Flatten gal took : 76 ms
[2023-03-08 11:15:44] [INFO ] Input system was already deterministic with 3072 transitions.
Computed a total of 270 stabilizing places and 270 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 40 places :
Symmetric choice reduction at 0 with 40 rule applications. Total rules 40 place count 1710 transition count 3002
Iterating global reduction 0 with 40 rules applied. Total rules applied 80 place count 1710 transition count 3002
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 100 place count 1690 transition count 2972
Iterating global reduction 0 with 20 rules applied. Total rules applied 120 place count 1690 transition count 2972
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 126 place count 1684 transition count 2956
Iterating global reduction 0 with 6 rules applied. Total rules applied 132 place count 1684 transition count 2956
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 137 place count 1679 transition count 2951
Iterating global reduction 0 with 5 rules applied. Total rules applied 142 place count 1679 transition count 2951
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 146 place count 1675 transition count 2947
Iterating global reduction 0 with 4 rules applied. Total rules applied 150 place count 1675 transition count 2947
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 153 place count 1672 transition count 2944
Iterating global reduction 0 with 3 rules applied. Total rules applied 156 place count 1672 transition count 2944
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 157 place count 1671 transition count 2943
Iterating global reduction 0 with 1 rules applied. Total rules applied 158 place count 1671 transition count 2943
Applied a total of 158 rules in 380 ms. Remains 1671 /1750 variables (removed 79) and now considering 2943/3072 (removed 129) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 381 ms. Remains : 1671/1750 places, 2943/3072 transitions.
[2023-03-08 11:15:45] [INFO ] Flatten gal took : 62 ms
[2023-03-08 11:15:45] [INFO ] Flatten gal took : 65 ms
[2023-03-08 11:15:45] [INFO ] Input system was already deterministic with 2943 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Graph (trivial) has 1565 edges and 1750 vertex of which 429 / 1750 are part of one of the 37 SCC in 2 ms
Free SCC test removed 392 places
Ensure Unique test removed 420 transitions
Reduce isomorphic transitions removed 420 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 296 transitions
Trivial Post-agglo rules discarded 296 transitions
Performed 296 trivial Post agglomeration. Transition count delta: 296
Iterating post reduction 0 with 296 rules applied. Total rules applied 297 place count 1357 transition count 2355
Reduce places removed 296 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Drop transitions removed 24 transitions
Trivial Post-agglo rules discarded 24 transitions
Performed 24 trivial Post agglomeration. Transition count delta: 24
Iterating post reduction 1 with 332 rules applied. Total rules applied 629 place count 1061 transition count 2319
Reduce places removed 24 places and 0 transitions.
Iterating post reduction 2 with 24 rules applied. Total rules applied 653 place count 1037 transition count 2319
Performed 127 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 127 Pre rules applied. Total rules applied 653 place count 1037 transition count 2192
Deduced a syphon composed of 127 places in 7 ms
Reduce places removed 127 places and 0 transitions.
Iterating global reduction 3 with 254 rules applied. Total rules applied 907 place count 910 transition count 2192
Discarding 80 places :
Symmetric choice reduction at 3 with 80 rule applications. Total rules 987 place count 830 transition count 1804
Iterating global reduction 3 with 80 rules applied. Total rules applied 1067 place count 830 transition count 1804
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 1071 place count 830 transition count 1800
Performed 19 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 19 Pre rules applied. Total rules applied 1071 place count 830 transition count 1781
Deduced a syphon composed of 19 places in 5 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 4 with 38 rules applied. Total rules applied 1109 place count 811 transition count 1781
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 1111 place count 809 transition count 1759
Iterating global reduction 4 with 2 rules applied. Total rules applied 1113 place count 809 transition count 1759
Performed 276 Post agglomeration using F-continuation condition.Transition count delta: 276
Deduced a syphon composed of 276 places in 1 ms
Reduce places removed 276 places and 0 transitions.
Iterating global reduction 4 with 552 rules applied. Total rules applied 1665 place count 533 transition count 1483
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 1666 place count 533 transition count 1482
Renaming transitions due to excessive name length > 1024 char.
Discarding 25 places :
Symmetric choice reduction at 5 with 25 rule applications. Total rules 1691 place count 508 transition count 1219
Iterating global reduction 5 with 25 rules applied. Total rules applied 1716 place count 508 transition count 1219
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 5 with 17 rules applied. Total rules applied 1733 place count 508 transition count 1202
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 1735 place count 507 transition count 1201
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 6 with 17 rules applied. Total rules applied 1752 place count 507 transition count 1184
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 6 with 8 rules applied. Total rules applied 1760 place count 507 transition count 1176
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 7 with 8 rules applied. Total rules applied 1768 place count 499 transition count 1176
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 8 with 1 rules applied. Total rules applied 1769 place count 499 transition count 1176
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 1771 place count 497 transition count 1174
Applied a total of 1771 rules in 247 ms. Remains 497 /1750 variables (removed 1253) and now considering 1174/3072 (removed 1898) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 248 ms. Remains : 497/1750 places, 1174/3072 transitions.
[2023-03-08 11:15:45] [INFO ] Flatten gal took : 27 ms
[2023-03-08 11:15:45] [INFO ] Flatten gal took : 30 ms
[2023-03-08 11:15:45] [INFO ] Input system was already deterministic with 1174 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Graph (trivial) has 1564 edges and 1750 vertex of which 448 / 1750 are part of one of the 36 SCC in 2 ms
Free SCC test removed 412 places
Ensure Unique test removed 444 transitions
Reduce isomorphic transitions removed 444 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 286 transitions
Trivial Post-agglo rules discarded 286 transitions
Performed 286 trivial Post agglomeration. Transition count delta: 286
Iterating post reduction 0 with 286 rules applied. Total rules applied 287 place count 1337 transition count 2341
Reduce places removed 286 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Drop transitions removed 24 transitions
Trivial Post-agglo rules discarded 24 transitions
Performed 24 trivial Post agglomeration. Transition count delta: 24
Iterating post reduction 1 with 322 rules applied. Total rules applied 609 place count 1051 transition count 2305
Reduce places removed 24 places and 0 transitions.
Iterating post reduction 2 with 24 rules applied. Total rules applied 633 place count 1027 transition count 2305
Performed 127 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 127 Pre rules applied. Total rules applied 633 place count 1027 transition count 2178
Deduced a syphon composed of 127 places in 6 ms
Reduce places removed 127 places and 0 transitions.
Iterating global reduction 3 with 254 rules applied. Total rules applied 887 place count 900 transition count 2178
Discarding 79 places :
Symmetric choice reduction at 3 with 79 rule applications. Total rules 966 place count 821 transition count 1801
Iterating global reduction 3 with 79 rules applied. Total rules applied 1045 place count 821 transition count 1801
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 1049 place count 821 transition count 1797
Performed 20 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 20 Pre rules applied. Total rules applied 1049 place count 821 transition count 1777
Deduced a syphon composed of 20 places in 5 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 4 with 40 rules applied. Total rules applied 1089 place count 801 transition count 1777
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 1090 place count 800 transition count 1766
Iterating global reduction 4 with 1 rules applied. Total rules applied 1091 place count 800 transition count 1766
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 1092 place count 800 transition count 1765
Performed 269 Post agglomeration using F-continuation condition.Transition count delta: 269
Deduced a syphon composed of 269 places in 1 ms
Reduce places removed 269 places and 0 transitions.
Iterating global reduction 5 with 538 rules applied. Total rules applied 1630 place count 531 transition count 1496
Renaming transitions due to excessive name length > 1024 char.
Discarding 26 places :
Symmetric choice reduction at 5 with 26 rule applications. Total rules 1656 place count 505 transition count 1222
Iterating global reduction 5 with 26 rules applied. Total rules applied 1682 place count 505 transition count 1222
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 5 with 18 rules applied. Total rules applied 1700 place count 505 transition count 1204
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 6 with 16 rules applied. Total rules applied 1716 place count 505 transition count 1188
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 6 with 8 rules applied. Total rules applied 1724 place count 505 transition count 1180
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 7 with 8 rules applied. Total rules applied 1732 place count 497 transition count 1180
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 1734 place count 495 transition count 1178
Applied a total of 1734 rules in 189 ms. Remains 495 /1750 variables (removed 1255) and now considering 1178/3072 (removed 1894) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 190 ms. Remains : 495/1750 places, 1178/3072 transitions.
[2023-03-08 11:15:46] [INFO ] Flatten gal took : 25 ms
[2023-03-08 11:15:46] [INFO ] Flatten gal took : 28 ms
[2023-03-08 11:15:46] [INFO ] Input system was already deterministic with 1178 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 39 places :
Symmetric choice reduction at 0 with 39 rule applications. Total rules 39 place count 1711 transition count 3003
Iterating global reduction 0 with 39 rules applied. Total rules applied 78 place count 1711 transition count 3003
Discarding 18 places :
Symmetric choice reduction at 0 with 18 rule applications. Total rules 96 place count 1693 transition count 2975
Iterating global reduction 0 with 18 rules applied. Total rules applied 114 place count 1693 transition count 2975
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 118 place count 1689 transition count 2961
Iterating global reduction 0 with 4 rules applied. Total rules applied 122 place count 1689 transition count 2961
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 125 place count 1686 transition count 2958
Iterating global reduction 0 with 3 rules applied. Total rules applied 128 place count 1686 transition count 2958
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 130 place count 1684 transition count 2956
Iterating global reduction 0 with 2 rules applied. Total rules applied 132 place count 1684 transition count 2956
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 133 place count 1683 transition count 2955
Iterating global reduction 0 with 1 rules applied. Total rules applied 134 place count 1683 transition count 2955
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 135 place count 1682 transition count 2954
Iterating global reduction 0 with 1 rules applied. Total rules applied 136 place count 1682 transition count 2954
Applied a total of 136 rules in 361 ms. Remains 1682 /1750 variables (removed 68) and now considering 2954/3072 (removed 118) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 362 ms. Remains : 1682/1750 places, 2954/3072 transitions.
[2023-03-08 11:15:46] [INFO ] Flatten gal took : 58 ms
[2023-03-08 11:15:46] [INFO ] Flatten gal took : 60 ms
[2023-03-08 11:15:46] [INFO ] Input system was already deterministic with 2954 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Graph (trivial) has 1566 edges and 1750 vertex of which 433 / 1750 are part of one of the 35 SCC in 1 ms
Free SCC test removed 398 places
Ensure Unique test removed 428 transitions
Reduce isomorphic transitions removed 428 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 295 transitions
Trivial Post-agglo rules discarded 295 transitions
Performed 295 trivial Post agglomeration. Transition count delta: 295
Iterating post reduction 0 with 295 rules applied. Total rules applied 296 place count 1351 transition count 2348
Reduce places removed 295 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Drop transitions removed 24 transitions
Trivial Post-agglo rules discarded 24 transitions
Performed 24 trivial Post agglomeration. Transition count delta: 24
Iterating post reduction 1 with 331 rules applied. Total rules applied 627 place count 1056 transition count 2312
Reduce places removed 24 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 25 rules applied. Total rules applied 652 place count 1032 transition count 2311
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 653 place count 1031 transition count 2311
Performed 127 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 127 Pre rules applied. Total rules applied 653 place count 1031 transition count 2184
Deduced a syphon composed of 127 places in 5 ms
Reduce places removed 127 places and 0 transitions.
Iterating global reduction 4 with 254 rules applied. Total rules applied 907 place count 904 transition count 2184
Discarding 82 places :
Symmetric choice reduction at 4 with 82 rule applications. Total rules 989 place count 822 transition count 1791
Iterating global reduction 4 with 82 rules applied. Total rules applied 1071 place count 822 transition count 1791
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 1074 place count 822 transition count 1788
Performed 21 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 21 Pre rules applied. Total rules applied 1074 place count 822 transition count 1767
Deduced a syphon composed of 21 places in 4 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 5 with 42 rules applied. Total rules applied 1116 place count 801 transition count 1767
Discarding 2 places :
Symmetric choice reduction at 5 with 2 rule applications. Total rules 1118 place count 799 transition count 1745
Iterating global reduction 5 with 2 rules applied. Total rules applied 1120 place count 799 transition count 1745
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 1121 place count 799 transition count 1744
Performed 272 Post agglomeration using F-continuation condition.Transition count delta: 272
Deduced a syphon composed of 272 places in 0 ms
Reduce places removed 272 places and 0 transitions.
Iterating global reduction 6 with 544 rules applied. Total rules applied 1665 place count 527 transition count 1472
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 1666 place count 527 transition count 1471
Renaming transitions due to excessive name length > 1024 char.
Discarding 26 places :
Symmetric choice reduction at 7 with 26 rule applications. Total rules 1692 place count 501 transition count 1197
Iterating global reduction 7 with 26 rules applied. Total rules applied 1718 place count 501 transition count 1197
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 7 with 19 rules applied. Total rules applied 1737 place count 501 transition count 1178
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 1739 place count 500 transition count 1177
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 8 with 17 rules applied. Total rules applied 1756 place count 500 transition count 1160
Drop transitions removed 9 transitions
Trivial Post-agglo rules discarded 9 transitions
Performed 9 trivial Post agglomeration. Transition count delta: 9
Iterating post reduction 8 with 9 rules applied. Total rules applied 1765 place count 500 transition count 1151
Reduce places removed 9 places and 0 transitions.
Iterating post reduction 9 with 9 rules applied. Total rules applied 1774 place count 491 transition count 1151
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 1776 place count 489 transition count 1149
Applied a total of 1776 rules in 194 ms. Remains 489 /1750 variables (removed 1261) and now considering 1149/3072 (removed 1923) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 195 ms. Remains : 489/1750 places, 1149/3072 transitions.
[2023-03-08 11:15:47] [INFO ] Flatten gal took : 23 ms
[2023-03-08 11:15:47] [INFO ] Flatten gal took : 25 ms
[2023-03-08 11:15:47] [INFO ] Input system was already deterministic with 1149 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 43 places :
Symmetric choice reduction at 0 with 43 rule applications. Total rules 43 place count 1707 transition count 2999
Iterating global reduction 0 with 43 rules applied. Total rules applied 86 place count 1707 transition count 2999
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 105 place count 1688 transition count 2970
Iterating global reduction 0 with 19 rules applied. Total rules applied 124 place count 1688 transition count 2970
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 129 place count 1683 transition count 2965
Iterating global reduction 0 with 5 rules applied. Total rules applied 134 place count 1683 transition count 2965
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 139 place count 1678 transition count 2960
Iterating global reduction 0 with 5 rules applied. Total rules applied 144 place count 1678 transition count 2960
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 148 place count 1674 transition count 2956
Iterating global reduction 0 with 4 rules applied. Total rules applied 152 place count 1674 transition count 2956
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 155 place count 1671 transition count 2953
Iterating global reduction 0 with 3 rules applied. Total rules applied 158 place count 1671 transition count 2953
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 159 place count 1670 transition count 2952
Iterating global reduction 0 with 1 rules applied. Total rules applied 160 place count 1670 transition count 2952
Applied a total of 160 rules in 384 ms. Remains 1670 /1750 variables (removed 80) and now considering 2952/3072 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 386 ms. Remains : 1670/1750 places, 2952/3072 transitions.
[2023-03-08 11:15:47] [INFO ] Flatten gal took : 56 ms
[2023-03-08 11:15:47] [INFO ] Flatten gal took : 59 ms
[2023-03-08 11:15:47] [INFO ] Input system was already deterministic with 2952 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Graph (trivial) has 1572 edges and 1750 vertex of which 448 / 1750 are part of one of the 36 SCC in 2 ms
Free SCC test removed 412 places
Ensure Unique test removed 444 transitions
Reduce isomorphic transitions removed 444 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 291 transitions
Trivial Post-agglo rules discarded 291 transitions
Performed 291 trivial Post agglomeration. Transition count delta: 291
Iterating post reduction 0 with 291 rules applied. Total rules applied 292 place count 1337 transition count 2336
Reduce places removed 291 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Drop transitions removed 24 transitions
Trivial Post-agglo rules discarded 24 transitions
Performed 24 trivial Post agglomeration. Transition count delta: 24
Iterating post reduction 1 with 327 rules applied. Total rules applied 619 place count 1046 transition count 2300
Reduce places removed 24 places and 0 transitions.
Iterating post reduction 2 with 24 rules applied. Total rules applied 643 place count 1022 transition count 2300
Performed 125 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 125 Pre rules applied. Total rules applied 643 place count 1022 transition count 2175
Deduced a syphon composed of 125 places in 6 ms
Reduce places removed 125 places and 0 transitions.
Iterating global reduction 3 with 250 rules applied. Total rules applied 893 place count 897 transition count 2175
Discarding 84 places :
Symmetric choice reduction at 3 with 84 rule applications. Total rules 977 place count 813 transition count 1773
Iterating global reduction 3 with 84 rules applied. Total rules applied 1061 place count 813 transition count 1773
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 1065 place count 813 transition count 1769
Performed 21 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 21 Pre rules applied. Total rules applied 1065 place count 813 transition count 1748
Deduced a syphon composed of 21 places in 5 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 4 with 42 rules applied. Total rules applied 1107 place count 792 transition count 1748
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 1109 place count 790 transition count 1726
Iterating global reduction 4 with 2 rules applied. Total rules applied 1111 place count 790 transition count 1726
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 1112 place count 790 transition count 1725
Performed 270 Post agglomeration using F-continuation condition.Transition count delta: 270
Deduced a syphon composed of 270 places in 0 ms
Reduce places removed 270 places and 0 transitions.
Iterating global reduction 5 with 540 rules applied. Total rules applied 1652 place count 520 transition count 1455
Renaming transitions due to excessive name length > 1024 char.
Discarding 26 places :
Symmetric choice reduction at 5 with 26 rule applications. Total rules 1678 place count 494 transition count 1181
Iterating global reduction 5 with 26 rules applied. Total rules applied 1704 place count 494 transition count 1181
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 5 with 19 rules applied. Total rules applied 1723 place count 494 transition count 1162
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 6 with 16 rules applied. Total rules applied 1739 place count 494 transition count 1146
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 6 with 8 rules applied. Total rules applied 1747 place count 494 transition count 1138
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 7 with 8 rules applied. Total rules applied 1755 place count 486 transition count 1138
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 1757 place count 484 transition count 1136
Applied a total of 1757 rules in 166 ms. Remains 484 /1750 variables (removed 1266) and now considering 1136/3072 (removed 1936) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 166 ms. Remains : 484/1750 places, 1136/3072 transitions.
[2023-03-08 11:15:48] [INFO ] Flatten gal took : 21 ms
[2023-03-08 11:15:48] [INFO ] Flatten gal took : 23 ms
[2023-03-08 11:15:48] [INFO ] Input system was already deterministic with 1136 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 1704 transition count 2996
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 1704 transition count 2996
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 114 place count 1682 transition count 2964
Iterating global reduction 0 with 22 rules applied. Total rules applied 136 place count 1682 transition count 2964
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 142 place count 1676 transition count 2948
Iterating global reduction 0 with 6 rules applied. Total rules applied 148 place count 1676 transition count 2948
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 153 place count 1671 transition count 2943
Iterating global reduction 0 with 5 rules applied. Total rules applied 158 place count 1671 transition count 2943
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 162 place count 1667 transition count 2939
Iterating global reduction 0 with 4 rules applied. Total rules applied 166 place count 1667 transition count 2939
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 169 place count 1664 transition count 2936
Iterating global reduction 0 with 3 rules applied. Total rules applied 172 place count 1664 transition count 2936
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 173 place count 1663 transition count 2935
Iterating global reduction 0 with 1 rules applied. Total rules applied 174 place count 1663 transition count 2935
Applied a total of 174 rules in 361 ms. Remains 1663 /1750 variables (removed 87) and now considering 2935/3072 (removed 137) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 362 ms. Remains : 1663/1750 places, 2935/3072 transitions.
[2023-03-08 11:15:48] [INFO ] Flatten gal took : 48 ms
[2023-03-08 11:15:48] [INFO ] Flatten gal took : 51 ms
[2023-03-08 11:15:48] [INFO ] Input system was already deterministic with 2935 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 1704 transition count 2996
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 1704 transition count 2996
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 114 place count 1682 transition count 2964
Iterating global reduction 0 with 22 rules applied. Total rules applied 136 place count 1682 transition count 2964
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 142 place count 1676 transition count 2948
Iterating global reduction 0 with 6 rules applied. Total rules applied 148 place count 1676 transition count 2948
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 153 place count 1671 transition count 2943
Iterating global reduction 0 with 5 rules applied. Total rules applied 158 place count 1671 transition count 2943
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 162 place count 1667 transition count 2939
Iterating global reduction 0 with 4 rules applied. Total rules applied 166 place count 1667 transition count 2939
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 169 place count 1664 transition count 2936
Iterating global reduction 0 with 3 rules applied. Total rules applied 172 place count 1664 transition count 2936
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 173 place count 1663 transition count 2935
Iterating global reduction 0 with 1 rules applied. Total rules applied 174 place count 1663 transition count 2935
Applied a total of 174 rules in 440 ms. Remains 1663 /1750 variables (removed 87) and now considering 2935/3072 (removed 137) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 441 ms. Remains : 1663/1750 places, 2935/3072 transitions.
[2023-03-08 11:15:49] [INFO ] Flatten gal took : 51 ms
[2023-03-08 11:15:49] [INFO ] Flatten gal took : 55 ms
[2023-03-08 11:15:49] [INFO ] Input system was already deterministic with 2935 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 43 places :
Symmetric choice reduction at 0 with 43 rule applications. Total rules 43 place count 1707 transition count 3009
Iterating global reduction 0 with 43 rules applied. Total rules applied 86 place count 1707 transition count 3009
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 108 place count 1685 transition count 2977
Iterating global reduction 0 with 22 rules applied. Total rules applied 130 place count 1685 transition count 2977
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 136 place count 1679 transition count 2961
Iterating global reduction 0 with 6 rules applied. Total rules applied 142 place count 1679 transition count 2961
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 147 place count 1674 transition count 2956
Iterating global reduction 0 with 5 rules applied. Total rules applied 152 place count 1674 transition count 2956
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 156 place count 1670 transition count 2952
Iterating global reduction 0 with 4 rules applied. Total rules applied 160 place count 1670 transition count 2952
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 163 place count 1667 transition count 2949
Iterating global reduction 0 with 3 rules applied. Total rules applied 166 place count 1667 transition count 2949
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 167 place count 1666 transition count 2948
Iterating global reduction 0 with 1 rules applied. Total rules applied 168 place count 1666 transition count 2948
Applied a total of 168 rules in 354 ms. Remains 1666 /1750 variables (removed 84) and now considering 2948/3072 (removed 124) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 355 ms. Remains : 1666/1750 places, 2948/3072 transitions.
[2023-03-08 11:15:49] [INFO ] Flatten gal took : 47 ms
[2023-03-08 11:15:49] [INFO ] Flatten gal took : 50 ms
[2023-03-08 11:15:50] [INFO ] Input system was already deterministic with 2948 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 44 places :
Symmetric choice reduction at 0 with 44 rule applications. Total rules 44 place count 1706 transition count 2998
Iterating global reduction 0 with 44 rules applied. Total rules applied 88 place count 1706 transition count 2998
Discarding 21 places :
Symmetric choice reduction at 0 with 21 rule applications. Total rules 109 place count 1685 transition count 2967
Iterating global reduction 0 with 21 rules applied. Total rules applied 130 place count 1685 transition count 2967
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 136 place count 1679 transition count 2951
Iterating global reduction 0 with 6 rules applied. Total rules applied 142 place count 1679 transition count 2951
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 147 place count 1674 transition count 2946
Iterating global reduction 0 with 5 rules applied. Total rules applied 152 place count 1674 transition count 2946
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 156 place count 1670 transition count 2942
Iterating global reduction 0 with 4 rules applied. Total rules applied 160 place count 1670 transition count 2942
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 163 place count 1667 transition count 2939
Iterating global reduction 0 with 3 rules applied. Total rules applied 166 place count 1667 transition count 2939
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 167 place count 1666 transition count 2938
Iterating global reduction 0 with 1 rules applied. Total rules applied 168 place count 1666 transition count 2938
Applied a total of 168 rules in 338 ms. Remains 1666 /1750 variables (removed 84) and now considering 2938/3072 (removed 134) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 338 ms. Remains : 1666/1750 places, 2938/3072 transitions.
[2023-03-08 11:15:50] [INFO ] Flatten gal took : 44 ms
[2023-03-08 11:15:50] [INFO ] Flatten gal took : 48 ms
[2023-03-08 11:15:50] [INFO ] Input system was already deterministic with 2938 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 41 places :
Symmetric choice reduction at 0 with 41 rule applications. Total rules 41 place count 1709 transition count 3001
Iterating global reduction 0 with 41 rules applied. Total rules applied 82 place count 1709 transition count 3001
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 101 place count 1690 transition count 2972
Iterating global reduction 0 with 19 rules applied. Total rules applied 120 place count 1690 transition count 2972
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 124 place count 1686 transition count 2958
Iterating global reduction 0 with 4 rules applied. Total rules applied 128 place count 1686 transition count 2958
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 131 place count 1683 transition count 2955
Iterating global reduction 0 with 3 rules applied. Total rules applied 134 place count 1683 transition count 2955
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 136 place count 1681 transition count 2953
Iterating global reduction 0 with 2 rules applied. Total rules applied 138 place count 1681 transition count 2953
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 140 place count 1679 transition count 2951
Iterating global reduction 0 with 2 rules applied. Total rules applied 142 place count 1679 transition count 2951
Applied a total of 142 rules in 295 ms. Remains 1679 /1750 variables (removed 71) and now considering 2951/3072 (removed 121) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 295 ms. Remains : 1679/1750 places, 2951/3072 transitions.
[2023-03-08 11:15:50] [INFO ] Flatten gal took : 45 ms
[2023-03-08 11:15:51] [INFO ] Flatten gal took : 48 ms
[2023-03-08 11:15:51] [INFO ] Input system was already deterministic with 2951 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 35 places :
Symmetric choice reduction at 0 with 35 rule applications. Total rules 35 place count 1715 transition count 3017
Iterating global reduction 0 with 35 rules applied. Total rules applied 70 place count 1715 transition count 3017
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 86 place count 1699 transition count 2991
Iterating global reduction 0 with 16 rules applied. Total rules applied 102 place count 1699 transition count 2991
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 107 place count 1694 transition count 2976
Iterating global reduction 0 with 5 rules applied. Total rules applied 112 place count 1694 transition count 2976
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 116 place count 1690 transition count 2972
Iterating global reduction 0 with 4 rules applied. Total rules applied 120 place count 1690 transition count 2972
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 124 place count 1686 transition count 2968
Iterating global reduction 0 with 4 rules applied. Total rules applied 128 place count 1686 transition count 2968
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 131 place count 1683 transition count 2965
Iterating global reduction 0 with 3 rules applied. Total rules applied 134 place count 1683 transition count 2965
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 135 place count 1682 transition count 2964
Iterating global reduction 0 with 1 rules applied. Total rules applied 136 place count 1682 transition count 2964
Applied a total of 136 rules in 420 ms. Remains 1682 /1750 variables (removed 68) and now considering 2964/3072 (removed 108) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 420 ms. Remains : 1682/1750 places, 2964/3072 transitions.
[2023-03-08 11:15:51] [INFO ] Flatten gal took : 44 ms
[2023-03-08 11:15:51] [INFO ] Flatten gal took : 47 ms
[2023-03-08 11:15:51] [INFO ] Input system was already deterministic with 2964 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Graph (trivial) has 1573 edges and 1750 vertex of which 448 / 1750 are part of one of the 36 SCC in 1 ms
Free SCC test removed 412 places
Ensure Unique test removed 444 transitions
Reduce isomorphic transitions removed 444 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 291 transitions
Trivial Post-agglo rules discarded 291 transitions
Performed 291 trivial Post agglomeration. Transition count delta: 291
Iterating post reduction 0 with 291 rules applied. Total rules applied 292 place count 1337 transition count 2336
Reduce places removed 291 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Drop transitions removed 24 transitions
Trivial Post-agglo rules discarded 24 transitions
Performed 24 trivial Post agglomeration. Transition count delta: 24
Iterating post reduction 1 with 327 rules applied. Total rules applied 619 place count 1046 transition count 2300
Reduce places removed 24 places and 0 transitions.
Iterating post reduction 2 with 24 rules applied. Total rules applied 643 place count 1022 transition count 2300
Performed 125 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 125 Pre rules applied. Total rules applied 643 place count 1022 transition count 2175
Deduced a syphon composed of 125 places in 6 ms
Reduce places removed 125 places and 0 transitions.
Iterating global reduction 3 with 250 rules applied. Total rules applied 893 place count 897 transition count 2175
Discarding 83 places :
Symmetric choice reduction at 3 with 83 rule applications. Total rules 976 place count 814 transition count 1774
Iterating global reduction 3 with 83 rules applied. Total rules applied 1059 place count 814 transition count 1774
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 1063 place count 814 transition count 1770
Performed 21 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 21 Pre rules applied. Total rules applied 1063 place count 814 transition count 1749
Deduced a syphon composed of 21 places in 4 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 4 with 42 rules applied. Total rules applied 1105 place count 793 transition count 1749
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 1107 place count 791 transition count 1727
Iterating global reduction 4 with 2 rules applied. Total rules applied 1109 place count 791 transition count 1727
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 1110 place count 791 transition count 1726
Performed 270 Post agglomeration using F-continuation condition.Transition count delta: 270
Deduced a syphon composed of 270 places in 0 ms
Reduce places removed 270 places and 0 transitions.
Iterating global reduction 5 with 540 rules applied. Total rules applied 1650 place count 521 transition count 1456
Renaming transitions due to excessive name length > 1024 char.
Discarding 25 places :
Symmetric choice reduction at 5 with 25 rule applications. Total rules 1675 place count 496 transition count 1193
Iterating global reduction 5 with 25 rules applied. Total rules applied 1700 place count 496 transition count 1193
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 5 with 19 rules applied. Total rules applied 1719 place count 496 transition count 1174
Drop transitions removed 15 transitions
Redundant transition composition rules discarded 15 transitions
Iterating global reduction 6 with 15 rules applied. Total rules applied 1734 place count 496 transition count 1159
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 6 with 7 rules applied. Total rules applied 1741 place count 496 transition count 1152
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 7 with 7 rules applied. Total rules applied 1748 place count 489 transition count 1152
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 1750 place count 487 transition count 1150
Applied a total of 1750 rules in 176 ms. Remains 487 /1750 variables (removed 1263) and now considering 1150/3072 (removed 1922) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 176 ms. Remains : 487/1750 places, 1150/3072 transitions.
[2023-03-08 11:15:51] [INFO ] Flatten gal took : 20 ms
[2023-03-08 11:15:52] [INFO ] Flatten gal took : 21 ms
[2023-03-08 11:15:52] [INFO ] Input system was already deterministic with 1150 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 1704 transition count 2996
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 1704 transition count 2996
Discarding 22 places :
Symmetric choice reduction at 0 with 22 rule applications. Total rules 114 place count 1682 transition count 2964
Iterating global reduction 0 with 22 rules applied. Total rules applied 136 place count 1682 transition count 2964
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 142 place count 1676 transition count 2948
Iterating global reduction 0 with 6 rules applied. Total rules applied 148 place count 1676 transition count 2948
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 153 place count 1671 transition count 2943
Iterating global reduction 0 with 5 rules applied. Total rules applied 158 place count 1671 transition count 2943
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 162 place count 1667 transition count 2939
Iterating global reduction 0 with 4 rules applied. Total rules applied 166 place count 1667 transition count 2939
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 169 place count 1664 transition count 2936
Iterating global reduction 0 with 3 rules applied. Total rules applied 172 place count 1664 transition count 2936
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 173 place count 1663 transition count 2935
Iterating global reduction 0 with 1 rules applied. Total rules applied 174 place count 1663 transition count 2935
Applied a total of 174 rules in 343 ms. Remains 1663 /1750 variables (removed 87) and now considering 2935/3072 (removed 137) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 344 ms. Remains : 1663/1750 places, 2935/3072 transitions.
[2023-03-08 11:15:52] [INFO ] Flatten gal took : 45 ms
[2023-03-08 11:15:52] [INFO ] Flatten gal took : 47 ms
[2023-03-08 11:15:52] [INFO ] Input system was already deterministic with 2935 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1750/1750 places, 3072/3072 transitions.
Graph (trivial) has 1565 edges and 1750 vertex of which 448 / 1750 are part of one of the 36 SCC in 0 ms
Free SCC test removed 412 places
Ensure Unique test removed 444 transitions
Reduce isomorphic transitions removed 444 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 287 transitions
Trivial Post-agglo rules discarded 287 transitions
Performed 287 trivial Post agglomeration. Transition count delta: 287
Iterating post reduction 0 with 287 rules applied. Total rules applied 288 place count 1337 transition count 2340
Reduce places removed 287 places and 0 transitions.
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Drop transitions removed 24 transitions
Trivial Post-agglo rules discarded 24 transitions
Performed 24 trivial Post agglomeration. Transition count delta: 24
Iterating post reduction 1 with 323 rules applied. Total rules applied 611 place count 1050 transition count 2304
Reduce places removed 24 places and 0 transitions.
Iterating post reduction 2 with 24 rules applied. Total rules applied 635 place count 1026 transition count 2304
Performed 125 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 125 Pre rules applied. Total rules applied 635 place count 1026 transition count 2179
Deduced a syphon composed of 125 places in 6 ms
Reduce places removed 125 places and 0 transitions.
Iterating global reduction 3 with 250 rules applied. Total rules applied 885 place count 901 transition count 2179
Discarding 81 places :
Symmetric choice reduction at 3 with 81 rule applications. Total rules 966 place count 820 transition count 1810
Iterating global reduction 3 with 81 rules applied. Total rules applied 1047 place count 820 transition count 1810
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 1051 place count 820 transition count 1806
Performed 21 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 21 Pre rules applied. Total rules applied 1051 place count 820 transition count 1785
Deduced a syphon composed of 21 places in 4 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 4 with 42 rules applied. Total rules applied 1093 place count 799 transition count 1785
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 1095 place count 797 transition count 1763
Iterating global reduction 4 with 2 rules applied. Total rules applied 1097 place count 797 transition count 1763
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 1098 place count 797 transition count 1762
Performed 270 Post agglomeration using F-continuation condition.Transition count delta: 270
Deduced a syphon composed of 270 places in 0 ms
Reduce places removed 270 places and 0 transitions.
Iterating global reduction 5 with 540 rules applied. Total rules applied 1638 place count 527 transition count 1492
Renaming transitions due to excessive name length > 1024 char.
Discarding 26 places :
Symmetric choice reduction at 5 with 26 rule applications. Total rules 1664 place count 501 transition count 1218
Iterating global reduction 5 with 26 rules applied. Total rules applied 1690 place count 501 transition count 1218
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 5 with 19 rules applied. Total rules applied 1709 place count 501 transition count 1199
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 6 with 13 rules applied. Total rules applied 1722 place count 501 transition count 1186
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 6 with 7 rules applied. Total rules applied 1729 place count 501 transition count 1179
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 7 with 7 rules applied. Total rules applied 1736 place count 494 transition count 1179
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 1738 place count 492 transition count 1177
Applied a total of 1738 rules in 169 ms. Remains 492 /1750 variables (removed 1258) and now considering 1177/3072 (removed 1895) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 170 ms. Remains : 492/1750 places, 1177/3072 transitions.
[2023-03-08 11:15:52] [INFO ] Flatten gal took : 21 ms
[2023-03-08 11:15:52] [INFO ] Flatten gal took : 22 ms
[2023-03-08 11:15:52] [INFO ] Input system was already deterministic with 1177 transitions.
[2023-03-08 11:15:52] [INFO ] Flatten gal took : 51 ms
[2023-03-08 11:15:52] [INFO ] Flatten gal took : 50 ms
[2023-03-08 11:15:53] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-08 11:15:53] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1750 places, 3072 transitions and 9009 arcs took 12 ms.
Total runtime 23703 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCround-PT-07b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA DLCround-PT-07b-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678274780984
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 64 (type EXCL) for 63 DLCround-PT-07b-CTLFireability-13
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 64 (type EXCL) for DLCround-PT-07b-CTLFireability-13
lola: result : false
lola: markings : 3988
lola: fired transitions : 10713
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-07b-CTLFireability-01
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 73 (type FNDP) for 12 DLCround-PT-07b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type EQUN) for 12 DLCround-PT-07b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type SRCH) for 12 DLCround-PT-07b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 1.000000 secs.
lola: FINISHED task # 76 (type SRCH) for DLCround-PT-07b-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/375/CTLFireability-74.sara.
lola: FINISHED task # 73 (type FNDP) for DLCround-PT-07b-CTLFireability-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 74 (type EQUN) for DLCround-PT-07b-CTLFireability-04 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: FINISHED task # 74 (type EQUN) for DLCround-PT-07b-CTLFireability-04
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 78 (type FNDP) for 12 DLCround-PT-07b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type EQUN) for 12 DLCround-PT-07b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SRCH) for 12 DLCround-PT-07b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 81 (type SRCH) for DLCround-PT-07b-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 78 (type FNDP) for DLCround-PT-07b-CTLFireability-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 79 (type EQUN) for DLCround-PT-07b-CTLFireability-04 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: try reading problem file /home/mcc/execution/375/CTLFireability-79.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 79 (type EQUN) for DLCround-PT-07b-CTLFireability-04
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 3/189 1/32 DLCround-PT-07b-CTLFireability-01 175511 m, 35102 m/sec, 578057 t fired, .
Time elapsed: 12 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 8/189 4/32 DLCround-PT-07b-CTLFireability-01 648088 m, 94515 m/sec, 2161980 t fired, .
Time elapsed: 17 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 13/189 7/32 DLCround-PT-07b-CTLFireability-01 1118741 m, 94130 m/sec, 3739762 t fired, .
Time elapsed: 22 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 18/189 9/32 DLCround-PT-07b-CTLFireability-01 1580074 m, 92266 m/sec, 5309669 t fired, .
Time elapsed: 27 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 23/189 12/32 DLCround-PT-07b-CTLFireability-01 2027745 m, 89534 m/sec, 6873191 t fired, .
Time elapsed: 32 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 28/189 14/32 DLCround-PT-07b-CTLFireability-01 2427090 m, 79869 m/sec, 8451257 t fired, .
Time elapsed: 37 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 33/189 16/32 DLCround-PT-07b-CTLFireability-01 2826446 m, 79871 m/sec, 10045176 t fired, .
Time elapsed: 42 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 38/189 19/32 DLCround-PT-07b-CTLFireability-01 3308087 m, 96328 m/sec, 11658729 t fired, .
Time elapsed: 47 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 43/189 22/32 DLCround-PT-07b-CTLFireability-01 3786945 m, 95771 m/sec, 13245583 t fired, .
Time elapsed: 52 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 48/189 25/32 DLCround-PT-07b-CTLFireability-01 4244053 m, 91421 m/sec, 14772122 t fired, .
Time elapsed: 57 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 53/189 27/32 DLCround-PT-07b-CTLFireability-01 4684880 m, 88165 m/sec, 16295722 t fired, .
Time elapsed: 62 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 58/189 29/32 DLCround-PT-07b-CTLFireability-01 5108496 m, 84723 m/sec, 17798687 t fired, .
Time elapsed: 67 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 63/189 32/32 DLCround-PT-07b-CTLFireability-01 5534295 m, 85159 m/sec, 19314094 t fired, .
Time elapsed: 72 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for DLCround-PT-07b-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 77 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 67 (type EXCL) for 66 DLCround-PT-07b-CTLFireability-14
lola: time limit : 195 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 5/195 3/32 DLCround-PT-07b-CTLFireability-14 198760 m, 39752 m/sec, 418018 t fired, .
Time elapsed: 82 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 10/195 5/32 DLCround-PT-07b-CTLFireability-14 393784 m, 39004 m/sec, 832437 t fired, .
Time elapsed: 87 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 15/195 7/32 DLCround-PT-07b-CTLFireability-14 585312 m, 38305 m/sec, 1241505 t fired, .
Time elapsed: 92 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 20/195 8/32 DLCround-PT-07b-CTLFireability-14 778563 m, 38650 m/sec, 1651605 t fired, .
Time elapsed: 97 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 25/195 10/32 DLCround-PT-07b-CTLFireability-14 969494 m, 38186 m/sec, 2060232 t fired, .
Time elapsed: 102 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 30/195 13/32 DLCround-PT-07b-CTLFireability-14 1158349 m, 37771 m/sec, 2460684 t fired, .
Time elapsed: 107 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 35/195 15/32 DLCround-PT-07b-CTLFireability-14 1351519 m, 38634 m/sec, 2869196 t fired, .
Time elapsed: 112 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 40/195 17/32 DLCround-PT-07b-CTLFireability-14 1545847 m, 38865 m/sec, 3279328 t fired, .
Time elapsed: 117 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 45/195 20/32 DLCround-PT-07b-CTLFireability-14 1742149 m, 39260 m/sec, 3694707 t fired, .
Time elapsed: 122 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 50/195 23/32 DLCround-PT-07b-CTLFireability-14 1942651 m, 40100 m/sec, 4120106 t fired, .
Time elapsed: 127 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 55/195 26/32 DLCround-PT-07b-CTLFireability-14 2143241 m, 40118 m/sec, 4545139 t fired, .
Time elapsed: 132 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 60/195 29/32 DLCround-PT-07b-CTLFireability-14 2340302 m, 39412 m/sec, 4975038 t fired, .
Time elapsed: 137 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 65/195 32/32 DLCround-PT-07b-CTLFireability-14 2539875 m, 39914 m/sec, 5397910 t fired, .
Time elapsed: 142 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 67 (type EXCL) for DLCround-PT-07b-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 147 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 61 (type EXCL) for 60 DLCround-PT-07b-CTLFireability-12
lola: time limit : 203 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 5/203 7/32 DLCround-PT-07b-CTLFireability-12 488451 m, 97690 m/sec, 508980 t fired, .
Time elapsed: 152 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 10/203 11/32 DLCround-PT-07b-CTLFireability-12 981609 m, 98631 m/sec, 1040378 t fired, .
Time elapsed: 157 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 15/203 16/32 DLCround-PT-07b-CTLFireability-12 1474570 m, 98592 m/sec, 1580054 t fired, .
Time elapsed: 162 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 20/203 22/32 DLCround-PT-07b-CTLFireability-12 1969735 m, 99033 m/sec, 2125949 t fired, .
Time elapsed: 167 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 25/203 26/32 DLCround-PT-07b-CTLFireability-12 2460503 m, 98153 m/sec, 2670244 t fired, .
Time elapsed: 172 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 30/203 30/32 DLCround-PT-07b-CTLFireability-12 2942571 m, 96413 m/sec, 3212502 t fired, .
Time elapsed: 177 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 61 (type EXCL) for DLCround-PT-07b-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-11: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 182 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 58 (type EXCL) for 45 DLCround-PT-07b-CTLFireability-11
lola: time limit : 213 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for DLCround-PT-07b-CTLFireability-11
lola: result : false
lola: markings : 646
lola: fired transitions : 646
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 DLCround-PT-07b-CTLFireability-10
lola: time limit : 284 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/284 2/32 DLCround-PT-07b-CTLFireability-10 159756 m, 31951 m/sec, 593629 t fired, .
Time elapsed: 187 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/284 3/32 DLCround-PT-07b-CTLFireability-10 303182 m, 28685 m/sec, 1192718 t fired, .
Time elapsed: 192 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/284 4/32 DLCround-PT-07b-CTLFireability-10 443660 m, 28095 m/sec, 1788436 t fired, .
Time elapsed: 197 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/284 5/32 DLCround-PT-07b-CTLFireability-10 590918 m, 29451 m/sec, 2376120 t fired, .
Time elapsed: 202 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/284 6/32 DLCround-PT-07b-CTLFireability-10 714668 m, 24750 m/sec, 2971334 t fired, .
Time elapsed: 207 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/284 7/32 DLCround-PT-07b-CTLFireability-10 838340 m, 24734 m/sec, 3564670 t fired, .
Time elapsed: 212 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 35/284 8/32 DLCround-PT-07b-CTLFireability-10 958862 m, 24104 m/sec, 4159646 t fired, .
Time elapsed: 217 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 40/284 9/32 DLCround-PT-07b-CTLFireability-10 1060984 m, 20424 m/sec, 4757410 t fired, .
Time elapsed: 222 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 45/284 10/32 DLCround-PT-07b-CTLFireability-10 1211772 m, 30157 m/sec, 5331065 t fired, .
Time elapsed: 227 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 50/284 11/32 DLCround-PT-07b-CTLFireability-10 1349348 m, 27515 m/sec, 5903312 t fired, .
Time elapsed: 232 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 55/284 12/32 DLCround-PT-07b-CTLFireability-10 1484120 m, 26954 m/sec, 6480735 t fired, .
Time elapsed: 237 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 60/284 13/32 DLCround-PT-07b-CTLFireability-10 1632954 m, 29766 m/sec, 7060247 t fired, .
Time elapsed: 242 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 65/284 14/32 DLCround-PT-07b-CTLFireability-10 1758568 m, 25122 m/sec, 7647697 t fired, .
Time elapsed: 247 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 70/284 15/32 DLCround-PT-07b-CTLFireability-10 1878948 m, 24076 m/sec, 8232146 t fired, .
Time elapsed: 252 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 75/284 15/32 DLCround-PT-07b-CTLFireability-10 1999604 m, 24131 m/sec, 8817718 t fired, .
Time elapsed: 257 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 80/284 16/32 DLCround-PT-07b-CTLFireability-10 2103654 m, 20810 m/sec, 9406844 t fired, .
Time elapsed: 262 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 85/284 17/32 DLCround-PT-07b-CTLFireability-10 2219789 m, 23227 m/sec, 9992334 t fired, .
Time elapsed: 267 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 90/284 18/32 DLCround-PT-07b-CTLFireability-10 2340976 m, 24237 m/sec, 10577862 t fired, .
Time elapsed: 272 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 95/284 19/32 DLCround-PT-07b-CTLFireability-10 2446603 m, 21125 m/sec, 11167881 t fired, .
Time elapsed: 277 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 100/284 20/32 DLCround-PT-07b-CTLFireability-10 2561370 m, 22953 m/sec, 11756916 t fired, .
Time elapsed: 282 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 105/284 20/32 DLCround-PT-07b-CTLFireability-10 2683110 m, 24348 m/sec, 12345654 t fired, .
Time elapsed: 287 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 110/284 21/32 DLCround-PT-07b-CTLFireability-10 2791482 m, 21674 m/sec, 12938420 t fired, .
Time elapsed: 292 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 115/284 22/32 DLCround-PT-07b-CTLFireability-10 2892624 m, 20228 m/sec, 13533468 t fired, .
Time elapsed: 297 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 120/284 23/32 DLCround-PT-07b-CTLFireability-10 2992254 m, 19926 m/sec, 14125928 t fired, .
Time elapsed: 302 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 125/284 23/32 DLCround-PT-07b-CTLFireability-10 3090237 m, 19596 m/sec, 14716341 t fired, .
Time elapsed: 307 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 130/284 24/32 DLCround-PT-07b-CTLFireability-10 3177498 m, 17452 m/sec, 15309729 t fired, .
Time elapsed: 312 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 135/284 25/32 DLCround-PT-07b-CTLFireability-10 3315122 m, 27524 m/sec, 15884357 t fired, .
Time elapsed: 317 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 140/284 26/32 DLCround-PT-07b-CTLFireability-10 3458544 m, 28684 m/sec, 16456312 t fired, .
Time elapsed: 322 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 145/284 27/32 DLCround-PT-07b-CTLFireability-10 3586299 m, 25551 m/sec, 17033235 t fired, .
Time elapsed: 327 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 150/284 28/32 DLCround-PT-07b-CTLFireability-10 3739245 m, 30589 m/sec, 17606936 t fired, .
Time elapsed: 332 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 155/284 29/32 DLCround-PT-07b-CTLFireability-10 3867066 m, 25564 m/sec, 18185666 t fired, .
Time elapsed: 337 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 160/284 30/32 DLCround-PT-07b-CTLFireability-10 3986540 m, 23894 m/sec, 18764029 t fired, .
Time elapsed: 342 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 165/284 30/32 DLCround-PT-07b-CTLFireability-10 4106068 m, 23905 m/sec, 19342704 t fired, .
Time elapsed: 347 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 170/284 31/32 DLCround-PT-07b-CTLFireability-10 4211188 m, 21024 m/sec, 19922838 t fired, .
Time elapsed: 352 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 175/284 32/32 DLCround-PT-07b-CTLFireability-10 4339533 m, 25669 m/sec, 20500877 t fired, .
Time elapsed: 357 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for DLCround-PT-07b-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 362 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 38 (type EXCL) for 35 DLCround-PT-07b-CTLFireability-09
lola: time limit : 294 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/294 5/32 DLCround-PT-07b-CTLFireability-09 434395 m, 86879 m/sec, 498696 t fired, .
Time elapsed: 367 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 10/294 9/32 DLCround-PT-07b-CTLFireability-09 860078 m, 85136 m/sec, 993996 t fired, .
Time elapsed: 372 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 15/294 14/32 DLCround-PT-07b-CTLFireability-09 1283741 m, 84732 m/sec, 1487408 t fired, .
Time elapsed: 377 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 20/294 18/32 DLCround-PT-07b-CTLFireability-09 1713937 m, 86039 m/sec, 1983630 t fired, .
Time elapsed: 382 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 25/294 22/32 DLCround-PT-07b-CTLFireability-09 2136866 m, 84585 m/sec, 2475046 t fired, .
Time elapsed: 387 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 30/294 27/32 DLCround-PT-07b-CTLFireability-09 2565750 m, 85776 m/sec, 2968940 t fired, .
Time elapsed: 392 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 35/294 32/32 DLCround-PT-07b-CTLFireability-09 2993977 m, 85645 m/sec, 3462284 t fired, .
Time elapsed: 397 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 38 (type EXCL) for DLCround-PT-07b-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 402 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 33 (type EXCL) for 32 DLCround-PT-07b-CTLFireability-08
lola: time limit : 319 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 5/319 5/32 DLCround-PT-07b-CTLFireability-08 445067 m, 89013 m/sec, 511165 t fired, .
Time elapsed: 407 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 10/319 10/32 DLCround-PT-07b-CTLFireability-08 876825 m, 86351 m/sec, 1013714 t fired, .
Time elapsed: 412 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 15/319 14/32 DLCround-PT-07b-CTLFireability-08 1301732 m, 84981 m/sec, 1508632 t fired, .
Time elapsed: 417 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 20/319 18/32 DLCround-PT-07b-CTLFireability-08 1732359 m, 86125 m/sec, 2004968 t fired, .
Time elapsed: 422 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 25/319 23/32 DLCround-PT-07b-CTLFireability-08 2157336 m, 84995 m/sec, 2498122 t fired, .
Time elapsed: 427 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 30/319 27/32 DLCround-PT-07b-CTLFireability-08 2587947 m, 86122 m/sec, 2994708 t fired, .
Time elapsed: 432 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 35/319 32/32 DLCround-PT-07b-CTLFireability-08 3018171 m, 86044 m/sec, 3490296 t fired, .
Time elapsed: 437 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 33 (type EXCL) for DLCround-PT-07b-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 442 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 30 (type EXCL) for 29 DLCround-PT-07b-CTLFireability-07
lola: time limit : 350 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 5/350 5/32 DLCround-PT-07b-CTLFireability-07 354426 m, 70885 m/sec, 393780 t fired, .
Time elapsed: 447 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 10/350 8/32 DLCround-PT-07b-CTLFireability-07 690328 m, 67180 m/sec, 773638 t fired, .
Time elapsed: 452 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 15/350 11/32 DLCround-PT-07b-CTLFireability-07 1024460 m, 66826 m/sec, 1153376 t fired, .
Time elapsed: 457 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 20/350 15/32 DLCround-PT-07b-CTLFireability-07 1363867 m, 67881 m/sec, 1531334 t fired, .
Time elapsed: 462 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 25/350 19/32 DLCround-PT-07b-CTLFireability-07 1700860 m, 67398 m/sec, 1906676 t fired, .
Time elapsed: 467 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 30/350 24/32 DLCround-PT-07b-CTLFireability-07 2044077 m, 68643 m/sec, 2290723 t fired, .
Time elapsed: 472 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 35/350 30/32 DLCround-PT-07b-CTLFireability-07 2376386 m, 66461 m/sec, 2676193 t fired, .
Time elapsed: 477 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 30 (type EXCL) for DLCround-PT-07b-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 482 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 24 (type EXCL) for 19 DLCround-PT-07b-CTLFireability-05
lola: time limit : 389 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 5/389 5/32 DLCround-PT-07b-CTLFireability-05 442396 m, 88479 m/sec, 509950 t fired, .
Time elapsed: 487 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 10/389 10/32 DLCround-PT-07b-CTLFireability-05 873747 m, 86270 m/sec, 1011993 t fired, .
Time elapsed: 492 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 15/389 14/32 DLCround-PT-07b-CTLFireability-05 1297724 m, 84795 m/sec, 1505872 t fired, .
Time elapsed: 497 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 20/389 18/32 DLCround-PT-07b-CTLFireability-05 1729290 m, 86313 m/sec, 2003289 t fired, .
Time elapsed: 502 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 25/389 23/32 DLCround-PT-07b-CTLFireability-05 2153592 m, 84860 m/sec, 2495853 t fired, .
Time elapsed: 507 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 30/389 27/32 DLCround-PT-07b-CTLFireability-05 2583759 m, 86033 m/sec, 2991722 t fired, .
Time elapsed: 512 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 35/389 32/32 DLCround-PT-07b-CTLFireability-05 3012639 m, 85776 m/sec, 3485856 t fired, .
Time elapsed: 517 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 24 (type EXCL) for DLCround-PT-07b-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 522 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 19 DLCround-PT-07b-CTLFireability-05
lola: time limit : 439 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for DLCround-PT-07b-CTLFireability-05
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 DLCround-PT-07b-CTLFireability-03
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for DLCround-PT-07b-CTLFireability-03
lola: result : true
lola: markings : 816
lola: fired transitions : 819
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-07b-CTLFireability-00
lola: time limit : 615 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/615 5/32 DLCround-PT-07b-CTLFireability-00 442941 m, 88588 m/sec, 508691 t fired, .
Time elapsed: 527 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/615 10/32 DLCround-PT-07b-CTLFireability-00 872351 m, 85882 m/sec, 1008388 t fired, .
Time elapsed: 532 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/615 14/32 DLCround-PT-07b-CTLFireability-00 1295706 m, 84671 m/sec, 1501602 t fired, .
Time elapsed: 537 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/615 18/32 DLCround-PT-07b-CTLFireability-00 1726280 m, 86114 m/sec, 1997835 t fired, .
Time elapsed: 542 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/615 23/32 DLCround-PT-07b-CTLFireability-00 2149585 m, 84661 m/sec, 2489430 t fired, .
Time elapsed: 547 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/615 27/32 DLCround-PT-07b-CTLFireability-00 2578603 m, 85803 m/sec, 2983858 t fired, .
Time elapsed: 552 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/615 32/32 DLCround-PT-07b-CTLFireability-00 3006728 m, 85625 m/sec, 3477144 t fired, .
Time elapsed: 557 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for DLCround-PT-07b-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-06: EG 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 562 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 27 (type EXCL) for 26 DLCround-PT-07b-CTLFireability-06
lola: time limit : 759 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for DLCround-PT-07b-CTLFireability-06
lola: result : true
lola: markings : 120
lola: fired transitions : 120
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 35 DLCround-PT-07b-CTLFireability-09
lola: time limit : 1012 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/1012 3/32 DLCround-PT-07b-CTLFireability-09 489838 m, 97967 m/sec, 1719867 t fired, .
Time elapsed: 567 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/1012 6/32 DLCround-PT-07b-CTLFireability-09 955684 m, 93169 m/sec, 3432170 t fired, .
Time elapsed: 572 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/1012 9/32 DLCround-PT-07b-CTLFireability-09 1437755 m, 96414 m/sec, 5133003 t fired, .
Time elapsed: 577 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/1012 11/32 DLCround-PT-07b-CTLFireability-09 1900633 m, 92575 m/sec, 6822100 t fired, .
Time elapsed: 582 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/1012 14/32 DLCround-PT-07b-CTLFireability-09 2370056 m, 93884 m/sec, 8453229 t fired, .
Time elapsed: 587 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 30/1012 16/32 DLCround-PT-07b-CTLFireability-09 2813490 m, 88686 m/sec, 10074973 t fired, .
Time elapsed: 592 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 35/1012 19/32 DLCround-PT-07b-CTLFireability-09 3266454 m, 90592 m/sec, 11698290 t fired, .
Time elapsed: 597 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 40/1012 21/32 DLCround-PT-07b-CTLFireability-09 3727878 m, 92284 m/sec, 13340320 t fired, .
Time elapsed: 602 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 45/1012 24/32 DLCround-PT-07b-CTLFireability-09 4203618 m, 95148 m/sec, 15009418 t fired, .
Time elapsed: 607 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 50/1012 26/32 DLCround-PT-07b-CTLFireability-09 4642427 m, 87761 m/sec, 16618216 t fired, .
Time elapsed: 612 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 55/1012 29/32 DLCround-PT-07b-CTLFireability-09 5067642 m, 85043 m/sec, 18219511 t fired, .
Time elapsed: 617 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 60/1012 31/32 DLCround-PT-07b-CTLFireability-09 5510827 m, 88637 m/sec, 19818398 t fired, .
Time elapsed: 622 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 40 (type EXCL) for DLCround-PT-07b-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07b-CTLFireability-05: CONJ 0 0 0 0 3 0 1 0
DLCround-PT-07b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-09: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-07b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 627 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 70 (type EXCL) for 69 DLCround-PT-07b-CTLFireability-15
lola: time limit : 1486 sec
lola: memory limit: 32 pages
lola: FINISHED task # 70 (type EXCL) for DLCround-PT-07b-CTLFireability-15
lola: result : false
lola: markings : 8
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 DLCround-PT-07b-CTLFireability-02
lola: time limit : 2973 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for DLCround-PT-07b-CTLFireability-02
lola: result : false
lola: markings : 13
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-CTLFireability-00: CTL unknown AGGR
DLCround-PT-07b-CTLFireability-01: CTL unknown AGGR
DLCround-PT-07b-CTLFireability-02: CTL false CTL model checker
DLCround-PT-07b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-07b-CTLFireability-04: DISJ true findpath
DLCround-PT-07b-CTLFireability-05: CONJ unknown CONJ
DLCround-PT-07b-CTLFireability-06: EG true state space / EG
DLCround-PT-07b-CTLFireability-07: CTL unknown AGGR
DLCround-PT-07b-CTLFireability-08: CTL unknown AGGR
DLCround-PT-07b-CTLFireability-09: CONJ unknown CONJ
DLCround-PT-07b-CTLFireability-10: CTL unknown AGGR
DLCround-PT-07b-CTLFireability-11: CONJ false CTL model checker
DLCround-PT-07b-CTLFireability-12: CTL unknown AGGR
DLCround-PT-07b-CTLFireability-13: AFAG false CTL model checker
DLCround-PT-07b-CTLFireability-14: CTL unknown AGGR
DLCround-PT-07b-CTLFireability-15: CTL false CTL model checker
Time elapsed: 627 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-07b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-07b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478600690"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-07b.tgz
mv DLCround-PT-07b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;