Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478200378.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DES-PT-02a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478200378
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 536K
-rw-r--r-- 1 mcc users 6.9K Feb 26 15:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 26 15:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 26 15:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 15:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 15:50 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:50 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 15:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 153K Feb 26 15:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.7K Feb 26 15:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Feb 26 15:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 15:50 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:50 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 33K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DES-PT-02a-CTLFireability-00
FORMULA_NAME DES-PT-02a-CTLFireability-01
FORMULA_NAME DES-PT-02a-CTLFireability-02
FORMULA_NAME DES-PT-02a-CTLFireability-03
FORMULA_NAME DES-PT-02a-CTLFireability-04
FORMULA_NAME DES-PT-02a-CTLFireability-05
FORMULA_NAME DES-PT-02a-CTLFireability-06
FORMULA_NAME DES-PT-02a-CTLFireability-07
FORMULA_NAME DES-PT-02a-CTLFireability-08
FORMULA_NAME DES-PT-02a-CTLFireability-09
FORMULA_NAME DES-PT-02a-CTLFireability-10
FORMULA_NAME DES-PT-02a-CTLFireability-11
FORMULA_NAME DES-PT-02a-CTLFireability-12
FORMULA_NAME DES-PT-02a-CTLFireability-13
FORMULA_NAME DES-PT-02a-CTLFireability-14
FORMULA_NAME DES-PT-02a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678248132874

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DES-PT-02a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 04:02:14] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 04:02:14] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 04:02:14] [INFO ] Load time of PNML (sax parser for PT used): 41 ms
[2023-03-08 04:02:14] [INFO ] Transformed 123 places.
[2023-03-08 04:02:14] [INFO ] Transformed 80 transitions.
[2023-03-08 04:02:14] [INFO ] Found NUPN structural information;
[2023-03-08 04:02:14] [INFO ] Parsed PT model containing 123 places and 80 transitions and 400 arcs in 99 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Ensure Unique test removed 14 transitions
Reduce redundant transitions removed 14 transitions.
Support contains 88 out of 123 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 123/123 places, 66/66 transitions.
Applied a total of 0 rules in 11 ms. Remains 123 /123 variables (removed 0) and now considering 66/66 (removed 0) transitions.
// Phase 1: matrix 66 rows 123 cols
[2023-03-08 04:02:14] [INFO ] Computed 59 place invariants in 16 ms
[2023-03-08 04:02:15] [INFO ] Implicit Places using invariants in 460 ms returned [20]
Discarding 1 places :
Implicit Place search using SMT only with invariants took 488 ms to find 1 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 122/123 places, 66/66 transitions.
Applied a total of 0 rules in 10 ms. Remains 122 /122 variables (removed 0) and now considering 66/66 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 509 ms. Remains : 122/123 places, 66/66 transitions.
Support contains 88 out of 122 places after structural reductions.
[2023-03-08 04:02:15] [INFO ] Flatten gal took : 51 ms
[2023-03-08 04:02:15] [INFO ] Flatten gal took : 13 ms
[2023-03-08 04:02:15] [INFO ] Input system was already deterministic with 66 transitions.
Incomplete random walk after 10000 steps, including 251 resets, run finished after 376 ms. (steps per millisecond=26 ) properties (out of 74) seen :70
Incomplete Best-First random walk after 10001 steps, including 44 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 52 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10000 steps, including 52 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 53 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 4) seen :1
Running SMT prover for 3 properties.
// Phase 1: matrix 66 rows 122 cols
[2023-03-08 04:02:16] [INFO ] Computed 58 place invariants in 13 ms
[2023-03-08 04:02:16] [INFO ] [Real]Absence check using 33 positive place invariants in 5 ms returned sat
[2023-03-08 04:02:16] [INFO ] [Real]Absence check using 33 positive and 25 generalized place invariants in 5 ms returned sat
[2023-03-08 04:02:16] [INFO ] After 87ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:2
[2023-03-08 04:02:16] [INFO ] [Nat]Absence check using 33 positive place invariants in 5 ms returned sat
[2023-03-08 04:02:16] [INFO ] [Nat]Absence check using 33 positive and 25 generalized place invariants in 6 ms returned sat
[2023-03-08 04:02:16] [INFO ] After 65ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :2
[2023-03-08 04:02:16] [INFO ] Deduced a trap composed of 9 places in 28 ms of which 4 ms to minimize.
[2023-03-08 04:02:16] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 42 ms
[2023-03-08 04:02:16] [INFO ] After 140ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :2
Attempting to minimize the solution found.
Minimization took 37 ms.
[2023-03-08 04:02:16] [INFO ] After 270ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :2
Fused 3 Parikh solutions to 2 different solutions.
Parikh walk visited 1 properties in 6 ms.
Support contains 4 out of 122 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 122/122 places, 66/66 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 122 transition count 64
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 3 place count 121 transition count 63
Iterating global reduction 1 with 1 rules applied. Total rules applied 4 place count 121 transition count 63
Partial Free-agglomeration rule applied 6 times.
Drop transitions removed 6 transitions
Iterating global reduction 1 with 6 rules applied. Total rules applied 10 place count 121 transition count 63
Applied a total of 10 rules in 24 ms. Remains 121 /122 variables (removed 1) and now considering 63/66 (removed 3) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 24 ms. Remains : 121/122 places, 63/66 transitions.
Incomplete random walk after 10000 steps, including 152 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 29 resets, run finished after 13 ms. (steps per millisecond=769 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2259402 steps, run timeout after 3001 ms. (steps per millisecond=752 ) properties seen :{}
Probabilistic random walk after 2259402 steps, saw 296399 distinct states, run finished after 3002 ms. (steps per millisecond=752 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 63 rows 121 cols
[2023-03-08 04:02:19] [INFO ] Computed 60 place invariants in 9 ms
[2023-03-08 04:02:19] [INFO ] [Real]Absence check using 35 positive place invariants in 5 ms returned sat
[2023-03-08 04:02:19] [INFO ] [Real]Absence check using 35 positive and 25 generalized place invariants in 5 ms returned sat
[2023-03-08 04:02:19] [INFO ] After 79ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 04:02:19] [INFO ] [Nat]Absence check using 35 positive place invariants in 12 ms returned sat
[2023-03-08 04:02:19] [INFO ] [Nat]Absence check using 35 positive and 25 generalized place invariants in 5 ms returned sat
[2023-03-08 04:02:19] [INFO ] After 42ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 04:02:19] [INFO ] State equation strengthened by 3 read => feed constraints.
[2023-03-08 04:02:19] [INFO ] After 22ms SMT Verify possible using 3 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-08 04:02:19] [INFO ] Deduced a trap composed of 6 places in 33 ms of which 1 ms to minimize.
[2023-03-08 04:02:19] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 53 ms
[2023-03-08 04:02:19] [INFO ] After 101ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 17 ms.
[2023-03-08 04:02:19] [INFO ] After 210ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished Parikh walk after 65 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=32 )
Parikh walk visited 1 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-08 04:02:19] [INFO ] Flatten gal took : 10 ms
[2023-03-08 04:02:19] [INFO ] Flatten gal took : 9 ms
[2023-03-08 04:02:19] [INFO ] Input system was already deterministic with 66 transitions.
Computed a total of 25 stabilizing places and 20 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Applied a total of 0 rules in 4 ms. Remains 122 /122 variables (removed 0) and now considering 66/66 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 122/122 places, 66/66 transitions.
[2023-03-08 04:02:19] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 66 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Applied a total of 0 rules in 2 ms. Remains 122 /122 variables (removed 0) and now considering 66/66 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 122/122 places, 66/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 66 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 9 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 3 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 2 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 3 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 3 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 3 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 3 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 3 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Applied a total of 0 rules in 2 ms. Remains 122 /122 variables (removed 0) and now considering 66/66 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 122/122 places, 66/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 66 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 7 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 3 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Reduce places removed 1 places and 1 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 120 transition count 64
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 120 transition count 64
Applied a total of 2 rules in 7 ms. Remains 120 /122 variables (removed 2) and now considering 64/66 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 120/122 places, 64/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Applied a total of 0 rules in 4 ms. Remains 122 /122 variables (removed 0) and now considering 66/66 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 122/122 places, 66/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 66 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 122/122 places, 66/66 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 121 transition count 65
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 121 transition count 65
Applied a total of 2 rules in 7 ms. Remains 121 /122 variables (removed 1) and now considering 65/66 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 121/122 places, 65/66 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:02:20] [INFO ] Input system was already deterministic with 65 transitions.
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 7 ms
[2023-03-08 04:02:20] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:02:20] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-08 04:02:20] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 122 places, 66 transitions and 333 arcs took 1 ms.
Total runtime 5920 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DES-PT-02a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA DES-PT-02a-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-02a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678248432027

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 13 (type EXCL) for 12 DES-PT-02a-CTLFireability-04
lola: time limit : 144 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 13 (type EXCL) for DES-PT-02a-CTLFireability-04
lola: result : false
lola: markings : 31
lola: fired transitions : 61
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 28 (type EXCL) for 27 DES-PT-02a-CTLFireability-09
lola: time limit : 150 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-02a-CTLFireability-04: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-02a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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DES-PT-02a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-02a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
DES-PT-02a-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/225 5/32 DES-PT-02a-CTLFireability-09 945968 m, 189193 m/sec, 5933613 t fired, .

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DES-PT-02a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
DES-PT-02a-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/225 8/32 DES-PT-02a-CTLFireability-09 1830120 m, 176830 m/sec, 11957890 t fired, .

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DES-PT-02a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
DES-PT-02a-CTLFireability-13: EFAG 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/225 12/32 DES-PT-02a-CTLFireability-09 2626397 m, 159255 m/sec, 18004326 t fired, .

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DES-PT-02a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-02a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/225 15/32 DES-PT-02a-CTLFireability-09 3466707 m, 168062 m/sec, 24266645 t fired, .

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28 CTL EXCL 25/225 19/32 DES-PT-02a-CTLFireability-09 4375910 m, 181840 m/sec, 30840003 t fired, .

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28 CTL EXCL 30/225 23/32 DES-PT-02a-CTLFireability-09 5287796 m, 182377 m/sec, 37398409 t fired, .

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28 CTL EXCL 40/225 30/32 DES-PT-02a-CTLFireability-09 7037134 m, 168053 m/sec, 50190786 t fired, .

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22 CTL EXCL 9/319 10/32 DES-PT-02a-CTLFireability-07 2196060 m, 209278 m/sec, 12251080 t fired, .

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47 CTL EXCL 5/3360 4/32 DES-PT-02a-CTLFireability-14 864516 m, 172903 m/sec, 6356306 t fired, .

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47 CTL EXCL 10/3360 7/32 DES-PT-02a-CTLFireability-14 1587809 m, 144658 m/sec, 12474227 t fired, .

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47 CTL EXCL 15/3360 10/32 DES-PT-02a-CTLFireability-14 2317916 m, 146021 m/sec, 18914467 t fired, .

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47 CTL EXCL 20/3360 13/32 DES-PT-02a-CTLFireability-14 3034286 m, 143274 m/sec, 25140160 t fired, .

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47 CTL EXCL 25/3360 16/32 DES-PT-02a-CTLFireability-14 3780416 m, 149226 m/sec, 31645104 t fired, .

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47 CTL EXCL 30/3360 20/32 DES-PT-02a-CTLFireability-14 4629188 m, 169754 m/sec, 38489657 t fired, .

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47 CTL EXCL 40/3360 27/32 DES-PT-02a-CTLFireability-14 6226888 m, 161851 m/sec, 51863678 t fired, .

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47 CTL EXCL 45/3360 30/32 DES-PT-02a-CTLFireability-14 7000627 m, 154747 m/sec, 58453728 t fired, .

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FINAL RESULTS
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DES-PT-02a-CTLFireability-13: EFAG true tscc_search
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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DES-PT-02a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DES-PT-02a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478200378"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DES-PT-02a.tgz
mv DES-PT-02a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;